JP2000322236A - Sort processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To designate a raising/lowering order of each sort key by inverting the bit of a designated key value different from the comparing function of a comparator for comparing the large/small relation of consecutive comparing object data of a data string so as to transmit to a sorting processor of an initial stage. SOLUTION: Designated keys 1 and 3 different from the comparing function of a comparator are raising-order-designated and a control part 19 receives designation on whether these keys are in a raising order or a lowering order from a host computer, interprets this and controls a key conversion part 20 to send data to a first sorting processor 11 by inverting the bit of the key 1 and the key 3. Thus, the sort processor can obtain a sort with respect to plural keys where the raising order and the lowering order are mixed in spite of having a function for only a lowering order sort.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sort processor and a sort processor for performing a sort of so-called sort processing of a large amount of data in database processing, business data processing and the like. In this specification, a processor that performs a partial sort process is called a sort processor, and a device that connects a plurality of sort processors in series and performs a complete sort process is called a sort processing device. It shall be.

[0002]

2. Description of the Related Art FIG. 6 shows, for example, "Information Processing" Vol. 3
3, No. 12 is a diagram showing a configuration of a computer system including a conventional sort processing device disclosed in P1416-1423, 1992. In the figure, 1 is a sort processing device, 2 is a system bus of a host computer, 3 is a main storage device of the host computer, 4 is a CPU of the host computer, 5 is a disk device for storing data on the host computer, and 6 is a host computer It is.

Hereinafter, the operation will be described with reference to the drawings. First, the general operation will be described. When a data processing request is generated in the host computer 6, the CPU 4 of the host computer 6 continuously retrieves data from the disk device 5 in which the target data is stored, and sorts it continuously via the system bus 2. Send to processing device 1. At this time, the main storage device 3 of the host computer 1 is used as an input / output buffer area as needed. In the sort processing device 1, when data is input, the sort process is performed, and the result is sent back to the host computer 6 via the system bus 2 again. The host computer 6 stores the returned result data in the disk device 5 in the same manner as at the time of input. Note that input of data to the sort processing device 1 and output of result data from the sort processing device 1 are executed in parallel.

Next, the operation of the sorting apparatus 1 will be described in detail. The sort processing device 1 continuously inputs a sequence of data sent from the host computer 6, rearranges the sequence in a specified order, and returns the result to the host computer 6 again. This situation will be described with reference to FIG. 5, which is also disclosed in the above-mentioned “information processing”. FIG. 7 is a diagram showing the configuration of the sort processing device 1 in FIG.
Is configured by connecting the sort processors 11, 12, 13, and 14 linearly. Each sort processor 11-1
4 includes data storage devices 15, 16, 17, and 1 respectively.
8 are connected. Reference numeral 21 denotes a host computer interface for exchanging data with the host computer 6 and exchanging processing instructions, and 19 denotes a control unit for controlling the entire sort processing apparatus 1. The sort processors 11 to 14 are respectively called a first-stage sort processor, a second-stage sort processor, a third-stage sort processor, and the like from the top. The i-th sort processor has storage devices each having a capacity of 2 ⁱ⁻¹ data.

Here, "8, 2, 1, 3, 5, 7, 7,
The operation will be described by taking as an example a case where data is input to the sort processing device 1 in the order of "6, 4,...". Two pieces are taken out, rearranged in a specified order, and sent to the next-stage sort processor, and the data input to the next-stage sort processor after being sorted by two are (8, 2), (3, 1), (7, 5), (6, 4),
... As described above, in the first-stage sort processor 11, the data input in the order of "1, 3" is replaced by the order, and becomes a set of two data sorted in the order of (3, 1). Has been output. The set of data sorted in this manner is hereinafter referred to as a data string or a string. The second-stage sort processor 12 inputs the data strings sorted by two, takes out two sets of the data strings, merges them, and
The data strings sorted into groups of four are sent to the sort processor 13 at the next stage. The result is (8, 3,
2, 1), (7, 6, 5, 4),... As described above, in the second-stage sort processor 12, the input data strings (8, 2) and (3, 1) are sorted, and as a result, the output data strings (8, 3,.
2, 1). The third stage sort processor 13
The data strings sorted into groups of four are input, extracted in pairs of two, merged, and the data strings sorted into groups of eight are sent to the sort processor 14 at the next stage. The results are (8, 7, 6, 5,
4, 3, 2, 1),. The same processing is performed for the fourth-stage sort processor 14 and thereafter.

By the way, as shown in FIG. 8, each stage of the sort processor can start the processing before the preceding stage of the sort processor has finished all the processing, whereby the data can be continuously read. It can be seen that the sorting result is output in parallel with the data input after a slight delay time when input. Thus, the rearrangement of 2 ⁿ data, that is, the sort processing is performed by the ⁿ sort processors. In addition, in these comparison and merging processes, each sort processor performs operations on the data storage devices 15 and 1 connected thereto.
6, 17, and 18 are used as storage areas.

Next, “information processing” shown in FIG. 3
1, No. 4, P457-465, 1990, the operation inside the sort processor will be described with reference to the configuration diagram of the conventional sort processor. Although FIG. 9 shows only the inside of the sort processor 12 in FIG. 7 for simplicity of description, the inside of the other sort processors has the same configuration. In FIG. 9, reference numeral 120 denotes a comparator for comparing data strings, 121 and 122 denote latch registers for temporarily storing a part of data to be compared, and 12
3, 124 are data input ports of the comparator 120, 125
Is a control unit for controlling the operation of the sort processor. The latch registers 121 and 122 have a data size equal to the comparison data size of the comparator 120 and the data width of the input ports 123 and 124 of the comparator. In the following description, this size is 4 bytes. 126 is an input bus for inputting data from the preceding sort processor 11;
127 is an output bus for outputting data to the next-stage sort processor 13, and 128 is the connected data storage device 1.
6 and an address and data bus for exchanging data with the data bus.

Hereinafter, the details of the sorting process of the sort processor 12 will be described. When the data strings (8, 2), (3, 1),... Are sequentially input from the preceding sort processor 11 to the sort processor 12,
An example will be described in which the sort processor 12 combines the data and outputs the data strings (8, 3, 2, 1) to the next-stage sort processor 13 as an example.

First, the data strings (8, 2) input first are stored in the data storage device 16 connected to the sort processor 12 while maintaining the same order. Next, the data “3” of the data string (3, 1)
Is input to the sort processor 12 and is similarly stored in the data storage device 16. Subsequently, the leading data “8” of the first data string (8, 2) and the leading data “3” of the data string (3, 1) are loaded from the data storage device 16 into the latch registers 121 and 122 by 4 bytes. Thus, the comparison is performed in the comparator 120. This comparison is performed by sequentially comparing data every four bytes.

In this sort processing, when ascending order is specified as the order specification for the sort key, the smaller of the comparison results is output first. Similarly, when the descending order is designated as the order designation, the larger one of the comparison results is output first. The control for these ascending and descending orders is performed by the control unit 125 for the sort key starting from the first byte of the data. When the comparison result is determined, the data is output to the next sort processor 13. In parallel with this comparison processing, the next data “1” in the second data string (3, 1)
Is stored in the data storage device 16. In the case of this example, as a result of the comparison, data “8” is output to the next-stage sort processor 13. Therefore, in the subsequent comparison, data "3" is compared with data "2" following "8" of data string (8, 2). The comparison is similarly performed by inputting data “3” and data “2” from the data storage device 16 to the latch registers 121 and 122 in 4-byte units, respectively.
Processed by performing byte-by-byte comparisons.

[0011]

Since the conventional sort processing apparatus is configured as described above, in the sort processing, a plurality of fields in a record are generally combined, and these fields are arranged in ascending and descending order. It is necessary to specify them independently and rearrange the data according to the specification. For this reason, in the control device of the sort processor,
It is necessary to interpret the ascending order and descending order for each of these multiple key fields and perform the processing accordingly.
There was a problem that hardware logic became complicated.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and the internal processing of a sort processor can be performed only in ascending or descending order while enabling the designation of ascending or descending order for each sort key in the sort processing. An object of the present invention is to simplify the internal configuration of a sort processor.

[0013]

According to the present invention, there is provided a sort processor comprising: a data storage device for storing an input data string; a comparator for comparing magnitude relations of successive comparison target data of the data string; A plurality of sort processors having a control unit for controlling the apparatus and the comparator are connected in series, and each sort processor operates in parallel, and performs a repetitive comparison process using each comparator. In a sort processing device that performs data sort processing, a key value conversion unit that inverts bits of the key value for a designated key value different from the comparison function of the comparator and transmits the inverted key value to the first-stage sort processor is provided. It was done.

Further, when the comparator is configured to take out the larger one of the data to be compared, the key value converter inverts the bits of the key value designated in descending order.

When the comparator is configured to take out the smaller one of the data to be compared, the key value converter inverts the bits of the key value specified in ascending order.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In this embodiment, a case where the number of data to be compared at a time is K = 4 and the data width to be compared is 4 bytes will be described. FIG. 1 is a diagram showing a connection relationship between sort processors according to the present invention. In the figure, reference numerals 11, 12, and 13 denote sort processors, and reference numerals 15, 16, and 17 denote data storage devices included in each sort processor for storing data strings to be sorted. Each sort processor 11-13
Is composed of four key storage areas 130 to 139 for storing data sort keys (hereinafter, referred to as key values), a latch register 140, a comparator 130, and a control unit 125 for controlling the entire sort processor. Note that the comparator 130 can be realized by combining a plurality of 2-input comparators without employing a special circuit configuration. Further, the latch register 140 may be configured by a general register.

Reference numeral 126 denotes a sort processor 1 in the preceding stage.
An input bus 127 for inputting data from 1 is an output bus for outputting data to the next sort processor 13,
Reference numeral 8 denotes an address and data bus for exchanging data with the connected data storage device 16. 136-1
Reference numeral 40 denotes an input port of the comparator 130. The latch register 140 is a register having a bit width to be compared by the comparator 130 at one time, and the key value storage units 131 to 134
Is composed of a register file, a memory element, and the like having a capacity capable of storing all the key value portions of data. In addition, the key value storage units 131, 132, 133, and 134 are referred to as first, second, third, and fourth key value storage units, respectively, for convenience.

First, a schematic operation in the sort processing of the sort processor configured as described above will be described. (1) The control unit 125 of the sort processor stores the key value of each data to be compared in the corresponding key value storage unit (131).
To 134). (2) If one data is output as a result of the comparison, the key value of the data next input from the data storage device 16 is
For example, the data is input to the latch register 135 in units of 4 bytes, and comparison is performed. At the same time, the same data is sequentially input to an empty key value storage. (3) At the start of the first comparison process of the comparison process repeatedly executed by each sort processor, each of the key values of three of the four data to be compared is stored in four key value storage units ( 131 to 134) in the three key value storage units (131 to 133), and the control unit in the sort processor sets these three key value storage units (1
Input ports (136 to 13) corresponding to the input ports (136 to 133)
8), the input port 140 connected to the latch register 135 is selected, and the comparison process is started at the same time when the leading part of the key value of the fourth data is stored in the latch register 135. In parallel, the key value of the fourth data is
The information is stored in the fourth key value storage unit 134. (4) In the comparison process that is not the first of the comparison processes repeatedly executed by each sort processor, the smallest data (in the case of ascending sort) is determined as a result of the comparison of the key values of the four data by the comparator 130. Then, in the next comparison, the key value of the next data in place of the output data is input to the latch register 135 to start the comparison and, in parallel, the key value of the output data. By storing the key value of this data in the key value storage unit in which has been stored, sorting is performed in ascending order. (5) In the case of the descending sort, the largest data is determined as a result of the comparison, and the largest data is output to realize the descending sort. (6) When the data input to the latch register 135 for comparison and simultaneously stored in the key value storage section is selected and output as a result of the ascending or descending comparison, the next data instead of this data is output. , The head of the key value is similarly input to the latch register 135 to start the comparison, and in parallel, the key value of the output data is stored in the key value storage unit. If a key value is input and this data is not selected or output as a result of the comparison, the key value of the next data instead of the output data is stored in the latch register 135 instead of this data. , The comparison is started, and in parallel, the key value of the output data is stored in the key value storage unit in which the key value of the data is stored. (7) When there is no more data replacing the output data, the control unit 125 does not subsequently select the input port of the comparator 130 corresponding to the key value storage unit in which the key value of the data has been stored. Is controlled so as not to be compared in the subsequent comparison.

FIG. 2 is a diagram showing a sort processing device constructed using the sort processor according to the present invention. The sort processing device 1 includes sort processors 11 to 14, data storage devices 15 to 18 for each sort processor, An interface unit 21 with the host computer for exchanging data with the host computer and exchanging processing instructions, a key conversion unit 20 for converting the value of a key part of data, and a sort process for controlling the entire sort processing device 1. Device control unit 1
9. The key conversion unit 20 is configured to be connected to the first sort processor 11. Hereinafter, the operation of this embodiment will be described with reference to the drawings. However, the data input from the host computer to the sort processing device 1 and the sort processing device 1 sorts the data and returns it to the host computer are the same. Yes, description is omitted.

First, the key conversion unit 20 according to the present invention will be described with reference to FIG. FIG. 2 has a configuration similar to that of FIG. 6 described in the conventional example, except that data storage devices 15, 16, 17, 1
8 and the internal configuration of each sort processor are different. The sort processing device 1 continuously inputs a sequence of data sent from the host computer, rearranges the data sequence in a specified order, and returns the result to the host computer again. The sort processing device includes sort processor groups 11, 12, 13,
14 and a data storage device group 15, 16, 17, 18 respectively added to the sort processor group are connected linearly, and a key conversion device 20 is connected before the leading sort processor 11.

In the sorting process, the data is rearranged based on the key values in the data. For example, assuming that the format of the data to be sorted is as follows, a case will be described in which the sort processor can perform only descending sort. Data format: key 1 + key 2 + key 3 + non-key data Here, keys 1 and 3 are specified in ascending order, and key 2 is in descending order. The control unit 19 receives designation of ascending order or descending order from the host computer for the keys 1 to 3,
By interpreting this, the key conversion unit 20 controls each input data to invert the bits of the keys 1 and 3 and send the data to the first sort processor 11. I do. As a result, even if the sort processor has only the function of sorting in descending order, it is possible to realize sorting for a plurality of keys in which ascending order and descending order are mixed as shown in the example.

A specific example will be described below. For example, when the key 1 of two data is “2” and “4”, these binary notations are “0010” and “0100”.
When these are sorted in ascending order, it is necessary to output them in the order of “2” and “4”. On the other hand, when these bits are bit-inverted, they are 1101 "and" 1011 ", which are decimal numbers" 13 "and" 11 ", respectively, so that a similar order can be obtained by sorting them in descending order.
If the sort processor has only the function of sorting in ascending order only, in this example, if the control unit 19 instructs the key conversion unit 20 to perform bit inversion on the key 2, Good.

Next, the operation of the sort processor will be described using a specific example. The sort processors are called a first-stage sort processor (P ₁ ), a second-stage sort processor (P ₂ ), a third-stage sort processor (P ₃ ), and the like, respectively, from the top. The i-th sort processor has a data storage device having a capacity of (K-1) K ^i-1 data. Hereinafter, the operation will be described with K = 4. As an example of the operation, the sort processing device 1, 8, 2, 1,.
3, 5, 7, 6, 4, 9, 0, 8, 5, 1, 10, 3,
When data is input in the order of 4,..., First, the first-stage sort processor 11
These are taken out one by one, rearranged and sent to the next-stage sort processor 12.

Here, data "8", "2",
“1”... Does not mean a decimal number, but is data composed of a key value and a data body (however, it may be composed of only a key value). Represents the size as The data input to the next-stage sort processor 12 after being sorted by four are (8, 3, 2, 1), (7, 6, 5, 4),
(9, 8, 5, 0), (10, 4, 3, 1), ...
Becomes

The second stage sort processor 12 outputs
The data sorted one by one is input, four sets are taken out, merged, and the data sequence sorted by 16 is sent to the sort processor 13 at the next stage. The results are (10, 9, 8, 8, 7, 6, 5, 5, 4, 4, 3,
3, 2, 1, 1, 0),. The same processing is performed for the third-stage sort processor 13 and thereafter. This is shown in FIG. As in the prior art, as shown in FIG. 3, the sort processor in each stage can start processing before the sort processor in the preceding stage finishes all the processes, whereby data can be continuously output. It can be seen that when the input is made, the sort result is output in parallel with the input of the data after a slight delay time.

In this manner, the rearrangement of K ⁿ data, that is, the sort processing is performed by the ⁿ sort processors. Stated another way, the sorting of N data is implemented by log _K N sort processors. For example, in order to sort 2 ²⁰ = 4 ¹⁰ = 1 million data, 20 sort processors are required in the conventional method of comparing two data, but in the present method in which K = 4, the sort processor is not used. It turns out that ten pieces are enough. Note that each sort processor performs the comparison and merging process by using the data storage devices 15, 16, 1
7, 18 are used as storage areas.

Next, the internal operation of the sort processor will be described with reference to FIG. Sort processor 1
2, the data strings (8, 3, 2, 1), (7, 6, 5, 4),
(9, 8, 5, 0), (10, 4, 3, 1)... Are input and sorted by the sort processor 12, and the data strings (10, 9, 8, 8, 7, 6, 6,
, 5, 5, 4, 4, 3, 3, 2, 1, 1, 0),... Will be described as an example.

First, the data strings (8, 3,...) Input from the input bus 126 to the sort processor 12 are input.
2, 1), (7, 6, 5, 4), (9, 8, 5, 0)
Is the sort processor 1 while maintaining the same order.
2 is stored in the data storage device 16 connected to the storage device 2. At this time, in parallel with storing the data in the data storage device 16, the leading data "8" of the data string (8, 3, 2, 1) and the leading data of the data string (7, 6, 5, 4) "7", data string, (9, 8, 5, 0)
Are stored in the first, second, and third key value storage units 131, 132, and 133, respectively. At this point, of the four key value storage units, 4
The key value storage unit 134 is still empty.
Here, the fourth data string (10,
4, 3, and 1) are stored. 1st key value storage: 1st data string key value 2nd key value storage: 2nd data string key value 3rd key value storage: 3rd data string 4th key value storage unit: The correspondence is determined and fixed as in the 4th data string key value. The above operation is controlled by the control unit 125.

Next, the control unit 125 comprises a comparator 130 and its data input ports 136, 137, 138, 13
9 and 140, the first, second and third key value storage units 136, 137 and 138 corresponding to the first K-1 of the key value storage units storing the key values, and the latch register 135. Is set so that the comparator 130 compares data (key value) input from the data input port 140 connected to the. Subsequently, the remaining fourth data string (10, 4, 3, 1) is sequentially input to the input bus 126 from the preceding sort processor 11. First, the sort processor 12 first outputs the data “10”
Are stored in the latch register 135 in order of 4 bytes at a time, and the comparison is performed 4 bytes at a time. At the same time, the key value portion of the input data is stored in the empty key value storage unit 134.

With a little supplement, the latch register 13
When the first 4 bytes of the key value of the data “10” are stored in 5, the comparison by the simultaneous comparator 130 starts. In this example, since the data “10” is the largest, the data “10” Are stored in the latch register 135 in order of 4 bytes. In addition, data “1”
0 "as in the other data strings.
6 may be stored.

In the comparator 130, "8",
“7”, “9”, and “10” are compared. As a result, the largest data "10" is output. When the data input to the latch register 135 is directly output to the next stage as a result of the comparison as in this example, first, the key portion of this data is output from the comparator 130 and the data output bus 127 is output as it is. Is output to the sort processor 13 at the next stage. Subsequently, when there is a non-key data portion in this data, the non-key value data portion of this data input from the data input bus 126 is output through the data output bus 127 as it is. These controls are performed by the control unit 125.

Subsequently, data “4” following data “10” of the fourth data string is input from the input bus 126. As in the case of the data “10”, this data is input to the latch register 135 in 4-byte units, and the data “8”, “7”, “9” in the key value storage units 131, 132, and 133 are stored in 4 bytes. Are compared one by one. At the same time as the input to the latch register 135, the key value of the data "4" is stored in the vacant key value storage unit 13.
4 is stored. In this comparison, the data “9” stored in the key value storage 133 is output as a result of the comparison, instead of the data “4” input to the latch register 135. Therefore, in this case, first, the key value portion of the data “9” is output from the comparator 130 to the next-stage sort processor 13 via the data output bus 127. Subsequently, when there is a non-key data portion of the data “9”, the non-key value portion of the data “9” is read from the data storage device 16 and the data output bus 1
These are output to the sort processor 13 of the next stage via 27. When the comparison of the key values is completed, if there is a non-key data portion following the key value in the data “4”, these data portions sent from the preceding sort processor 11 by the data input bus 126 are Are sent to the data storage device 16 and stored therein.

At this stage, the key value of data "4" is stored in the key value storage unit 134 which was previously empty (output to the next-stage sort processor and unnecessary data remains). On the other hand, the key value storage unit 133 in which the key value of “9” was stored is vacant. Therefore, the control unit 125 sends the data input ports 136, 137, 139,
The setting is made so as to compare the data from 140. When the setting is completed, the key value of the data “8” following the data “9” of the data string (9, 8, 5, 0) is stored in the latch register 135 connected to the comparator 130 from the data storage device 16. Are read out and stored in units of 4 bytes, and compared with the data “8”, “7”, and “4” stored in the other key value storage units 131, 132, and 134, respectively, in the comparator 130 in units of 4 bytes. Is done. This comparison operation starts as soon as the first four bytes of the key value of data “8” are stored in the latch register 135. At the same time as storing the key value of data “8” in the latch register 135, the same key value is stored in the vacant key value storage unit 133. Further, at the same time, the data is sent from the preceding sort processor 11 by the data input bus 126 (10,
Data “3” following “4” in (4, 3, 1) is stored in the data storage device 16.

FIG. 4 illustrates the flow of data in the sort processing described above. In the figure, 10 _K indicates the key value of the data “10”, and 10 _K −1 and 10 _K −2 indicate the first 4 bytes and the next 4 bytes of the key value of the data “10”, respectively. Also, the example of this figure shows a case where the key value is 8 bytes (4 bytes * 2).

In the above description, the data "9"
Is output, the key value portion of the data “8” is read from the data storage device 16 and stored in the key value storage unit 133.
Also, the description has been made such that the key value is stored in the latch register in order of 4 bytes. However, in the operation of the sort processor shown in FIG. 1, the control unit 125 is connected to the key value storage unit. This is performed using the bus in a time-sharing manner. Further, the data storage device 16 and the key value storage unit 131
To 134 and the latch register 135 may be connected by another bus.

By repeating the above operation, the sorting process is completed. Here, as the sort process approaches to completion, the data of the four data strings is lost. For example, in the case of this example, the data strings (8, 3, 2, 1), (7, 6, 5, 4), (9, 8,
5, 0), (10, 4, 3, 1)...
The sort processor 12 merges the data strings into data strings (10, 9, 8, 8, 7, 6, 5, 5, 4, 4, 3,.
3, 2, 1, 1, 0),..., But when two data “4” are output, the second data string (7, 6, 5, 4) is output. Data is,
This sort processor 12 is no longer present. For such a data string, the control unit 125 controls the comparator 130 so that the data from the corresponding key value storage unit is not compared.

Next, the configuration of the data storage devices 15 to 18 will be described. The data storage devices 15 to 18 are usually D
It is composed of a RAM. For example, 1 million, 64M
Considering that the B data is sorted, there is a difference as shown in FIG. 4 between the prior art and the present invention. FIG.
FIG. 5 is a diagram showing a comparison of the number of DRAMs required for a data storage device when data to be compared at a time is changed.
As described above, the present invention can reduce the amount of hardware compared to the prior art, and furthermore, the number K to be compared at a time by the comparator is determined by the capacity of the DRAM, for example, the capacity of 16 Mb.
It, the minimum unit for 4 DRAMs of 8 bit width is 8MB
It can be seen that hardware implementation that reduces the number of DRAMs is possible by selecting and implementing a divisor of this (4 in this case).

As described above, according to this embodiment,
It is possible to solve the problem of mounting the sort processor on the LSI, which is caused by the limitation of the number of pins of the LSI. Also, L
By solving the SI implementation problem, the number of sort processors required in the sort processing device is reduced, thereby reducing the hardware scale of the sort processing device and providing a sort processing device for sorting a fixed amount of data. It is possible to reduce the size. Further, it is possible to reduce the number of DRAMs of the data storage device used inside such a sort processing device, and to reduce the size of the sort processing device. In addition, even if the sort processor is configured according to the present invention, performance degradation due to an increase in the number of times the sort processor accesses the data storage device does not occur. Also, when the data input to the sort processing device has a plurality of sort keys, and the sort specification of the ascending order and the descending order is independently specified for each of the sort keys, the sort processor performs the processing for the single key. Only sort in descending or ascending order.
The hardware of the sort processor can be simplified.

[0039]

As described above, according to the present invention, the key value conversion section for inverting the key value data is provided, so that the comparator having the sort processor has the largest data among the data to be compared. Alternatively, only the function of selecting the smallest data may be provided.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a sort processor according to the present invention.

FIG. 2 is a diagram showing a configuration of a sort processing device configured using a sort processor according to the present invention.

FIG. 3 is a diagram showing a state of sorting by a sort processing device.

FIG. 4 is a diagram showing a data flow in a sort process of a sort processor.

FIG. 5 is a diagram showing a comparison between the data storage device and the required number of DRAMs when data to be compared at one time is changed.

FIG. 6 is a diagram showing a connection form of a conventional sort processing device with a host computer.

FIG. 7 is a diagram illustrating a configuration of a conventional sort processing device.

FIG. 8 is a diagram showing how data is sorted by a conventional sort processing device.

FIG. 9 is a diagram showing a sort processor used inside a conventional sort processing device.

FIG. 10 is a diagram for explaining performance degradation that occurs when the number of data to be compared at a time is increased from 2 to a number larger than 2 in a conventional sort processor.

[Explanation of symbols]

11, 12, 13, 14 sort processor, 15, 1
6, 17, 18 Data storage device, 19 Control unit of sort processing device, 20 Key conversion device, 125 Control unit inside sort processor, 130 Comparator, 131, 13
2, 133, 134 Key value storage, 135 Latch register, 136, 137, 138, 139140 Input port.

Claims (3)

[Claims] 1. A data storage device for storing an input data string, a comparator for comparing the magnitude relation of successive comparison target data of the data string, and a control unit for controlling the data storage device and the comparator. In a sort processing device that sorts a plurality of data by connecting a plurality of sort processors in series, each sort processor operates in parallel, and repeatedly performs a comparison process using each comparator. A sort processing device comprising: a key value conversion unit that inverts a bit of a specified key value different from a comparison function of a comparator and transmits the inverted key value to a first-stage sort processor. 2. The apparatus according to claim 1, wherein when the comparator is configured to take out the larger one of the data to be compared, the key value converter inverts the bits of the key value specified in descending order. 2. The sort processing device according to 1. 3. The key value conversion unit according to claim 1, wherein when the comparator is configured to take out the smaller one of the data to be compared, the key value conversion unit inverts the bits of the key value specified in ascending order. 2. The sort processing device according to 1.