JP2000315393A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the increase of the chip size by arranging elements storing data required for address conversion to relieve defects in a random access memory between a pad provided at the central part of a semiconductor substrate main surface and a random access memory. SOLUTION: In order to store a relief address in a memory mat MAT, an address signal formed by an address buffer circuit is converted to write-in data, and stored in a non-volatile memory element. In the layout of a large capacity mask ROM integrated circuit, a pad is arranged at the central part of a semiconductor substrate chip to prevent signal delay and noise caused by lengthening the power source line, the ground line and the signal line. As a space can be easily obtained in periphery of the pad, the non-volatile memory element storing a relief address is arranged here. Then, the increase of the chip size of a semiconductor substrate is prevented and characteristics variation caused by the stress at the time of sealing the substrate into a package is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology that is effective when used as a defect repair technology for a memory matrix including read-only memory cells.

[0002]

2. Description of the Related Art A technique using an EPROM (erasable & electrical read only memory) for relieving defects in a mask ROM and changing stored data is known.
A technique using a single-layer polysilicon gate structure as the EPROM is described in, for example, May 21, 1990.
Date IEICE Technical Report Vol. 90, No. 4
7, pages 51 to 53. A technique using a two-layer gate structure as the EPROM is described in, for example, JP-A-61-47671.

[0003]

The inventors of the present invention have analyzed the data retention characteristics of an EPROM and found that the following phenomena existed. FIG.
2 shows data holding characteristics of EPROMs having different structures. In the figure, the horizontal axis represents time,
The vertical axis indicates the rate of change of the threshold voltage [ΔVth _t ÷ ΔVth ₀ × 1
00]%. Here, ΔVth ₀ indicates a threshold voltage at the time of writing, and ΔVth _t indicates a threshold voltage after elapse of t time. In addition, data retention characteristics in an environment where the device is left in air at a temperature of 300 ° C. are examined.

In FIG. 16, the element structure having a characteristic B is an EPROM having a single-layer polysilicon gate structure, and the characteristic D is an EPROM having a two-layer gate structure. The inventor of the present application does not mean that the control gate in the two-layer gate structure acts as a barrier layer to prevent the reduction of information charges accumulated in the floating gate due to the difference in data retention characteristics between the two EPROMs. I guessed.

In order to confirm this, an EPROM having a single-layer polysilicon gate structure in which an aluminum layer is provided on the entire upper surface of the floating gate made of the single-layer polysilicon is formed. Thus, a significant improvement in data retention characteristics was observed. In addition, a plasma-C
It has been found that when an oxide film (P-SiO) formed by the VD method is provided, good data retention characteristics such as characteristic C can be obtained. The oxide film (P-SiO) is formed as an interlayer insulating film for a two-layer aluminum wiring. That is, the first aluminum layer is formed on the BPSG film, and the oxide film (P-
This is an EPROM having a two-layer gate structure in which a second aluminum layer is formed via SiO).

From a result of careful analysis of the relationship between the element structure and the data retention characteristics as described above, a nonvolatile memory device having a single-layer gate structure with improved data retention characteristics and a semiconductor integrated circuit device using the same are disclosed. The invention has been made.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device whose defect can be relieved, changed in function, or trimmed with high reliability and simple manufacturing. Another object of the present invention is to provide a semiconductor integrated circuit device provided with a nonvolatile memory element having a single-layer gate structure for improving data retention characteristics. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a microprocessor, an input / output port, a RAM and its RAM are provided on a main surface of a semiconductor substrate.
And an element for storing data necessary for address conversion for relieving defects, and a pad in the center of the main surface and the element between the pad and the RAM.

[0009]

FIG. 1 is a sectional view showing a manufacturing process for explaining a nonvolatile memory element according to the present invention.
Shown with OSFET. In this specification, MOSFET is used to mean an insulated gate field effect transistor (IGFET).

1A to 1D, a nonvolatile memory element Q having a single-layer polysilicon gate structure from the left side.
E, N-channel MOSFET QN, P-channel MO
The SFET QP is shown. N-channel MOSFE
The TQN and the P-channel MOSFET QP include peripheral circuits such as an address selection circuit of the nonvolatile memory element QE,
It is used to configure other memory circuits and digital circuits formed on the same semiconductor substrate as the EPROM according to the present invention. The nonvolatile memory element QE is a cross-sectional view in which the left side is perpendicular to the source and the drain and the right side is parallel.

In FIG. 1A, a P-type well 2 and an N-type well 102 are formed on one main surface of a P-type semiconductor substrate 1 by a known means. Next, a thick field insulating film 3 and a P-channel stopper 4 indicated by a dotted line in FIG.

In FIG. 1B, a nonvolatile memory element Q
An N-type diffusion layer 6 to be an E control gate is formed. Although the N-type diffusion layer 6 is not particularly limited, after phosphorus is implanted at about 1 × 10 ¹⁴ cm ⁻² at an acceleration energy of 80 Kev through the insulating film 5 by ion implantation, about 1% of oxygen is introduced into nitrogen. Is formed by performing a heat treatment at a temperature of 950 ° C. for about 30 minutes in an atmosphere containing. Of course, arsenic alone or both arsenic and phosphorus may be used as impurities. Although it is basically unnecessary to perform the heat treatment, it is better to perform the heat treatment in order to recover the semiconductor substrate 1 damaged by the ion implantation.

Next, after the insulating film 5 damaged by the ion implantation is removed, a clean gate insulating film 7 is formed by a thermal oxidation method. At this time, the thickness of the gate insulating film 7 on the N-type diffusion layer 6 is formed to be about 10 to 20% thicker than the region without the N-type diffusion layer 6.

Then, a conductor layer 8 serving as a floating gate of the nonvolatile memory element QE and gate electrodes of the N-channel MOSFET QN and the P-channel MOSFET QP is formed. The conductor layer 8 is composed of a polycrystalline silicon (polysilicon) film or a polycide film in which a silicide film is laminated on the polycrystalline silicon film.

As shown in FIG. 1C, N-type diffusion layers 9 and 10 and a P-type diffusion layer 109 are formed. The N-type diffusion layer 9 has an acceleration energy of 50 KeV by ion implantation.
At about 2 × 10 ¹³ cm ⁻² . The N-type diffusion layer 10 is formed by implanting about 5 × 10 ¹⁵ cm ^{−2 of} phosphorus at an acceleration energy of 50 Kev by an ion implantation method. The P-type diffusion layer 109 is formed by ion implantation at an acceleration energy of 15 KeV and 1 × boron.
It is formed by implanting about 10 ¹³ cm ^-2 .

Next, after a CVD insulating film is formed on the entire surface, a sidewall 11 is formed by anisotropic etching. Then, an N-type diffusion layer 12 and a P-type diffusion layer 112 are formed. The N-type diffusion layer 12 is formed by implanting about 5 × 10 ¹⁵ cm ^{−2 of} arsenic at an acceleration energy of 80 Kev by an ion implantation method. The P-type diffusion layer 112 has an acceleration energy of 15 Ke
It is formed by implanting about 2 × 10 ¹⁵ cm ⁻² at v. In this embodiment, the N-type diffusion layer 10 has been described to be formed before the formation of the side wall 11, but may be formed after the formation of the side wall 11. Further, the manufacturing process of the P-type diffusion layer 109 may be omitted, and the P-type diffusion layer 112 may be formed before the formation of the sidewall 11. In this case, the N-type diffusion layer 9
It can be formed by ion implantation over the entire surface without using a mask.

In FIG. 1D, a nonvolatile memory element Q
E denotes a single-layer gate in which a control gate is formed by diffusion layers 6 and 10, a floating gate 8, a gate insulating film 7, an interlayer insulating film 7 between the control gate and the floating gate, and a source and a drain are formed by an N-type diffusion layer 10. Structured. The reason why the source and the drain are formed by the N-type diffusion layer 10 is to improve the writing characteristics.

The N-type diffusion layer 10 has the same configuration as the source and drain of the N-channel MOSFET QN constituting the input / output. The N-channel MOSFET QN has a so-called LDD structure in which a gate electrode 8, a gate insulating film 7, and sources and drains are constituted by N-type diffusion layers 9 and 12. The P-channel MOSFET QP has a so-called LDD structure in which the gate electrode 8, the gate insulating film 7, and the source and the drain are constituted by the P-type diffusion layers 109 and 112.

Each element is separated by a field insulating film 3 and a P-type channel stopper 4.
Each element is connected by a wiring 15 made of aluminum through a contact hole formed in the insulating film 13. The N-type diffusion layers 6 and 10, which are control gates of the nonvolatile element QE, are shunted by the wiring 15 to reduce parasitic resistance. That is, the wiring 15 forms a word line and is connected to the control gate of each nonvolatile storage element. The N-type diffusion layer 10 is provided for improving ohmic contact with the wiring 15.

In this embodiment, in order to improve the data retention characteristics of such a nonvolatile memory element QE having a single-layer gate structure, an aluminum layer 15 covering the entire surface of the floating gate 8 with an insulating film 13 interposed therebetween is used as a barrier. Formed as a layer. The insulating film 13 is composed of a PSG film or a BPSG film. Although not particularly limited, the insulating film 1
An aluminum layer 15 as a barrier layer formed so as to cover the entire surface of the floating gate via 3 is formed integrally with a word line to which the control gate of the nonvolatile memory element QE is connected.

The nonvolatile memory element QE of this embodiment
However, when used for relieving defects in a mask ROM as described later, the N-channel MOSFET QN has a structure similar to that of a storage element. However, in FIG. 1 (A),
An N-type impurity is introduced into a portion where a mask ROM is formed by ion implantation, and an N-channel MOSFET formed there is placed in a depletion type.

FIG. 4 shows an element pattern diagram of one embodiment of the nonvolatile memory element QE. The N-type diffusion layer 6 serving as a control gate is connected to the aluminum layer 15 indicated by a dotted line in FIG.
Connected to a word line WL. The aluminum layer 15 extends rightward along the floating gate 8 so as to cover the entire surface of the floating gate 8 hatched by a broken line in FIG. It is formed as follows.

FIG. 2 shows two memory cells vertically symmetrical with respect to the alternate long and short dash line ab. That is, the drain of the upper nonvolatile memory element QE is connected to the aluminum layer 15 via the contact hole 14.
This aluminum layer 15 is formed of a data line D made of a polysilicon layer extending to the left and right through contact hole 14.
L. Further, the N-type diffusion layer 10 constituting the source of the nonvolatile memory element QE is formed integrally with the source of the lower nonvolatile memory element QE, and the aluminum layer 15 and the drain constituting the barrier layer are formed of poly-silicon. It extends rightward along the center line ab to a region that does not intersect with an aluminum layer connected to a word line made of a silicon layer, and extends vertically through a contact hole 14 formed there, in other words, a word. It is connected to a source line SL made of an aluminum layer extending in parallel with the line.

The nonvolatile memory element QE having a single-layer gate structure according to this embodiment is provided with a barrier layer made of an aluminum layer formed so as to cover the entire upper surface of the floating gate. In this embodiment, a large-sized barrier layer having a margin exceeding the size of the floating gate 8 is used to prevent injection of the radical hydrogen into the floating gate due to diffusion of radical hydrogen as described later.

From the data holding characteristics shown in FIG.
The following is assumed. As compared with the characteristic B, the characteristic D has an improvement in the data holding characteristic. The subsequent difference between the two is that the characteristic B has a single-layer gate structure while the characteristic D has a two-layer gate structure. The inventor of the present application has presumed from this fact that the control gate in the two-layer gate structure has an effect of preventing a factor that penetrates into the floating gate to eliminate the retained charge. In order to confirm this, an element having an aluminum layer as a barrier layer shown in FIG. 1D or 4 was formed on a floating gate in a single-layer gate structure.
As for the data retention characteristic, a large improvement in the retention characteristic is recognized as shown in characteristic A.

One of the reasons that one of the factors for losing the information charges accumulated in the floating gate was radical hydrogen from the final passivation film was presumed to be as follows.
This is for the following reasons. That is, although omitted in FIG. 16, when a plasma nitride (P-SiN) film is used as the final passivation film,
It was recognized that the data retention characteristics were poor as compared with the case where a CVD oxide (PSG) film was used. The difference between the two is that there is a large difference in the amount of radical hydrogen. It was concluded that the aluminum layer as a barrier layer itself contained a large amount of hydrogen and served as a dam for blocking radical hydrogen, thereby preventing diffusion of hydrogen to the floating gate.

The barrier layer may be a polysilicon layer. The polysilicon layer also has a property of easily containing hydrogen, and when used as a floating gate, captures hydrogen diffused from the final passivation film and loses information charges. Taking advantage of this fact, a polysilicon layer is provided as a barrier layer on the floating gate. The polysilicon layer serving as the barrier layer first captures and captures radical hydrogen diffused from the final passivation film, and acts to prevent diffusion to a floating gate provided thereunder. As a result, as in the case of the aluminum layer, the polysilicon layer serving as the barrier layer functions as a dam for radical hydrogen, so as to prevent penetration into the floating gate.

Although the above phenomenon is merely speculation,
As is apparent from the data retention characteristics shown in FIG. 16, the provision of the barrier layer as described above clearly improves the data retention characteristics of the nonvolatile memory element having the single-layer gate structure.

When plasma nitride (P-SiN) is used as the final passivation film, an inexpensive plastic package that does not transmit ultraviolet light can be used. Therefore, by providing the barrier layer as in this embodiment, it is possible to obtain a semiconductor integrated circuit device using an inexpensive package while improving data retention characteristics.

FIG. 2 is a sectional view showing the element structure of another embodiment of the nonvolatile memory element according to the present invention. This embodiment is directed to a case where a semiconductor integrated circuit device provided with a nonvolatile memory element uses two layers of aluminum wiring. That is, as shown in FIG. 1D, instead of using the first aluminum layer 15 as a barrier layer, a first aluminum layer 15 is formed on an interlayer insulating film 16 formed on the aluminum layer 15. A second aluminum layer 17 is formed so as to cover the entire surface of the floating gate made of the polysilicon layer 8. In this case, when the second aluminum layer 17 is used as a word line, the nonvolatile memory element is formed by using the contact holes 14 provided in the interlayer insulating films 13 and 16 and the first aluminum layer 15. It is connected to a control gate composed of diffusion layers 6 and 10 of QE.

Although not shown, when the first aluminum layer 15 is used as a word line, the second aluminum layer 17 formed as the barrier layer is set to an electrically floating state, and is simply set to a floating gate. 8 is formed so as to cover the top.

When two aluminum layers are formed as described above, the second aluminum layer is used as a word line and the first aluminum layer is used as a data line. Conversely, the first aluminum layer is used as a word line,
The second aluminum layer may be used as a data line. Alternatively, the two aluminum layers may be used as a common source line or a sub-word line described later.

FIG. 3 shows an N-channel MOSFET.
And a P-channel MOSFET are also shown.
This N-channel MOSFET and P-channel MOS
The FET is the same as that shown in FIG.

FIG. 3 is a sectional view showing the element structure of still another embodiment of the nonvolatile memory element according to the present invention. In the characteristic diagram of FIG. 16, the characteristic C is between the first aluminum layer and the second aluminum layer in order to form a nonvolatile memory element having a two-layer gate structure and a two-layer aluminum wiring. As an interlayer insulating film to be provided, an oxide film (P-
SiO) is disposed.

The characteristic D of the nonvolatile memory element having no oxide film (P-SiO) even with the same two-layer gate structure is used.
The present inventors have found that the oxide film (P-SiO) itself also has an action of preventing the diffusion of the radical hydrogen, since a much better data retention characteristic can be obtained as compared with the above. That is, the oxide film (P-SiO) is formed by using monosilane (SiH ₄ ) + nitrogen oxide (N ₂ O) as a raw material gas and guiding it to the plasma reaction chamber to attach it. It is presumed to have the effect of absorbing the radical hydrogen that has been produced.

Therefore, in the embodiment shown in FIG. 3, the first interlayer insulating film 13 is formed of a PSG film or a BPSG film, and the second interlayer insulating film 16 is formed of the oxide film (PS).
iO) and uses the plasma nitride film (P-SiN) as the final passivation film 18.

The structure of such an interlayer insulating film is described in FIG.
This is the same as the two-layer aluminum wiring shown in FIG. Therefore, on the interlayer insulating film (PSG or BPSG) 13,
The first aluminum layer 15 constitutes a word line or the like, and although not shown, a second aluminum layer is formed on the interlayer insulating film (P-SiO) 16 by a data line, a common source line or another. It may be formed as a wiring.

In the embodiment shown in FIG. 2, if the oxide film (P-SiO) formed by the plasma-CVD method is used as the interlayer insulating film 16, the barrier layer is made of an oxide film (P-SiO) and aluminum. It can be inferred that a good data retention characteristic comparable to the characteristic C in FIG. 16 can be obtained because the layers can be doubled.

Hereinafter, a defect relief circuit of a mask ROM using a nonvolatile memory element having a single-layer gate structure as described above will be described.

FIG. 6 shows a mask R to which the present invention is applied.
A block diagram of one embodiment of the OM is shown. The memory mat MR-MAT is configured by arranging memory elements for a mask ROM in a matrix. Memory mat PR-M
The AT is configured by arranging nonvolatile memory elements having a single-layer gate structure as described above in a matrix, and is used for relieving the above-described defect data.

In the memory mat MR-MAT, a memory element is arranged at each intersection of a word line and data as in a known mask ROM, and the gate of the memory element is connected to the word line.
The drain is connected to the data line and the source is connected to the circuit ground line.

The word line of the memory mat MR-MAT is selected by the X decoder circuit XDC. The X decoder circuit XDC decodes a complementary internal address signal formed by the address buffer ADB receiving the X-system address signals A _{i + 1 to An} and stores the memory mat MR-MA.
One word line of T is selected.

The data line of the memory mat MR-MAT is connected to a common data line by a column switch gate MR-YGT. Column switch gate MR-YG
T is formed by the address buffer ADB to undergo Y-system address signals A ₀ to A _i, and in accordance with the decode signal formed by the Y decoder circuit YDC for decoding the internal address signal complementary, the memory mat MR-MAT within Then, one data line is connected to the common data line for each output mat.

The common data line is connected to an input terminal of the sense amplifier circuit MR-SAM. The sense amplifier circuit MR-SAM amplifies the storage information read from the memory element at the intersection of the selected word line and data line.

The memory mat PR-MAT includes a nonvolatile memory element having a single-layer gate structure as described above, which is arranged at each intersection between a word line and a data line.
-Used as a redundant circuit for defective data in MAT. The control gate of the nonvolatile memory element is
Connected to word line, drain connected to data line,
The source is connected to the circuit ground line. A word line of the redundant memory mat PR-MAT is supplied with a redundant word line selection signal formed by a relief address storage circuit PR-ADD described later.

The data line of the redundant memory mat PR-MAT is connected to the write data input circuit PR-PGT and the column switch gate PR-YGT. The write data input circuit PR-PGC outputs the Y-system address signals A ₀ to
The internal address signals complementary formed by the address buffer ADB undergoing A _i, the input data signal formed by the buffer DIB for receiving a write data input DI, to one data line of the redundancy memory mat PR-MAT An operation of transmitting a write signal is performed.

The above-mentioned column switch gate PR-YGT
Is the Y-system address signal A₀~ A _iAddress to receive
Complementary internal address formed by buffer ADB
According to the output signal of the Y decoder PR-YDC for decoding the signal.
For each output mat of the redundant memory mat PR-MAT,
One data line is connected to the common data line. Como
The data line is an input terminal of the sense amplifier circuit PR-SAM.
Connected to child. The sense amplifier circuit PR-SAM reads
Of the word line and data line selected in
Read from the memory cell (non-volatile storage element) at the intersection
The amplified stored information is amplified.

The output signal of this sense amplifier circuit PR-SAM is input to a multiplexer circuit MPX for switching the sense amplifier. This multiplexer circuit MPX
Selects either the output signal of the sense amplifier circuit MR-SAM for the mask ROM or the output signal of the sense amplifier circuit PR-SAM for the redundant memory mat PR-MAT and transmits it to the output buffer DOB. The output buffer DOB sends the read data that has been transmitted through a multiplexer circuit MPX from the output terminal DO ₀ to DO _m.

Although not particularly limited, in this embodiment,
The non-volatile memory element is used to store the
Have been. The method of storing the relief address is based on the X-system address signal.
Issue A _{i + 1}~ A_nReceiving address buffer circuit ADB
The formed address signal is transferred to a relief address selection circuit RAS.
Is converted to write data by the
Stored in the non-volatile memory element arranged in the path PR-ADD.
Let Although not particularly limited, the relief address storage circuit PR
-ADD can store a plurality of relief word lines.
You. These plurality of relief word lines store the relief address storage locations.
Conversion of the Y-address signal A₀~ A_iAddress to receive
Address signal formed by the buffer circuit ADB
Assigned by the redundant word line selection circuit RAST that decodes the signal
I can

The relief address storage circuit PR-ADD, as well as storage of the relief address, written to form a word line selection signal / RWS ₁ ~ / RWS _p address, the word line selecting operation of the redundant memory mat PR-MAT Do.
Further, it forms output switching complementary signals RSDA and / RSDA of the multiplexer circuit MPX. In the present specification, an overbar of a logic symbol having a low level as an active level is replaced with /.

The control circuit CONT receives a chip enable signal CE for activating the semiconductor integrated circuit device and an output enable signal / OE for controlling an output buffer at the time of reading, and receives each circuit block activation signal / OE.
ce, activation signal / s of sense amplifier circuit MR-SAM
ac, an activation signal / doc for the output buffer circuit DOB, and a high-voltage terminal Vpp for writing the nonvolatile memory elements (PR-MAT, PR-ADD) arranged for redundancy, although not particularly limited, Upon receiving a write enable signal / WE for performing write control, an internal write control signal / we, a write signal RS for rescue address storage,
RWNS or the like is formed.

FIG. 7 shows the redundant word line selection circuit RA.
A circuit diagram of one embodiment of ST is shown. Complementary address signals a ₀ and // formed by address buffer circuit ADB receiving Y-system address signals A _{0 to} A _h (h ≦ i)
a ₀ ~a _h, / a _h receiving, relief address storage circuit PR
A signal RWNS which is activated at the time of writing ADD to the storage element to generate a storage location assignment signal AST _1-
AST _j is formed. For example, if three-bit address signals A _{0 to} A ₂ are used, eight kinds of storage location allocation signals AST _{1 to} AST ₈ can be formed. As a result, a word line having a maximum of eight defective bits in the memory mat MR-MAT is replaced with the redundant memory mat P
It can be replaced with an R-MAT storage cell. Therefore, when the above-described relief address storage circuit PR-ADD is used, nonvolatile memory elements corresponding to the eight word lines are arranged in a matrix in the redundant memory mat PR-MAT.

FIG. 8 shows the relief address selection circuit RA.
A circuit diagram of one embodiment of S is shown. Relief address selection
The selection circuit RAS outputs the X-system address signal A_{i + 1}~ A_nIt
Each formed by an address buffer circuit ADB to be received.
Each of the above address signals a_{i + 1}~ A_nReceiving relief address
Write to the nonvolatile memory element of the memory circuit PR-ADD
Signal RWNS activated at the time of
Dress signal a_{i + 1}~ A _nIs the write data RAWa_{i + 1}
~ RAWa_nThe relief address storage circuit PR-AD
D is told. Stored rescue address and X-system address
Less signal A_{i + 1}~ A_nAddress signal to compare with
No. Ca_{i + 1}~ Ca_nIs the relief address assigned earlier
Each is formed in the storage unit.

FIG. 9 shows a relief address storage circuit PR-A.
A circuit diagram of one embodiment of the DD is shown. The rescue address storage write signal RS is transmitted to the word line to which the nonvolatile memory element having the single-layer gate structure arranged as the storage element is coupled, and the memory formed by the rescue address selection circuit RAS. Address data RAW
a i _{+ 1} ~RAWa _n is by being transmitted to the data lines, writing to the memory device is performed.

The data line connected to the memory element storing the relief address is connected to the input terminal of the sense amplifier SA, and is amplified by the sense amplifier SA at the time of a read operation. In this embodiment, although not particularly limited, an extra 1-bit memory element is provided as a memory element for storing the relief address in addition to the above-described relief address. "1" information or "0" is stored in this 1-bit memory element.
By storing any data of the information, it is confirmed whether or not the relief address is stored, and the activation signal of the sense amplifier SA and the relief address selection circuit RA are stored.
S of the address comparison signal Ca _i + 1 ~Ca activation signal / RS ₁ for _n form ~ / RS _p is formed.

[0056] When the reading of the memory device storing the repair address is performed, the output signal of the sense amplifier SA, match with the address comparison signal Ca i _{+ 1} ~Ca _n /
It is input to an exclusive-OR circuit to confirm a mismatch. The output of the exclusive OR circuit, the output and the address of the sense amplifier SA compares the signal Ca i _{+ 1} if and to CA _n match "0", in the case of disagreement becomes "1". When all data in the memory device for relief address storage match, activates the selection signal one of the redundant word line selection signal RWS ₁ ~RWS _p. Further, if any one of the redundant word line selection signal RWS ₁ ~RWS _p is selected, the activation of the sense amplifier circuit PR-SAM provided redundant memory mat PR-MAT, and supplied to the multiplexer MPX Switching signal RS
AD and / RSAD are formed.

FIG. 10 shows a write data input circuit PR
A circuit diagram of one embodiment of the PGC is shown. Address buffer circuit A which receives the Y-system address signals A ₀ to A _i of
Complementary internal address signals a ₀ , / a formed by DB
₀ ~a _i, / a _i and data Data decodes and supplies the write data Dy ₀ ~Dy _k to the data lines of the memory mat PR-MAT for redundancy by writing signals we.

FIG. 11 shows a Y decoder circuit PR for redundancy.
A circuit diagram of one embodiment of -YDC is shown. The Y decoder circuit PR-YDC for redundancy uses the Y address signal A
₀ to A internal address signals complementary formed by the address buffer circuit ADB receiving a _{i a 0, / a 0 ~a} i, /
forming a column select signal y ₀ ~y _k supplied to the column switch gate PR-YGT decrypts the a _i.

FIG. 12 shows a redundant memory mat PR-
A circuit diagram of one embodiment of the MAT, the column switch gate PR-YGT, and the sense amplifier circuit PR-SAM is shown.

FIG. 13 is a circuit diagram showing an embodiment of the multiplexer MPX. In this embodiment, 3
A clocked inverter circuit having a status output function is used. When the inversion switching signal RSDA is activated,
A clocked inverter circuit receiving a read signal of a memory element selected by a memory mat MR-MAT constituting a mask ROM is activated, and transmits it to an output buffer circuit DOB. Non-inverted switching signal RSDA
Is activated, the redundant memory mat PR-MAT
Activates the clocked inverter circuit that receives the read signal of the selected memory element, and transmits it to the output buffer circuit DOB. That is, the memory mat M
Correct data stored in the redundant memory mat PR-MAT is output instead of the read data including the defective bit existing in the R-MAT.

FIG. 14 is a circuit diagram showing another embodiment of the mask ROM to which the present invention is applied. The mask ROM of this embodiment is an N-channel type storage MOS.
A series circuit of FETs is composed of a plurality. Each of the storage MOSFETs Qm is formed as a depression type or an enhancement type according to stored information. Writing of storage information to such a memory element is performed by the ion implantation method as described above. In the figure, the depletion type MOSFET is distinguished from the enhancement type MOSFET by adding a straight line to the channel portion.

A series circuit corresponding to one data line D1 exemplarily shown as a representative includes an MO for column selection.
SFET T1, T2, etc. and storage MOSFET for data storage
It is composed of TQ1 to Q3 and the like. In a series circuit adjacent to this and corresponding to another data line D2 exemplarily shown as a representative, storage MOSFETs Q4 to Q6 for data storage are connected to MOSFETs T3 and T4 for column selection.

For example, the column selection MOSFETs T1 and T4 shown as examples are depletion type MOs.
In the SFET, T2 and T3 are enhancement type MOSF
When the other series MOSFETs respectively constituted by ET and not shown in the figure are in the ON state, the selection signal supplied to the gates of T1 and T3 by the column selector is at low level, and the selection signal supplied to the gates of T2 and T4 is selected. When the signal is at a high level, both T1 and T2 are turned on, and the storage MOSFETs Q1-Q connected in series to the data line D1.
3 etc. are connected. Also, T1,
When the selection signal supplied to the gate of T3 is at a high level,
When the selection signal supplied to the gates of T2 and T4 is at a low level, T3 and T4 are both turned on, and the storage MOSFETs Q4 to Q6 in series are connected to the data line D2. Therefore, although not shown, each data line D in FIG.
It becomes possible to provide a plurality of series circuits in parallel with respect to 1, D2, and the like.

Storage MOS of each series type of memory array
Of the FETs, the storage MOSFET Q corresponding to the lateral direction
The gates of m are commonly connected to word lines W1, W2, W3, etc., which are shown as representatives, for example. These word lines W1 to W3 are connected to corresponding output terminals of the X decoder.

The data lines D1, D2, etc. are connected to a common data line CD via a Y decoder. The Y decoder in FIG. 1 shows the Y decoder itself and a column switch circuit including switch elements that are switch-controlled by the selection signal.

The common data line CD is connected to the input terminal of the sense amplifier SA. The sense amplifier SA refers to the reference voltage formed by the reference voltage generation circuit VRF,
Sense amplification of the high level and the low level of the read signal of the selected memory cell is performed.

Although not particularly limited, the sense amplifier S
As the reference voltage of A, the sensing operation may be performed with reference to a reference voltage formed by a dummy array including a storage circuit similar to the memory array unit. As the dummy array, a memory array in which all of the storage MOSFETs Qm are constituted by enhancement MOSFETs and whose gates are constantly supplied with the power supply voltage Vcc to be constantly turned on can be used.

Next, the address selection operation of the vertical ROM in this embodiment will be described. The X decoder decodes the internal address signal supplied from the row address buffer,
A decoded output in which the selected level is set to the low level and the non-selected level is set to the high level is formed. For example, when the number of word lines is 512, one selected word line is set to low level, and all the other 511 word lines are set to high level. As a result, if the storage MOSFET coupled to the selected word line is a depletion type, a current path is formed in the series circuit, and if the storage MOSFET is an enhancement type, no current path is formed.

The Y decoder YDCR decodes the internal address signal supplied through the address buffer, selects, for example, one of 512 data lines, and selects a common data line CD.
To be connected. Thereby, one read signal corresponding to one selected data line is amplified by the sense amplifier SA. When the read data is read in units of a plurality of bits such as 8 bits or 16 bits,
Either 8 or 16 similar memory arrays may be provided, or 8 or 16 data lines may be simultaneously selected by a Y decoder, and a sense amplifier and an output circuit may be provided for each of them.

To remedy such a vertical ROM defect, the above-mentioned nonvolatile memory element is used. The circuit shown in FIG. 6 and the like can be used for the relief address storage circuit and the redundant memory mat using the nonvolatile storage element.

FIG. 15 is a circuit diagram showing another embodiment of the redundant memory mat and its peripheral circuits. Although the circuit symbols given to the respective elements in FIG. 14 partially overlap with the elements shown in FIG. 14, it should be understood that they are different from each other.

FIG. 9 exemplarily shows one word line W1 and a plurality of storage elements Qm connected thereto. The selection circuit for the word line W1 is constituted by a ratio type logic circuit. That is, the selection signal formed by the NAND gate circuit G is the N-channel drive MOSF
It is supplied to the gate of ETQ1. This MOSFET Q1
Is connected to the ground potential of the circuit, and an N-channel MOSFET receiving a selection signal inverted by the CMOS inverter circuit N between the drain side and the power supply voltage Vcc.
Q2 is provided. The drain output of the drive MOSFET Q1 is connected to the word line W1 via the depletion type MOSFET Q3 whose gate is supplied with the write control signal / WE. The word line W1 is provided with a depression type load MOSFET Q4. The power supply terminal to which the depletion type load MOSFET Q4 is connected is supplied with a high voltage Vpp during a write operation and a low power supply voltage Vcc such as 5 V during a read operation.

In this embodiment, at the time of the write operation of the storage element Qm, in the storage element provided on the non-selected word line, the leakage to the channel occurs in accordance with the potential of the floating gate being raised by the write high level of the data line. In order to prevent a current from flowing, the source of the storage MOSFET Qm corresponding to the word line is connected to a common source line S1, and this source line has a switch MOS.
A ground potential is applied via FET Q7.

In this embodiment, since the word line is formed by the ratio type logic circuit as described above, the MOSFETs Q1 and Q3 and the load M
The level is set higher than the ground potential according to the conductance ratio with the OSFET Q4, and the MOSFET Q7 cannot be reliably turned off. That is, at the time of the write operation, the write control signal / WE is at the low level, and when the output signal of the gate circuit G is at the non-selected state of the high level, the MOSFET Q1 is turned on to connect the word line to the ground potential side of the circuit. However, the level rises above the ground potential according to the ratio of the conductance of the load MOSFET Q4 to the combined conductance of the MOSFETs Q3 and Q1.

Therefore, a sub-word line SW1 to which the output signal of the CMOS inverter circuit N1 is supplied is provided, and a selection signal corresponding to the word line W1 is supplied to the gate of the switch MOSFET Q7. With this configuration, when the word line W1 is in the non-selected state, the output signal of the CMOS inverter circuit N is at a low level such as the ground potential, and the switch MOSFET Q7 can be reliably turned off.

Thus, when the word line W1 is in a non-selected state such as a low level, a high level is supplied to the data lines D1 to D16, etc., so that the storage element Qm coupled to another word line (not shown) is supplied. It is possible to prevent a leak current from flowing through the storage MOSFET Qm provided on the non-selected word line W1 to which no writing is performed during the writing operation. Since the channel current does not flow through the non-selected storage element Qm, the MOSFET
Withstand voltage is also improved. This is because the MOS breakdown voltage when a channel current flows is due to a parasitic bipolar operation composed of a source, a substrate, and a drain, and is lower than the MOS breakdown voltage due to surface breakdown when no channel current flows.

When a word driver for forming a word line selection signal is formed by a CMOS circuit,
The switch of the switch MOSFET Q7 may be controlled by the word line W1. In this case, since the potential of the word line at the time of the write operation is increased to the high voltage Vpp, the switch MOSFET Q7 needs to have a higher breakdown voltage accordingly.

In this embodiment, in order to reduce the writing time, the data line D1 shown as a representative is
, A write circuit WA having a latch circuit FF is provided for all data lines D2 to D16. The storage element Qm is composed of a non-volatile storage element having a single-layer gate structure as shown in FIG. 1D and FIG. Therefore, the size thereof is larger than that of the nonvolatile memory element having the two-layer gate structure. Therefore, the pitch between the data lines becomes relatively large, and the above-described write circuit WA can be provided for each data line without sacrificing the data line pitch of the memory mat.

As described above, the write circuit WA is connected to each data line.
Is provided, a write operation including two steps is performed. That is, the write operation in the first step is as follows.
This is an operation of storing write data in the latch circuit FF. At this time, the data input through the data input circuit DIB sequentially selects a data line via the column switch CW, and the data is transferred to the latch circuit FF provided therein. When the data transfer to all the data lines corresponding to one word line or to the latch circuits FF corresponding to a plurality of predetermined data lines is completed, the write operation in the second step is started. In the write operation of the second step, the potential of the selected word line is set to the write high voltage for the word line, and the write high voltage is supplied to the data line D1 in accordance with the data taken into the latch circuit FF of each write circuit WA. Switch MOSFET
The switch of Q6 is controlled to inject charges into the floating gate of the storage element Qm.

In this case, since the write current flows simultaneously to a plurality of storage elements as described above, the leak current prevention circuit as described above is also used in order to prevent the write current from becoming enormous. It is necessary to provide.

When a write operation is performed simultaneously on a plurality of storage elements Qm as described above, the storage element Qm in which charge is injected into the floating gate is used.
Since a relatively large current flows through the source line S1, a large current flows through the source line S1 and it is necessary to prevent disconnection of the wiring due to migration. To prevent such disconnection due to migration, the width of the source line may be increased. However, for high integration, it is not advisable to increase the wiring width. Therefore, by providing a plurality of switch MOSFETs Q7 at regular intervals of the source line S1 and dispersing the write current, the disconnection due to the above-described migration can be prevented without forming the source line so thick.

The above-described write operation is performed by, but not limited to, a probing process when a circuit is completed on a semiconductor wafer. That is, in the probing process, a read test of the mask ROM is performed, a defective bit is detected from the test result, and a rescue address is written and storage data corresponding to the rescue address is written. When relieving defects, by performing writing in the probing process in this way,
When the mask ROM is completed, no special control terminal is required for writing the above-described rescue address and data corresponding thereto.

When the user changes or corrects data, it is necessary to perform writing after the completion of the semiconductor integrated circuit device. Therefore, an appropriate external terminal must be provided or a high voltage input must be provided. May be provided so that one terminal is multiplexed and used.

The write voltage applied to the data line is not switched from the power supply voltage Vcc to the high voltage Vpp, but the power supply voltage Vcc of about 5 V is raised to about 7 V to 8 V within the allowable range of the breakdown voltage of the MOSFET. The voltage (Vcc ') shown in FIG. In this case, since it is not necessary to increase the breakdown voltage of the write MOSFETs Q6 and Q5, the manufacturing process can be simplified. When the high voltage Vpp is used only as a selection level at the time of writing to a word line, no DC current flows from the high voltage terminal Vpp, so that the high voltage Vpp can be formed by a relatively simple internal booster circuit.

When the write voltage applied to the data line at the time of writing is relatively low, such as about 7 to 8 V, the writing time is relatively long. However, when the non-volatile storage element having the single-layer gate structure is used for defect repair or function change as in this embodiment, the number of write data may be relatively small, so that the unit write time is slightly longer. It will not be a big problem.

As described above, in the write operation of the nonvolatile memory element having the single-layer gate structure, the method of increasing the high voltage applied to the drain to the power supply voltage Vcc as Vcc 'is the same as that of the embodiment of FIG. Needless to say, the present invention can be used not only when the write circuit WA using the latch circuit FF is used but also when data is input from an external terminal shared with other terminals such as a pad, an external terminal, or an address terminal. Nor.

FIG. 5 is a pattern diagram showing one embodiment of the storage element having the above-described sub-word line. In this embodiment, a sub word line SW made of the same aluminum layer as the source line SL is provided in parallel with the source line SL.
Is placed. In the configuration in which the sub-word lines SW are arranged as described above, the size of the memory cell is correspondingly increased. Therefore, in order to prevent this, the source diffusion layer is formed small, and the source line wiring is formed to extend therethrough.

FIGS. 17 to 23 show another embodiment of the present invention. In these embodiments, a part of the floating gate is exposed from the barrier layer covering the upper part of the floating gate. That is, the barrier layer does not cover the entire surface of the floating gate but covers a part thereof.

As described above, in order to improve data retention characteristics, it is desirable to form a barrier layer so as to cover the entire surface of the floating gate. However, if the entire surface of the floating gate is covered, the size of the nonvolatile memory element increases accordingly. For this reason,
When a large-capacity, single-layer gate structure nonvolatile memory element is required as in the case of mask ROM relief, it is disadvantageous from the viewpoint of the degree of integration. Therefore, in order to reduce the size of the nonvolatile memory element, a configuration in which a part of the floating gate is exposed from the barrier layer is used. In other words, the barrier layer does not cover the entire surface of the floating gate but a word line. , The shape of the data line or the source line is intentionally partially deformed to the extent possible and extended above the floating gate. By doing so, since the floating gate is partially covered with the barrier layer, the data retention characteristics can be surely improved by that much.

That is, it is presumed that the cause of impairing the data retention characteristic is that radical hydrogen from the final passivation film reacts with electrons accumulated in the floating gate to combine with the electrons, resulting in a decrease in the accumulated electrons. You. In this case, the rate at which the accumulated electrons decrease per unit time is considered to be proportional to the product of the electron density on the surface of the floating gate and the radical hydrogen density. Therefore, if the area ratio where the floating gate is exposed from the barrier layer is reduced, the reaction between radical hydrogen and the electrons stored in the floating gate is reduced, and the rate at which the stored electrons are reduced is also reduced. As a result, the data retention characteristics are improved as described above.

FIG. 17 is a sectional view showing the element structure of another embodiment of the nonvolatile memory element according to the present invention.
Shows a plan view thereof. 17 and 18, an aluminum layer 15 forming a word line WL is formed.
Is used as a barrier layer of the floating gate 8 by being intentionally extended to the right side (source line side) in FIG.

FIG. 19 is a sectional view showing the element structure of another embodiment of the nonvolatile memory element according to the present invention.
Shows a plan view thereof. 19 and 20, the aluminum layer 1 forming the word line WL is
As a result of the slits being provided in 5, the floating gate 8 is partially exposed. Although not particularly limited, the slit is formed in a rectangular shape so as to be parallel to a word line extending over two floating gates. When the word line is extended to cover the entire surface of the floating gate to form the barrier layer as described above, the word line becomes thicker. When the word line becomes thicker in this way, cracks are formed in the aluminum layer 15 as the word line and the lower insulating film 13 of the aluminum layer 15 due to the stress of the final passivation film, and there is a possibility that the element characteristics may be impaired. Therefore, in this embodiment, slits are provided in the aluminum layer acting as the barrier layer to reduce the substantial thickness, thereby preventing the above-described cracks from occurring.

In FIGS. 17 to 20, the aluminum layer 15 forming the word line WL is extended to cover a part of the floating gate.
Instead of this, the barrier layer that covers a part or the whole surface of the floating gate by extending the aluminum layer 15 that forms the data line DL or the source line SL may be formed. Similar to the above, a slit may be provided to prevent cracks.

FIG. 21 is a sectional view showing the element structure of another embodiment of the nonvolatile memory element according to the present invention.
Shows a plan view thereof. In FIGS. 21 and 22, the aluminum layers 15 forming the word lines WL and the data lines DL are respectively extended, so that the floating gates 8 are partially covered. In such a case, the proportion of the individual aluminum layers forming the word line WL and the data line DL covering the upper part of the floating gate is small.
By using both L and data line DL as barrier layers, the ratio of covering the upper part of floating gate 8 can be substantially increased. When the barrier layer is divided into two layers as described above, the thickness of each aluminum layer can be reduced, so that the occurrence of cracks can be prevented without providing the slit as described above.

In the above embodiments, the word line WL is constituted by the aluminum layer 15 and the data line DL is constituted by the conductor layer 8 such as polysilicon or polycide. Such a configuration is convenient when the number of nonvolatile storage elements connected to the data line DL is smaller than the number of nonvolatile storage elements connected to the word line WL. That is, since the word line WL is formed of the aluminum layer 15 having a small resistance value, the delay time of the word line WL at the time of reading can be reduced.

FIG. 23 is a plan view showing another embodiment of the nonvolatile memory element according to the present invention. FIG.
In the embodiment of (A), the word line WL is constituted by a conductor layer 8 made of polysilicon or polycide. Such a configuration is convenient when the number of nonvolatile memory elements connected to the word line WL is smaller than the number of nonvolatile memory elements connected to the data line DL. Data line DL
Is the aluminum layer 1 as shown by the dotted line in FIG.
5 is comprised. Therefore, barrier layer is formed by forming aluminum layer 15 constituting data line DL so as to extend to a part of the upper portion of floating gate 8.

In the embodiment of FIG. 23B, the word line WL
Is constituted by a conductor layer 8 made of polysilicon or polycide. Such a configuration is convenient when the number of nonvolatile storage elements connected to the word line WL is smaller than the number of nonvolatile storage elements connected to the data line DL. The data line DL and the source line SL are composed of the aluminum layer 15 as shown by the dotted line in FIG. In this embodiment, the aluminum layer 15 constituting the source line SL is extended to a part of the upper part of the two floating gates 8 constituting the two nonvolatile memory elements sandwiching the source line SL. The barrier layer is formed by being formed.

Similar to the embodiment shown in FIGS. 21 and 22, aluminum layers 15 of both data line DL and source line SL extend so as to cover part of floating gate 8 respectively. May be present.

FIGS. 24A to 24D are cross-sectional views showing a manufacturing process for explaining another embodiment of the nonvolatile memory element according to the present invention.
Shown with OSFET and P-channel MOSFET.

In this embodiment, unlike the nonvolatile memory element shown in FIGS. 1A to 1D,
The step of forming the N-type diffusion layer 6 is omitted. That is, the control gate of the nonvolatile memory element QE of this embodiment is formed by the N-type well region 102 (n ⁻ ) forming the P-channel MOSFET QP. Further, in the nonvolatile memory element QE, an N-type diffusion layer 10 is formed so as to extend below the floating gate similarly to the nonvolatile memory element QE shown in FIGS. 1A to 1D. . That is, the capacitive coupling between the floating gate and the control gate is determined by the capacitance between the N-type well region 102 and the floating gate and the capacitance between the N-type diffusion layer and the floating gate. Since the capacity coupling can be increased as compared with the case where only the capacitance between the cells is used, the cell size can be reduced.

FIG. 25 is a plan view of the nonvolatile memory element corresponding to FIGS. 24A to 24D. In this case, the depletion type N channel M
When OSFETs are formed on the same semiconductor substrate,
Implanting an N-type impurity used for the depletion type has an effect of further increasing the capacitance value between the N-type well region 102 and the floating gate. Of course, the control gate may be constituted only by the N-type well region 102. Alternatively, a diffusion layer extending below the floating gate, such as the N-type diffusion layer 10, may be used as the control gate without using the N-type well region 102.

In this embodiment, the N-type well region formed on the P-type semiconductor substrate is used as the control gate.
When a type semiconductor substrate is used, a nonvolatile memory element having a PMOS structure using a P-type well region as a control gate may be used, and various modifications are possible.

According to the present embodiment, it is possible to obtain a nonvolatile memory element in which the control gate is formed of a diffusion layer without adding any manufacturing process, so that the present invention can be applied to any semiconductor integrated circuit device.

Since the distance for separating the N-type well region from another diffusion layer such as the N-type diffusion layer 10 becomes long in the nonvolatile memory element of this embodiment, the cell size is as shown in FIG. 4 or FIG. The cell size is larger than that of the above embodiment.
However, as will be described later, the number of nonvolatile storage elements required is small in the case of only address conversion as in the case of repairing the RAM, so that there is no problem even if the cell size is slightly large.

FIGS. 26A to 26C are cross-sectional views showing a manufacturing process for explaining still another embodiment of the nonvolatile memory element according to the present invention. Channel MOSFET and 2
Storage MOSFE forming mask ROM having layer gate structure
Shown with TQM.

In this embodiment, in order to improve the integration of the mask ROM, the conductor layers 8 and 1 having different adjacent word lines are different.
08. That is, of the plurality of storage MOSFETs arranged in series, the word line of the odd-numbered MOSFET is formed by the first polysilicon layer 8, and the word line of the even-numbered MOSFET is formed by the second polysilicon layer 108. Configure a word line. When such an adjacent word line has a two-layer gate structure, a substantial interval between word lines (pitch of storage MOSFET) is narrowed, so that the degree of integration can be improved.

Also in this case, the nonvolatile memory element QE used for defect relief has a one-layer gate structure in which the control gate is constituted by a diffusion layer. The non-volatile memory element has a single-layer gate structure despite the fact that the polysilicon layer has a two-layer structure for the following reasons. In a nonvolatile memory element having a two-layer gate structure, a gate insulating film provided between the first and second polysilicon layers is essentially different from that of a mask ROM having a two-layer gate structure.

In other words, the two-layer gate structure in the mask ROM is different from the two-layer gate structure in that an insulating film may be formed merely for the purpose of simply electrically separating the first and second gates. In a nonvolatile memory element having a gate structure, a thin insulating film whose film quality and film pressure are controlled to satisfy desired write / read characteristics is required. Therefore, in a nonvolatile memory element having a two-layer gate structure, it is necessary to add a special manufacturing process for forming an insulating film to be formed between the floating gate and the control gate. Therefore, by using the nonvolatile memory element having the single-layer gate structure as described above, defect relief or the like can be performed without substantially increasing the number of manufacturing steps.

In FIG. 26A, the N-type diffusion layer 6 serving as a control gate, the first gate insulating film 7, and the first gate electrode 8 are formed similarly to the embodiment shown in FIGS. 1A to 1D. The first MOSFET of the mask ROM is formed. Insulating films 201 and 211 are formed on the upper and side surfaces of the first gate electrode 8 for insulation from the second MOSFET of the mask ROM.

In FIG. 26B, a second MOSFET of a mask ROM including the second gate insulating film 107 and the second gate electrode 108 is formed. In this embodiment, the floating gate of the nonvolatile memory element QE and the N-channel MOSFETs QN and P
The gate electrode of the channel MOSFET QP is formed by the second conductor layer 108. Of course, these gate electrodes may be constituted by the first conductor layer 8.

As shown in FIG. 26C, each of these circuit elements is completed in the same manner as in the above embodiment. However, the passivation film is omitted in FIG. In this embodiment, even if the original semiconductor integrated circuit device has a two-layer gate structure as described above, the manufacturing process is simplified by making the nonvolatile memory element a one-layer gate structure.

FIGS. 27A and 27B are cross-sectional views of an element structure of an embodiment of a semiconductor integrated circuit device when a nonvolatile memory element having a single-layer gate structure is used for rescue of a dynamic RAM. Have been.

In the dynamic memory cell of FIG. 27A, the information storage capacitor is composed of the conductor layer 203 and the dielectric film 2.
04, a so-called STC constituted by the conductor layer 205
Structure. The dynamic memory cell of FIG. 27B has a so-called planar structure in which an information storage capacitor includes an N-type diffusion layer 6, a dielectric film 204, and a conductor layer 205. In the figure, the passivation film is omitted.

In each of the embodiments shown in FIGS. 27A and 27B, similarly to the embodiment shown in FIGS. 24A to 24E, a nonvolatile memory element having a single-layer gate structure is used. Since the control gate is constituted by the N-type well region 102, there is no additional manufacturing process. Since the defect relief in the dynamic RAM is performed only by address conversion, the number of necessary nonvolatile memory elements may be small, so that there is no substantial problem even if the cell size is large.

When two wiring layers 15 and 17 are provided, as shown in the cross-sectional view of FIG. 27B and the plan view of FIG. Wiring layer 15 composed of two layers
And 17 are covered. That is, in this embodiment, the word line WL is formed of the first aluminum layer 15 and the data line DL is formed of the second aluminum layer 17. Therefore, 2
The aluminum layers 15 and 17 are overlapped with each other so as to cover a floating gate provided thereunder.

FIG. 29 shows a dynamic RA incorporating a defect rescue circuit using a nonvolatile memory element according to the present invention.
A block diagram of one embodiment of M is shown. The memory part of the dynamic RAM is a memory mat DR-MAT,
Y gate circuit DR-YGT, sense amplifier circuit DR-S
AM. The memory mat DR-MAT is configured by arranging a memory cell including an information storage capacitor and an address selection transfer MOSFET as shown in FIG. 27A or 27B in a matrix. In the case of a dynamic RAM, the mask R
A non-volatile memory element for storing data later such as OM is not required, and a spare (redundant) memory mat dr-MAT arranged and arranged in a matrix composed of the same memory cells as the memory mat DR-MAT. , Y gate circuit dr-MAT and sense amplifier circuit dr-SAM.

The dynamic RAM incorporates a substrate bias generation circuit VBBG. That is, as described above, the spare memory mat dr-MAT uses the same volatile memory cell as the memory mat DR-MAT,
Except that there is no circuit for writing to the spare memory mat dr-MAT and that a substrate bias generation circuit VBBG is mounted, defects of the dynamic RAM can be rescued by the same method as in the mask ROM address conversion. .

Although not particularly limited, at the time of writing to the nonvolatile memory element, the substrate bias generation circuit VBBG is inactivated, and the semiconductor substrate is set to the circuit ground potential (ground potential). This is because a high voltage is applied to the control gate formed of the diffusion layer formed on the semiconductor substrate when writing to the nonvolatile memory element, so that the voltage of the PN junction does not become too high. That is, this enables writing to a nonvolatile memory element having a single-layer gate structure using the diffusion layer as a control gate without particularly increasing the breakdown voltage of the PN junction. Needless to say, defect relief of a static RAM can also be realized by the same method as that of defect relief of a dynamic RAM as in this embodiment.

FIG. 30 is a block diagram showing an embodiment in which the nonvolatile memory element having a one-layer gate structure according to the present invention is used for a microcomputer or the like. The microcomputer according to the present embodiment includes a CPU (microprocessor) and an RO configured on the same semiconductor substrate.
M, RAM, and I / O (input / output) ports. Each circuit block is mutually connected by a BUS (bus). The CPU is provided with a μROM (microprogram ROM).

The relief circuit is indicated by hatching in the μROM, ROM, ROM, and I / O port. These rescue circuits have a similar configuration to the circuits shown in FIGS.
In the OM, address conversion and data storage are performed using a nonvolatile storage element, and in the RAM, address conversion is performed using a nonvolatile storage element. Since these rescue methods are the same as those in the above-described embodiment, description thereof will be omitted. Also, I /
In the O port, for example, TTL level input / output and CMO
The change of the S level input / output is performed. As in the present embodiment, a nonvolatile memory element having a single-layer gate structure in which a control gate is formed of a diffusion layer relieves each logic block mounted on a microprocessor or performs I / O.
Logical changes such as ports can be easily made. In addition, a spare BUS is prepared, and the defective BUS
It is also possible to translate the address of each logical block connected to the.

FIG. 31 shows a non-volatile memory element having a one-layer gate structure according to the present invention, and a conventional two-layer gate structure EP.
An element structure sectional view of one embodiment when mounted on a ROM is shown. The control gate of the nonvolatile memory element QE having the single-layer gate structure according to the present invention is formed of the N-type well region 102 which does not require any additional manufacturing steps as described above. The N-channel MOSFET QHN and the P-channel MOSFET QHP are high-breakdown-voltage MOSFETs used at the time of writing in a nonvolatile memory element (EPROM) QEP having a two-layer gate structure, and include a first gate insulating film 7 and a first gate electrode 8. ing. The N-channel MOSFET QN and the P-channel MOSFET QP are MOSFETs used at a normal operating voltage, and include a second gate insulating film 107 and a second gate electrode. Non-volatile memory element QE with two-layer gate structure
P is composed of a floating gate composed of the first gate electrode 8 and a control gate composed of the second gate electrode 108 provided thereon with an insulating film 207 interposed therebetween.

EPROM having a two-layer gate structure as described above
In this case, it is easy to use an EPROM having a two-layer gate structure also as a nonvolatile storage element for relief. However, in the case of the microcomputer shown in FIG. 24, an EPROM whose data can be easily changed is used as a data ROM in the early stage of product development, but the function is the same after temporary data is determined. Even if inexpensive mask ROM is used. At this time, if the repair is performed by the EPROM having the two-layer gate structure, the EPROM having the two-layer gate structure must be changed to the nonvolatile memory element having the one-layer gate structure. ). Therefore, in such a case, as in the present embodiment, the rescue circuit portion is constituted by a circuit including a nonvolatile memory element having a single-layer gate structure from the beginning. Thereby, for example, the data ROM is changed from the EPROM having the two-layer gate structure to the mask R.
A microcomputer changed to OM can be easily obtained. Alternatively, this is convenient when the number of nonvolatile storage elements mounted on the microcomputer may be small.

FIG. 32 is a sectional view showing an element structure of an embodiment when the nonvolatile memory element according to the present invention is used for trimming a semiconductor integrated circuit device including an analog circuit. FIG. 33 shows a trimming circuit. The circuit diagram of one embodiment is shown. As shown in FIG. 32, a semiconductor integrated circuit device including an analog circuit includes an N-channel MOSFET that forms an operational amplifier circuit AMP of a digital section or an analog section.
TQN or P-channel MOSFET QP and capacitive element Q
C, and a resistance element QR.

The trimming circuit shown in FIG. 33 trims the reference voltage used in the analog circuit, and sets the internally generated voltage Vin to a desired voltage Vout using 3-bit data. is there. Voltage Vou
A series resistor circuit R0 is provided between t and the ground potential,
Each mutual terminal is connected to one terminal of an operational amplifier AMP via a decoder DEC. The decoder DEC is operated by the data generated by the trimming circuits TRC1 and TRC3, and trimming is performed by changing the resistance ratio.

First, the PC terminal is set to the ground potential, predetermined data is input to the PD terminal, and trimming data is determined. Next, the Vcc terminal is set to the ground potential, the write voltage Vpp is applied to the PC terminal, the previously determined data is input to the PD terminal, and the nonvolatile memory element QE is written.

In this embodiment, data is transferred to P through a resistor R.
Although the input is made directly from the D terminal, it may be performed as in the above embodiment. Alternatively, only one data input terminal may be provided, and serial data may be changed to parallel data by a shift register for writing.

A semiconductor integrated circuit device including an analog circuit is often operated with a battery of about 1 V.
The threshold voltage of the nonvolatile memory element QE before writing is usually about 1 V, and it is not possible to judge before and after writing. In such a case, (1) the gate voltage of the nonvolatile memory element QE is boosted to a voltage that allows determination before and after writing, for example, about 3 to 5 V. (2) The state before writing is set to the depletion mode, and the mode is set to the enhancement mode after writing. Then, the gate voltage is set to the ground potential and read. (3) By a method described later, the state before writing is set to the enhancement mode, and the mode is set to the depletion mode after writing. Then, the gate voltage is set to the ground potential and read.

FIG. 34 is a circuit diagram of one embodiment of a memory array having a vertical (NAND) configuration using nonvolatile memory elements according to the present invention, and FIG. 35 is a partial plan view thereof. FIG. 36 shows a principle diagram of the writing method. In FIG. 34, in the memory array of the NAND configuration, nonvolatile storage elements are connected in series, MOSFETs forming column switches are provided on the data lines (or bit lines) D0 and D1, and the other end is connected to the circuit. A switch MOSFET is provided between the switch MOSFET and the ground potential point.
This configuration is basically the same as the vertical mask ROM except that the storage MOSFET is a nonvolatile storage element and the switch MOSFET is provided.

In FIG. 35, a word line WL made of an aluminum layer extending in the vertical direction is commonly contacted with a diffusion layer forming a control gate corresponding to two adjacent data lines DL, and overlaps with this diffusion layer. A non-volatile memory element having a single-layer gate structure is formed by extending a hatched control gate across a data line DL constituting a source and a drain extending in the horizontal direction and connected in series. Is done. By adopting such a layout, the occupied area can be reduced by about 4 times as compared with a conventional horizontal (NOR) memory array.
It can be reduced to 2%.

In FIG. 36, writing is performed sequentially from the source side in the nonvolatile memory element in the serial form. At this time, the control signal SW is set to a low level such as the ground potential so that the DC current does not flow in the series circuit at the time of writing, and the switch MOSFET is turned off. In the initial state, the threshold voltage of the nonvolatile memory element has a positive voltage (enhancement mode).

In this state, writing is performed from the nonvolatile memory element connected to the word line W7, and the word line W7 is set to a low level such as the ground potential, and the other word lines W6 to W
1 and the control voltages Y0 and Y1 of the column switches are set to relatively high voltages. If the write data D0 is low level,
Since no electric field acts between the control gate and the drain, no tunnel current flows from the floating gate to the drain, and the threshold voltage (Vth> 0)
Remains. On the other hand, if the write data D0 is at a high level at a relatively high voltage, a high electric field acts between the control gate and the drain, causing a tunnel current to flow from the floating gate to the drain, and the threshold voltage (Vth <0).

Thereafter, similarly, writing is performed by setting the selected word line to the low level in the order of W6 to W0. In such a write operation, only a tunnel current flows, so that the write current is small, and a current clamp or the like as in the case of the NOR type configuration is not required, thereby simplifying the circuit configuration.

At the time of reading, the control signal SW is set to the high level to turn on the switch MOSFET. In this state, the conventional memory cell is read out in the same manner as the conventional vertical ROM because the depletion type is the enhancement type according to the stored information as described above.

FIG. 37 is a circuit diagram showing an embodiment in which the nonvolatile memory element according to the present invention is used to enable erasure even electrically. In this embodiment, data is written using hot carriers as in a conventional EPROM, and data is erased using a tunnel current as shown in FIG. That is, data writing is performed in the same manner as shown in FIG. When erasing data, the word line of the nonvolatile storage element to be erased is set to low level. Thereby, the P-channel MOS
When the FET Q2 is turned on, a high level (Vpp) is supplied to the source line, and a high electric field is applied between the control gate and the source in the same manner as shown in FIG. A tunnel current is caused to flow. The MOSFET Q3 is turned off at the time of writing and turned on at the time of erasing by the control signal RW. MOSFET Q1 is turned on according to the selection / selection of the word line.

At the time of reading, the source of the nonvolatile memory element connected to the non-selected word line is opened by the off state of the MOSFET Q1, so that even if the nonvolatile memory element is overerased and becomes the depletion state, the nonvolatile memory element remains in the depleted state. No leakage current flows and no problem occurs in reading.

FIGS. 38A and 38B are layout diagrams of one embodiment of the semiconductor integrated circuit device according to the present invention. The embodiment shown in the figure is directed to a case where a relief circuit using a nonvolatile memory element according to the present invention is mounted on a mask ROM.

In FIG. 38A, a pad is provided at the center of the chip, and a relief circuit is provided between the pad and the memory mat MAT as indicated by diagonal lines.

In FIG. 38 (B), a relief circuit is provided between the pads arranged in a zigzag manner in two rows provided at the center of the chip, as indicated by diagonal lines.

In the above configuration, 1) Since the stress at the center of the chip is small when it is sealed in a package, the characteristic fluctuation of the nonvolatile memory element is small.
In addition, reliability can be increased. 2) When the mask ROM has a large capacity, a power supply line, a ground line, or a signal line becomes long. As a result, a malfunction due to signal delay or noise becomes a problem. As a countermeasure, it is necessary to arrange the pad at the center of the chip. In this case, the position where the relief circuit is arranged is desirably around the pad where the space can be obtained most easily. This can prevent an increase in chip size.

FIGS. 39A and 39B are layout diagrams of another embodiment of the semiconductor integrated circuit device according to the present invention. The embodiment shown in the figure is directed to a case where a relief circuit using a nonvolatile memory element according to the present invention is mounted on a microcomputer.

In FIG. 39A, the relief circuits shaded with diagonal lines are combined in one place on the chip. In this configuration, it is possible to easily input a data line from the outside to the relief circuit.

In FIG. 39B, the rescue circuit is provided for each functional block to be rescued, for example, μROM, ROM,
They are distributed and arranged in a RAM or an ADC (analog / digital conversion circuit). In this configuration, since the relief circuit is provided close to the corresponding circuit, the delay time at the time of relief can be shortened.

FIGS. 40A and 40B are circuit diagrams of an embodiment of a pad used for a write operation to a nonvolatile memory element. In FIG. 40A, a P-channel MOSFET having a high resistance value for pulling up a pad to a power supply voltage Vcc is provided. FIG. 40 (B)
Is provided with an N-channel MOSFET having a high resistance value for pulling down the pad to the ground potential of the circuit.

As described above, when relieving or changing functions, 1
Pull-up or pull-down resistance elements are provided for pads used for a write operation to a nonvolatile memory element having a layer gate structure, and these pads are not directly connected to external terminals. With such a configuration, an increase in the number of external terminals can be prevented. Further, in the semiconductor integrated circuit device in which the defect relief or the function change is performed as described above, the pad used for the pad is pulled up or pulled down to a fixed level, so that the pad has an undesired potential. Malfunction can be prevented. The resistance element to be pulled up or down is a high resistance M as described above.
Instead of the OSFET, polysilicon or the like may be used.

FIG. 41 is a flowchart for explaining one embodiment of the trimming method. FIG.
In the embodiment of FIG. 1A, trimming data is determined after being sealed in a package by a terminal shared with an external terminal or another terminal.

In the embodiment shown in FIG. 41B, of a plurality of bits of data used for trimming, before encapsulation in a package, in other words, in a probing process when a chip is completed on a semiconductor wafer. The upper bits are determined and rough trimming is performed. After the chip is sealed in a package, the remaining lower bits are determined and minute trimming is performed. By employing such a trimming method, it is possible to perform highly accurate trimming that can cope with minute fluctuations in element characteristics caused by heat treatment or the like when a chip is sealed in a package.

FIG. 42 is a flow chart of an embodiment in which writing is performed after the package is sealed in the nonvolatile memory element according to the present invention. In the chip forming step, a desired semiconductor integrated circuit is formed on a semiconductor wafer as described above.

In the test step, a test is performed on a semiconductor integrated circuit including a nonvolatile memory element. The test of the nonvolatile memory element performs both the state before writing data and the state after writing data.

In the erasing step, the nonvolatile memory element is returned to the initial state. That is, the state before writing data is set. The erasing operation is performed by irradiating ultraviolet rays when the nonvolatile storage element is an EPROM. In the nonvolatile memory element having a one-layer gate structure of this embodiment, a barrier layer made of aluminum or the like is provided on the floating gate. The aluminum layer itself does not transmit ultraviolet light, but can be erased by diffracting or irregularly reflecting ultraviolet light. In particular, when the barrier layer is provided only on a part of the floating gate as in the above embodiment or when the slit is provided, the erasing can be efficiently performed. Even if the entire surface of the floating gate is covered with aluminum to prevent the radical hydrogen from the final passivation film from reaching the floating gate, the distance that the barrier layer extends from the floating gate is short, as described above. It can be sufficiently erased by diffraction and irregular reflection of ultraviolet rays.

It is to be noted that a two-layer gate structure EP as in the prior art is used.
In a ROM, when an EPROM having a two-layer gate structure for relieving defects is used for address conversion, the aluminum layer is subjected to address conversion in order to prevent the address conversion section from being erased by the erasing operation of the memory array section. Covering the entire surface of the unit is performed. In this case, a large aluminum shielding film is formed in consideration of diffraction and irregular reflection of erasing ultraviolet rays in the memory array section. Therefore, even in the same aluminum layer, in the nonvolatile memory element having the single-layer gate structure according to the present invention, an aluminum layer as a barrier layer for preventing radical hydrogen from entering the floating gate from the final passivation film is provided. Are fundamentally different in their technical ideas.

In the encapsulation step, chips of which the test results are good among the chips individually separated from the semiconductor wafer are encapsulated in a package. In the data storage step, desired data is stored in the nonvolatile storage element. Since a test of the nonvolatile memory element is performed in the test step, a good semiconductor integrated circuit device can be obtained regardless of what data is stored in the nonvolatile memory element in the data storage step. .

The above-described test process is effective for any nonvolatile memory element. In particular, in the case where the nonvolatile memory element is an EPROM and is sealed in a package made of plastic or the like that does not transmit ultraviolet rays, the paraphrase is applied. Then, this is effective when the erasing function by ultraviolet rays is disabled and the nonvolatile memory element is used for one-time writing.

The non-volatile memory element having a single-layer gate structure according to the present invention can be used not only for relieving defects in a mask ROM, but also
It may be used for changing or correcting OM data. Further, the present invention may be applied to a PLD using a non-volatile memory element as a logic decision element, and used to set / change a circuit function. When a nonvolatile memory element having a single-layer gate structure is used for setting or changing the function of such a mask ROM or digital integrated circuit, it is only necessary to add a diffusion layer forming a control gate.
In a CMOS circuit, since a well region can be used, it is unnecessary, and the manufacturing process can be simplified as compared with the case where a nonvolatile memory element having a two-layer gate structure is used.

Since the barrier layer is provided in the nonvolatile memory element having the single-layer gate structure, high reliability can be obtained. The nonvolatile memory element having the single-layer gate structure of this embodiment may constitute one semiconductor memory device by itself. However, the cell size is significantly larger than that of a nonvolatile memory element having a two-layer gate structure. Therefore, the nonvolatile memory element having the single-layer gate structure of this embodiment is suitable for a small-capacity memory circuit for relieving defects of a memory circuit such as a mask ROM and setting / changing a function of a digital circuit. I have.

The functions and effects obtained from the above embodiment are as follows. That is, (1) a barrier layer is formed so as to cover the entire upper surface of a floating gate formed of a conductor layer formed so that a part thereof overlaps a control gate formed of a diffusion layer via a thin insulating film. By doing so, it is possible to obtain an effect that data retention characteristics can be significantly improved.

(2) When a nitride passivation film formed by a plasma CVD method is used as a final passivation film in a semiconductor integrated circuit device, an inexpensive plastic package can be used. The effect is obtained that an inexpensive semiconductor integrated circuit device can be obtained while improving.

(3) The barrier layer uses a conductor layer or an oxide film formed by a plasma-CVD method, thereby retaining data of a nonvolatile memory element having a single-layer gate structure without adding a special manufacturing process. The effect that characteristics can be improved is obtained.

(4) By forming the barrier layer integrally with a word line made of an aluminum layer to which the control gate is connected, the effect that the barrier layer can be easily formed can be obtained.

(5) The nonvolatile memory element having the single-layer gate structure provided with the barrier layer is used for relieving defects or setting / changing functions of a mask ROM or a digital circuit, thereby preventing an increase in the number of manufacturing steps. The effect is obtained that the defect can be repaired and the function can be set / changed with high reliability.

(6) Analog circuit and ROM or RAM
In the semiconductor integrated circuit device including the above, the effect is obtained that the ROM or the RAM can be relieved before the package is sealed, and the analog circuit can be trimmed after the package is sealed.

(7) By using a non-volatile memory element having a single-layer gate structure provided with a barrier layer for repairing a defect in a mask ROM or modifying data for modification, high reliability can be achieved without increasing the manufacturing process or the occupied area. Under such circumstances, it is possible to obtain the effect that the defect can be repaired and the data can be corrected and changed.

(8) The source of the nonvolatile memory element having a single-layer gate structure composed of a plurality of layers corresponding to the word lines is connected to the common source line, and the circuit of the circuit is controlled by the switch element which is switch-controlled by the corresponding word line selection signal. By applying the ground potential, it is possible to prevent the occurrence of a leak current in the storage element of the non-selected word line, and to obtain an effect that the withstand voltage can be improved accordingly.

(9) The nonvolatile memory elements arranged in a matrix form one based on write data held in a latch circuit provided on a data line to which the nonvolatile memory elements are coupled.
By simultaneously writing data to a plurality of memory cells connected to one word line, the effect of shortening the writing time can be obtained.

(10) The word line selection signal can be simplified by using a drive circuit that forms an output level in accordance with the conductance ratio between the load MOSFET and the drive MOSFET. A switch element for applying a ground potential to a common source of the above-described method transmits a selection signal formed by a CMOS circuit through a sub-word line, thereby effectively preventing the occurrence of leakage current. can get.

(11) The nonvolatile storage element is an EPROM
As in the case of (1), the voltage Vcc for performing the normal operation is set to a relatively small voltage such as 5 V in the normal state, and is set to a high voltage such as 7 V or 8 V in the write operation. Thus, there is no need to use a high breakdown voltage MOSFET as a write-related circuit, and an effect is obtained that the manufacturing process of the semiconductor integrated circuit can be simplified.

The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say. For example, the barrier layer may be formed below the final passivation film and above the floating gate layer. Various embodiments can be employed for the pattern of the nonvolatile memory element having the single-layer gate structure.

In the nonvolatile memory element having the single-layer gate structure according to the present invention, writing is performed by hot carriers and erasing is performed by applying a high voltage to the source or drain with a tunnel current, or writing and erasing are performed by a tunnel current. It can also be used as an electrically writable and erasable nonvolatile storage element.

The present invention can be widely used for a non-volatile memory element having a single-layer gate structure itself and a semiconductor integrated circuit device using the same for function setting or change, a redundant circuit, or the like.

[0169]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, by providing a microprocessor, an input / output port, a RAM, and an element for storing data necessary for address conversion for performing a defect remedy on the RAM on one semiconductor substrate, the defect remedy can be prevented while preventing an increase in the number of manufacturing steps. And function changes become possible.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of an embodiment for explaining a nonvolatile memory element according to the present invention.

FIG. 2 is a sectional view of an element structure showing another embodiment of the nonvolatile memory element according to the present invention.

FIG. 3 is a sectional view of an element structure showing still another embodiment of the nonvolatile memory element according to the present invention.

FIG. 4 is an element pattern diagram showing one embodiment of a nonvolatile memory element according to the present invention.

FIG. 5 is an element pattern diagram showing another embodiment of the nonvolatile memory element according to the present invention.

FIG. 6 is a block diagram showing an embodiment of a mask ROM to which the present invention is applied.

FIG. 7 is a circuit diagram showing one embodiment of a redundant word line selection circuit RAST in the mask ROM of FIG. 6;

8 is a circuit diagram showing one embodiment of a relief address selection circuit RAS in the mask ROM of FIG.

9 is a circuit diagram showing one embodiment of a relief address storage circuit PR-ADD in the mask ROM of FIG.

FIG. 10 is a circuit diagram showing one embodiment of a write data input circuit PR-PGC in the mask ROM of FIG. 6;

11 is a circuit diagram showing one embodiment of a Y decoder circuit PR-YDC for redundancy in the mask ROM of FIG. 6;

FIG. 12 shows a redundant memory mat PR-MAT and a column switch gate PR-YG in the mask ROM of FIG.
FIG. 3 is a circuit diagram illustrating an example of a T and a sense amplifier circuit PR-SAM.

FIG. 13 is a circuit diagram showing one embodiment of a multiplexer MPX in the mask ROM of FIG. 6;

FIG. 14 is a circuit diagram showing another embodiment of the mask ROM to which the present invention is applied.

FIG. 15 is a circuit diagram showing another embodiment of the redundant memory mat and its peripheral circuits according to the present invention.

FIG. 16 is a data retention characteristic diagram of a nonvolatile memory element for explaining the present invention.

FIG. 17 is a sectional view of an element structure showing another embodiment of the nonvolatile memory element according to the present invention.

18 is a plan view of the nonvolatile memory element in FIG.

FIG. 19 is an element structure sectional view showing another embodiment of the nonvolatile memory element according to the present invention.

20 is a plan view of the nonvolatile memory element in FIG.

FIG. 21 is a sectional view of an element structure showing another embodiment of the nonvolatile memory element according to the present invention.

FIG. 22 is a plan view of the nonvolatile memory element in FIG. 21;

FIG. 23 is a plan view showing another embodiment of the nonvolatile memory element according to the present invention.

FIG. 24 is a manufacturing process sectional view for explaining another embodiment of the nonvolatile memory element according to the present invention.

FIG. 25 is a plan view of the nonvolatile memory element in FIG. 24;

FIG. 26 is a manufacturing process sectional view for explaining still another embodiment of the nonvolatile memory element according to the present invention.

FIG. 27 is a cross-sectional view of an element structure showing an embodiment of a semiconductor integrated circuit device in a case where a nonvolatile memory element having a single-layer gate structure according to the present invention is used for relief of a dynamic RAM.

FIG. 28 is a plan view corresponding to FIG. 27 (B).

FIG. 29 is a block diagram showing one embodiment of a dynamic RAM incorporating a defect rescue circuit using a nonvolatile memory element according to the present invention.

FIG. 30 is a block diagram showing an embodiment in which the nonvolatile memory element according to the present invention is used for rescue of a microcomputer or the like.

FIG. 31 is a sectional view of an element structure showing an embodiment in which a nonvolatile memory element having a one-layer gate structure according to the present invention is mounted on a conventional EPROM having a two-layer gate structure.

FIG. 32 is a cross-sectional view of an element structure showing an embodiment when the nonvolatile memory element according to the present invention is used for trimming of a semiconductor integrated circuit device including an analog circuit.

FIG. 33 is a circuit diagram showing one embodiment of the trimming circuit of FIG. 32;

FIG. 34 is a circuit diagram showing one embodiment of a memory array having a vertical configuration using a nonvolatile memory element according to the present invention.

FIG. 35 is a plan view showing one embodiment of the memory cell of FIG. 34;

FIG. 36 is a principle view showing one embodiment of a writing method of the nonvolatile memory element in FIG. 34;

FIG. 37 is a circuit diagram showing one embodiment in a case where the nonvolatile memory element according to the present invention can be electrically erased.

FIG. 38 is a layout diagram showing one embodiment of a semiconductor integrated circuit device (mask ROM) according to the present invention.

FIG. 39 is a layout diagram showing one embodiment of a semiconductor integrated circuit device (microcomputer) according to the present invention.

FIG. 40 is a circuit diagram showing one embodiment of a pad used for a write operation to a nonvolatile memory element.

FIG. 41 is a flowchart showing one embodiment of a trimming method.

FIG. 42 is a flowchart showing one embodiment in which writing is performed on the nonvolatile memory element according to the present invention after the package is sealed;

[Explanation of symbols]

QE..Non-volatile memory element, QN..N channel MO
SFET, QP ... P-channel MOSFET, QHN
..High voltage N-channel MOSFET, QHP High voltage P-channel MOSFET, QD dynamic memory cell, QM mask memory cell, QEP
EPROM with two-layer gate structure, QR-resistance element, QC
..Capacitive element, 1..semiconductor substrate, 2,102..well region, 3..field insulating film, 4..channel stopper, 7,107..gate insulating film, 5,11,1
3,16,201,211 ··· insulating film (interlayer insulating layer)
8, 108, 204, 205 ··· conductive layer, 15, 17 ·
.Wiring layers, 6, 9, 10, 109, 112. .. diffusion layers,
14,114 contact hole, 18 final passivation film, 204 dielectric film, ADB
Address buffer, MR-MAT, Mask ROM,
OR-MAT..redundant memory circuit, XDC..X decoder circuit, MR-YGT, PR-YGT..column switch gate, YDC..Y decoder circuit, MR-SA
M, PR-SAM sense amplifier circuit, DIB input buffer circuit, DOB output buffer circuit, MPX
..Multiplexer, RAS, relief address selection circuit, R-ADD, relief address storage circuit, RAST
.Redundant word line selection circuit, CONT ..control circuit, PR
-PGC write data input circuit, WA write circuit, FF latch circuit, DEC decoder circuit, TRC1 to TRC3 trimming circuit, AMP
・ Op amp, μROM ・ ・ Micro program RO
M, ROM, read only memory, RAM
Random access memory, CPU, microprocessor, ADC, analog / digital conversion circuit, P
ORT ... I / O port.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/822 G11C 17/00 639B 27/115 H01L 21/82 R 27/10 461 27/04 E 481 27 / 10 434 491 621C 27/108 29/78 371 21/8242 21/8247 29/788 29/792 (72) Inventor Toshifumi Takeda 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo Musashi Hitachi, Ltd. Inside the plant (72) Inventor Hisahiro Moriuchi 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside Musashi Plant, Hitachi, Ltd. (72) Inventor Masayoshi Shirai 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Musashi Plant of Hitachi, Ltd. (72) Inventor Jiro Sakaguchi 5-2-1, Kamisumihonmachi, Kodaira-shi, Tokyo Inside the Musashi Plant of Hitachi, Ltd. (72) Inventor Akinori Matsuo Small in Tokyo 5-20-1, Honcho, Josui-shi, Japan Nippon Cho LSI Engineering Co., Ltd. (72) Inventor Shoji Yoshida 5-2-1, Joshonhoncho, Kodaira-shi, Tokyo Nichicho Cho LS・ I Engineering Co., Ltd.

Claims (14)

[Claims] 1. A semiconductor substrate comprising, on a main surface thereof, a microprocessor, an input / output port, a RAM, and an element for storing data necessary for address conversion for repairing defects in the RAM, and a central portion of the main surface. A semiconductor integrated circuit device, wherein a pad is provided on the pad, and the element is provided between the pad and the RAM. 2. A semiconductor device comprising: a main surface of a semiconductor substrate; a microprocessor; an input / output port; a RAM; and an element for storing data necessary for address conversion for repairing defects in the RAM. A pad arranged in two rows in a zigzag pattern, and the element is provided between the pads. 3. An acroprocessor formed in a first region of a main surface of a semiconductor substrate, a first memory mat formed in a second region of the main surface and including a first memory cell, and A second memory cell formed in the third region and having a memory cell structure different from the memory cell structure of the first memory cell;
A semiconductor integrated circuit device, comprising: a second memory mat including a memory cell; and a rescue circuit formed on the main surface to rescue the first memory mat and the second memory mat. 4. The semiconductor integrated circuit device according to claim 3, wherein said first memory mat is a random access memory, and said second memory mat is a read only memory. 5. The repair circuit according to claim 3, wherein the repair circuit includes a redundant memory cell and a redundant decoder for selecting the redundant memory cell, and the redundant memory cell includes a nonvolatile memory cell. 13. The semiconductor integrated circuit device according to claim 1. 6. A microprocessor formed in a first region of a main surface of a semiconductor substrate, a random access memory formed in a second region of the main surface of the semiconductor substrate and including a memory cell, The first surface is formed in a third region of the main surface.
A semiconductor, comprising: a first nonvolatile memory including a nonvolatile memory cell; and a relief circuit formed on the main surface of the semiconductor substrate to remove the random access memory and the first nonvolatile memory. Integrated circuit device. 7. The semiconductor device according to claim 6, wherein said rescue circuit has a second nonvolatile memory for storing an address of said random access memory to be relieved and an address of said first nonvolatile memory. Integrated circuit device. 8. A second nonvolatile memory included in the second nonvolatile memory.
8. The semiconductor integrated circuit device according to claim 7, wherein the nonvolatile memory cell has a single-layer gate structure. 9. The semiconductor integrated circuit device according to claim 6, wherein the memory cells of the random access memory are dynamic memory cells. 10. The rescue circuit has a first rescue circuit formed in the second area and a second rescue circuit formed in the third area, wherein the first rescue circuit is the random access memory. 10. The semiconductor integrated circuit device according to claim 6, wherein the second relief circuit is provided near the first nonvolatile memory. 11. The semiconductor integrated recycle device according to claim 8, wherein the first nonvolatile memory cell has a structure in which a control gate is formed on a floating gate. 12. The semiconductor integrated circuit device according to claim 11, wherein said first nonvolatile memory cell is programmed or erased by a tunnel current between said floating gate and said substrate. 13. A microprocessor formed in a first region of a main surface of a semiconductor substrate, a random access memory formed in a second region of the main surface of the semiconductor substrate and including a memory cell; A read-only memory formed in a third region of the main surface and including a memory cell; and a read-only memory formed on the main surface of the semiconductor substrate and used for a relief circuit for rescuing the random access memory and the read-only memory. 1. A semiconductor integrated circuit device comprising: a non-volatile memory. 14. The semiconductor integrated circuit device according to claim 13, wherein said first nonvolatile memory cell stores an address of said random access memory to be repaired and an address of said read only memory.