JP2000307038A - Chip size package(csp) and manufacture thereof - Google Patents

Chip size package(csp) and manufacture thereof

Info

Publication number
JP2000307038A
JP2000307038A JP11116509A JP11650999A JP2000307038A JP 2000307038 A JP2000307038 A JP 2000307038A JP 11116509 A JP11116509 A JP 11116509A JP 11650999 A JP11650999 A JP 11650999A JP 2000307038 A JP2000307038 A JP 2000307038A
Authority
JP
Japan
Prior art keywords
chip
resin
bare
heat transfer
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11116509A
Other languages
Japanese (ja)
Inventor
Masami Ishii
正美 石井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP11116509A priority Critical patent/JP2000307038A/en
Publication of JP2000307038A publication Critical patent/JP2000307038A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

PROBLEM TO BE SOLVED: To provide a CSP of excellent heat radiation. SOLUTION: A CSP 10 comprises an interposer substrate 12, a bare IC chip 16 mounted on a chip pad 14 comprising a solder resist on the interposer substrate with an adhesive layer 15, a resin insulating layer 18, and a heat-radiation plate 22 bonded through an epoxy resin layer 20. A backside electrode 26 with a solder ball 28 for an electrode is provided away from each other between a backside pad insulating part 24 and an inter-chip insulating part 25 when the CSP 10 is mounted on a motherboard, on the backside of the interposer substrate 10. On the front surface of interposer substrate, a substrate junction electrode 32 is provided, which is wire-bonded to an electrode 30 of the bare IC chip. On the outside of the substrate junction electrode, a heat-transfer pad 36 is provided with an inter-electrode insulating part 34 in between. The heat- transfer pad is thermally connected to the heat-radiation plate with the head- conductor 38 penetrating the insulating layer and epoxy resin layer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、チップサイズ・パ
ッケージ（以下、ＣＳＰと言う）及びその作製方法に関
し、更に詳細には、放熱性及びノイズ遮蔽性に優れたＣ
ＳＰ及びその作製方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip-size package (hereinafter referred to as a CSP) and a method of manufacturing the same, and more particularly, to a C-type package excellent in heat dissipation and noise shielding.
The present invention relates to an SP and a method for manufacturing the SP.

【０００２】[0002]

【従来の技術】最近の電子機器の小型化に伴ない、それ
を実現する手法として半導体装置を含む電子部品を実装
基板上に高密度実装する表面実装法が注目され、その一
環としてＱＦＰ型、ＳＯＰ型等の半導体パッケージを更
に小型化したチップサイズ・パッケージ（ＣＳＰ（Chip
Size Package ））の研究、開発が、盛んになってい
る。2. Description of the Related Art Along with the recent miniaturization of electronic equipment, a surface mounting method for mounting electronic components including a semiconductor device on a mounting board at a high density has been attracting attention as a technique for realizing it. A chip size package (CSP (Chip)
Research and development of Size Package)) has become active.

【０００３】ここで、図６を参照して、従来のＣＳＰの
構成を説明する。図６は従来のＣＳＰの構成を示す断面
図である。従来のＣＳＰ５０は、図６に示すように、イ
ンターポーザ基板５２と、インターポーザ基板５２上の
金属製（例えば銅箔製）チップ・パッド５４に接着剤層
５５によって固着されたベアＩＣチップ５６と、ベアＩ
Ｃチップ５６を封止した樹脂絶縁層５８とを備えてい
る。また、ＣＳＰ５０は、ベアＩＣチップ５２とは反対
側のインターポーザ基板５２の裏面には、ＣＳＰ５０を
マザー基板（図示せず）に実装する際に電極となるはん
だボール６０付き裏面電極６２が、所定数（図６では、
簡単に４個のみ図示）、相互に離隔して設けられてい
る。更に、チップ・パッド５４と対向するインターポー
ザ基板５２の裏面位置には、放熱板６４が設けられ、チ
ップ・パッド５４及びインターポーザ基板５２を貫通す
るサーマルビアを導電ペーストで充填してなる伝熱体６
６を介してベアＩＣチップ５６で発生する熱を放熱す
る。Here, the configuration of a conventional CSP will be described with reference to FIG. FIG. 6 is a sectional view showing a configuration of a conventional CSP. As shown in FIG. 6, a conventional CSP 50 includes an interposer substrate 52, a bare IC chip 56 fixed to a metal (for example, copper foil) chip pad 54 on the interposer substrate 52 by an adhesive layer 55, I
A resin insulating layer 58 in which the C chip 56 is sealed. The CSP 50 has a predetermined number of back electrodes 62 with solder balls 60 serving as electrodes when the CSP 50 is mounted on a mother board (not shown) on the back surface of the interposer substrate 52 opposite to the bare IC chip 52. (In FIG. 6,
(Only four are simply shown), and are provided separately from each other. Further, a heat radiating plate 64 is provided at a rear surface position of the interposer substrate 52 facing the chip pad 54, and a heat transfer member 6 is formed by filling a thermal via penetrating the chip pad 54 and the interposer substrate 52 with a conductive paste.
6, the heat generated in the bare IC chip 56 is radiated.

【０００４】インターポーザ基板５２の表面上では、基
板中継電極７２が、ベアＩＣチップ５６の両側に設けら
れ、金線６８によってベアＩＣチップ５６の電極７０と
ワイヤーボンディングされている。また、基板中継電極
７２の外側にも必要な配線パターン７４が設けてある。On the surface of the interposer substrate 52, substrate relay electrodes 72 are provided on both sides of the bare IC chip 56, and are wire-bonded to the electrodes 70 of the bare IC chip 56 by gold wires 68. Also, a necessary wiring pattern 74 is provided outside the substrate relay electrode 72.

【０００５】[0005]

【発明が解決しようとする課題】しかし、従来のＣＳＰ
では、ベアＩＣチップで発生する熱を放熱する放熱板が
小さく、放熱性が悪いという問題があった。そこで、本
発明の目的は、放熱性に優れたＣＳＰを提供することで
ある。However, the conventional CSP
In this case, there is a problem that a heat radiating plate for radiating heat generated in the bare IC chip is small and heat radiation is poor. Then, an object of the present invention is to provide a CSP excellent in heat dissipation.

【０００６】[0006]

【課題を解決するための手段】本発明者は、従来のＣＳ
Ｐの低放熱性を改善する方策として、例えば配線、電極
等を除いた、インターポーザ基板の表面及び裏面の空き
領域に銅箔による放熱又はヒートシンク層を設けること
を考えたが、空き領域が小さくて、効果がなく、また、
別途、インターポーザ基板の表面又は裏面に放熱・ヒー
トシンク層を設けようとすると、インターポーザ基板の
高密度実装化が難しくなって、ＣＳＰの寸法が大きくな
る。また、本発明者は、ベアＩＣチップを樹脂封止して
いる樹脂封止体上に金属層を設け、放熱・ヒートシンク
板とすることを考えたが、ベアＩＣチップとインターポ
ーザ基板の基板中継電極とを金線等でワイヤーボンディ
ングしたワイヤーボンディング接続方式のＣＳＰは、ワ
イヤーボンド接続したベアＩＣの保護膜であるモールド
樹脂層が平滑でないため、その上に金属層を設けて、ヒ
ートシンク、ヒート・スプレッダーとすることが困難で
ある。Means for Solving the Problems The present inventor has developed a conventional CS.
As a measure to improve the low heat radiation property of P, for example, it is considered to provide a heat radiation or a heat sink layer by a copper foil in a vacant area on the front and back surfaces of the interposer substrate except for wiring, electrodes, etc., but the vacant area is small. Has no effect,
Separately, if a heat radiation / heat sink layer is to be provided on the front surface or the back surface of the interposer substrate, it is difficult to mount the interposer substrate at a high density, and the size of the CSP increases. In addition, the present inventor considered that a metal layer was provided on a resin sealing body for sealing a bare IC chip with a resin, and used as a heat dissipation / heat sink plate. However, the bare IC chip and a substrate relay electrode of an interposer substrate were considered. In the CSP of the wire bonding connection method in which the wire bonding is performed by a gold wire or the like, since the mold resin layer which is the protective film of the bare IC which is wire bonded is not smooth, a metal layer is provided thereon, and a heat sink and a heat spreader are provided. It is difficult to do.

【０００７】ところで、フリップチップ接続方式のＣＳ
Ｐは、ベアＩＣチップが脆いために、ベアＩＣチップの
裏面（回路形成していない面）に金属層を設けること
が、プロセス的に困難であるから、従来のＣＳＰの構成
をフリップチップ接合タイプのＣＳＰに適用すること
は、その適用自体が、技術的に難しいと言わざるを得な
い。そこで、本発明者は、ワイヤーボンディング接続方
式のみならずフリップチップ接続方式のＣＳＰに適用で
きるように、表面が平滑なモールド樹脂層でベアＩＣチ
ップを封止し、モールド樹脂層の平滑な表面上に金属層
からなる放熱・ヒートシンク板を形成することを着想
し、本発明を完成するに到った。By the way, flip-chip connection type CS
In the case of P, since the bare IC chip is brittle, it is difficult to provide a metal layer on the back surface (the surface on which no circuit is formed) of the bare IC chip in terms of process. Is difficult to apply to the CSP itself. Therefore, the inventor of the present invention sealed a bare IC chip with a mold resin layer having a smooth surface so that the bare IC chip could be applied not only to a wire bonding connection method but also to a flip chip connection method CSP. The present invention was completed with the idea of forming a heat radiation / heat sink plate made of a metal layer.

【０００８】上記目的を達成するために、本発明に係る
チップサイズ・パッケージ（ＣＳＰ）は、インターポー
ザ基板上に搭載されたベアＩＣチップ及びインターポー
ザ基板上に設けられた金属製伝熱パッドと、インターポ
ーザ基板上に形成され、ベアＩＣチップ及び金属製伝熱
パッドを樹脂封止する樹脂絶縁層と、樹脂絶縁層上に設
けられた金属製放熱板と、樹脂絶縁層を貫通し、下端で
伝熱パッドに、上端で放熱板に、それぞれ接触して、伝
熱パッドから放熱板に熱を伝熱する伝熱体とを備えてい
ることを特徴としている。In order to achieve the above object, a chip size package (CSP) according to the present invention comprises a bare IC chip mounted on an interposer substrate, a metal heat transfer pad provided on the interposer substrate, and an interposer. A resin insulating layer formed on a substrate and resin-sealing a bare IC chip and a metal heat transfer pad; a metal heat sink provided on the resin insulating layer; It is characterized in that the pad is provided with a heat transfer body that is in contact with the radiator plate at the upper end, and transfers heat from the heat transfer pad to the radiator plate.

【０００９】本発明を適用するベアＩＣチップは、フェ
ースダウンのフリップチップ接続方式のベアＩＣチップ
でも、フェースアップのワイヤーボンディング接続方式
のベアＩＣチップでも良い。また、インターポーザ基板
は、両面配線基板でも、多層基板構造の最上層の配線基
板でも良い。本発明の放熱板は、放熱機能のみならずヒ
ートシンク機能も有するものであって、好適には樹脂絶
縁層の全面に形成されている。本発明では、放熱板をＣ
ＳＰの上面全面に備えているので、放熱性に優れ、しか
も放熱板によってノイズ信号を遮蔽するので、外部ノイ
ズの影響を軽減することができる。The bare IC chip to which the present invention is applied may be a face-down flip-chip type bare IC chip or a face-up wire bonding type bare IC chip. Further, the interposer substrate may be a double-sided wiring substrate or a wiring substrate in the uppermost layer of a multilayer substrate structure. The heat sink of the present invention has a heat sink function as well as a heat dissipation function, and is preferably formed on the entire surface of the resin insulating layer. In the present invention, the heat sink is C
Since the heat radiation plate is provided on the entire upper surface of the SP, the heat radiation is excellent, and since the noise signal is shielded by the heat radiation plate, the influence of external noise can be reduced.

【００１０】本発明の好適な実施態様では、樹脂絶縁層
が、低内部応力のエポキシ系熱硬化性樹脂で形成されて
いる。これにより、インターポーザ基板の反り等の変形
を抑制し、ベアＩＣチップとインターポーザ基板との間
の接続信頼性を向上させることができる。In a preferred embodiment of the present invention, the resin insulating layer is formed of a low internal stress epoxy thermosetting resin. Thereby, deformation such as warpage of the interposer substrate can be suppressed, and connection reliability between the bare IC chip and the interposer substrate can be improved.

【００１１】本発明の別の好適な実施態様では、ベアＩ
Ｃチップが、インターポーザ基板に形成された絶縁性チ
ップ・パッド上に搭載され、かつ、ベアＩＣチップへの
入出力配線がチップ・パッド内に延在する。これによ
り、インターポーザ基板上の実装密度が更に高くするこ
とができる。本発明の別の好適な実施態様では、放熱板
が、樹脂層付き銅箔（レジン・コーティング・カッパー
（ＲＣＣ））の樹脂側を樹脂絶縁層に接着させてなる銅
箔で形成されている。これにより、放熱板の形成が容易
になる。本発明の別の好適な実施態様では、伝熱体は、
樹脂絶縁層を貫通する孔に導電性ペーストを充填してな
る充填体として形成されているか、又は樹脂絶縁層を貫
通する孔の孔壁に沿って設けられた金属めっき層として
形成されている。In another preferred embodiment of the present invention, a bare I
A C chip is mounted on an insulating chip pad formed on an interposer substrate, and input / output wiring to a bare IC chip extends into the chip pad. Thereby, the mounting density on the interposer substrate can be further increased. In another preferred embodiment of the present invention, the heat sink is formed of a copper foil having a resin layer adhered to a resin insulating layer on a resin side of a resin layer-coated copper foil (resin coating copper (RCC)). This facilitates the formation of the heat sink. In another preferred embodiment of the present invention, the heat transfer element comprises:
It is formed as a filling body formed by filling a conductive paste into a hole penetrating the resin insulating layer, or is formed as a metal plating layer provided along a hole wall of the hole penetrating the resin insulating layer.

【００１２】本発明に係るＣＳＰの作製方法は、ベアＩ
Ｃチップをパッケージしたチップサイズ・パッケージ
（ＣＳＰ）の作製方法であって、ベアＩＣチップを搭載
するチップ・パッドをインターポーザ基板の表面に形成
する工程と、インターポーザ基板の表面に金属製伝熱パ
ッドを形成する工程と、インターポーザ基板のチップ・
パッド上にベアＩＣチップを固着させる工程と、インタ
ーポーザ基板のベアＩＣチップ側に樹脂絶縁層を形成し
て、ベアＩＣチップを樹脂封止する工程と、樹脂層付き
銅箔（ＲＣＣ（レジン・コーティング・カッパー））の
樹脂層を樹脂絶縁層に圧着し、銅箔からなる放熱板をイ
ンターポーザ基板全面に形成する工程と、放熱板をエッ
チングして、伝熱パッドの直上位置に伝熱パッドより小
さい窓を開口する工程と、窓を開口した放熱板をマスク
にして樹脂絶縁層をエッチングし、樹脂絶縁層を貫通し
て伝熱パッドを露出させる孔を開口する工程と、孔に導
電ペーストを充填してなる伝熱体、又は孔にめっき加工
を施して、孔の孔壁に沿った金属めっき層からなる筒状
の伝熱体を形成する工程とを備えることを特徴としてい
る。本発明方法を適用することにより、本発明に係るＣ
ＳＰを少ないプロセス工程数で経済的に作製することが
できる。[0012] The method of manufacturing a CSP according to the present invention comprises a bare I
A method of manufacturing a chip size package (CSP) in which a C chip is packaged, comprising: forming a chip pad on which a bare IC chip is mounted on a surface of an interposer substrate; and forming a metal heat transfer pad on the surface of the interposer substrate. Forming process and chip / interposer substrate chip
A step of fixing a bare IC chip on the pad, a step of forming a resin insulating layer on the bare IC chip side of the interposer substrate and sealing the bare IC chip with a resin, and a step of forming a copper foil with a resin layer (RCC (resin coating)・ Copper)) The resin layer is pressed against the resin insulation layer, and a heat radiating plate made of copper foil is formed on the entire interposer substrate. A step of opening a window, a step of etching a resin insulating layer using a heat sink having the window opened as a mask, a step of opening a hole that penetrates the resin insulating layer and exposes a heat transfer pad, and filling the hole with a conductive paste Forming a tubular heat transfer body made of a metal plating layer along the hole wall of the hole by plating the heat transfer body or the hole. By applying the method of the present invention, C
SP can be economically produced with a small number of process steps.

【００１３】ワイヤーボンディング接続方式のベアＩＣ
チップの場合には、本発明に係るＣＳＰの作製方法は、
伝熱パッドを形成する工程では、インターポーザ基板の
表面に伝熱パッドから離隔して基板中継電極を形成し、
かつベアＩＣチップを樹脂封止する工程の前に、基板中
継電極とベアＩＣチップの電極とをワイヤーボンディン
グする工程を備えている。好適には、チップ・パッドを
形成する工程では、ソルダーレジスト層を被着させたイ
ンターポーザ基板のソルダーレジスト層をパターニング
して、チップ・パッド、及び基板中継電極と伝熱パッド
とを隔てる電極間絶縁部を形成する。また、基板中継電
極及び伝熱パッドを形成する工程では、基板中継電極と
接続する裏面電極をインターポーザ基板の裏面に形成す
る。Bare IC of wire bonding connection system
In the case of a chip, the method for manufacturing a CSP according to the present invention is as follows.
In the step of forming the heat transfer pad, a substrate relay electrode is formed on the surface of the interposer substrate at a distance from the heat transfer pad,
In addition, before the step of resin-sealing the bare IC chip, a step of wire-bonding the substrate relay electrode and the electrode of the bare IC chip is provided. Preferably, in the step of forming a chip pad, the solder resist layer of the interposer substrate on which the solder resist layer is applied is patterned to form a chip pad, and an electrode-to-electrode insulating layer separating the substrate relay electrode and the heat transfer pad. Form a part. In the step of forming the substrate relay electrode and the heat transfer pad, a back surface electrode connected to the substrate relay electrode is formed on the back surface of the interposer substrate.

【００１４】[0014]

【発明の実施の形態】以下に、添付図面を参照して、本
発明の実施の形態例について具体的かつ詳細に説明す
る。 ＣＳＰの実施の形態例１ 図１は本実施の形態の一例であるＣＳＰの構成を示す断
面図である。本実施形態例のＣＳＰ１０は、図１に示す
ように、インターポーザ基板１２と、インターポーザ基
板１２に設けられた、膜厚４０±５μｍのソルダーレジ
スト層からなるチップ・パッド１４上に接着剤層１５に
よって固着されたベアＩＣチップ１６と、ベアＩＣチッ
プ１６を樹脂封止するために成膜されている樹脂絶縁層
１８と、樹脂絶縁層１８上に全面にエポキシ系樹脂層２
０を介して接着されている放熱板２２とを備えている。
また、ＣＳＰ１０は、チップ・パッド１４とは反対側の
インターポーザ基板１２の裏面に、ＣＳＰ１０をマザー
基板（図示せず）に実装する際に電極となるはんだボー
ル２８付き裏面電極２６が、所定数（図１では、簡単に
４個のみ図示）、相互に離隔して、裏面パッド絶縁部２
４とチップ間絶縁部２５との間に設けてある。裏面電極
２６は、直径０．３mmから０．５mmの大きさである。Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. First Embodiment of CSP FIG. 1 is a cross-sectional view showing a configuration of a CSP as an example of the present embodiment. As shown in FIG. 1, the CSP 10 of the present embodiment is provided with an adhesive layer 15 on an interposer substrate 12 and a chip pad 14 formed on the interposer substrate 12 and formed of a solder resist layer having a thickness of 40 ± 5 μm. The fixed bare IC chip 16, a resin insulating layer 18 formed to seal the bare IC chip 16 with resin, and an epoxy resin layer 2 on the entire surface of the resin insulating layer 18.
And a heat radiating plate 22 adhered to the radiating plate 22 via the radiating plate.
The CSP 10 has a predetermined number of back electrodes 26 with solder balls 28 that serve as electrodes when the CSP 10 is mounted on a mother board (not shown) on the back surface of the interposer substrate 12 opposite to the chip pads 14. In FIG. 1, only four are simply shown), and are separated from each other,
4 and the inter-chip insulating portion 25. The back electrode 26 has a size of 0.3 mm to 0.5 mm in diameter.

【００１５】インターポーザ基板１２は、厚さ０．４mm
から１．０mmの絶縁性基板であって、その表面上には、
基板中継電極３２が、ベアＩＣチップ１６の両側に設け
られ、線径２０μｍから４０μｍの金線２９によってベ
アＩＣチップ１６の電極３０とワイヤーボンディングさ
れている。また、基板中継電極３２の外側に、電極間絶
縁部３４を介在させて、直径０．２mmから０．５mmの伝
熱パッド３６が設けられている。また、伝熱パッド３６
の外側にはチップ間絶縁部３５が設けてある。伝熱パッ
ド３６は、それぞれ、樹脂絶縁層１８及びエポキシ系樹
脂層２０を貫通する径０．１mmから０．４mmの伝熱体３
８によって放熱板２２に熱的に接続されている。The interposer substrate 12 has a thickness of 0.4 mm
From 1.0mm insulating substrate, on the surface of which
Substrate relay electrodes 32 are provided on both sides of the bare IC chip 16 and are wire-bonded to the electrodes 30 of the bare IC chip 16 by gold wires 29 having a wire diameter of 20 μm to 40 μm. A heat transfer pad 36 having a diameter of 0.2 mm to 0.5 mm is provided outside the substrate relay electrode 32 with an inter-electrode insulating portion 34 interposed therebetween. The heat transfer pad 36
Is provided outside the chip. The heat transfer pad 36 is a heat transfer body 3 having a diameter of 0.1 mm to 0.4 mm penetrating through the resin insulating layer 18 and the epoxy resin layer 20, respectively.
8 is thermally connected to the heat sink 22.

【００１６】本実施の形態例のＣＳＰ１０では、ベアＩ
Ｃチップ１６は、接着剤層１５によってチップ・パッド
１４上に接着されている。樹脂絶縁層１８は、ベアＩＣ
チップ１６を樹脂封止するために、ベアＩＣチップ１６
上に１００μｍから３００μｍの厚さで成膜された樹脂
封止用の樹脂で形成されている。放熱板２２は、厚さ１
２μｍの銅箔で形成され、厚さ３０μｍから８０μｍの
エポキシ系樹脂層２０の樹脂と放熱板２２の銅箔とから
なる樹脂層付き銅箔（ＲＣＣ）を接着剤で樹脂絶縁層１
８上に全面に接着することにより形成されている。銅箔
の膜厚は、１８μｍでも、また３５μｍでも良い。In the CSP 10 of this embodiment, the bear I
The C chip 16 is adhered on the chip pad 14 by an adhesive layer 15. The resin insulation layer 18 is a bare IC
To seal the chip 16 with a resin, the bare IC chip 16
It is formed of a resin for resin encapsulation, having a thickness of 100 μm to 300 μm. The heat sink 22 has a thickness of 1
A copper foil with a resin layer (RCC) formed of a 2 μm copper foil and having a thickness of 30 μm to 80 μm and made of a resin of an epoxy resin layer 20 and a copper foil of a heat sink 22 is bonded to a resin insulation layer
8 is formed by adhering to the entire surface. The thickness of the copper foil may be 18 μm or 35 μm.

【００１７】裏面電極２６、基板中継電極３２、及び伝
熱パッド３６は、２０μｍから５０μｍの厚さの銅パタ
ーン３７ａと、銅パターン３７ａ上にニッケルめっき処
理、次いで金めっき処理を施してなる、厚さ４μｍから
５μｍのＮｉ層及び厚さ０．０３μｍから０．２μｍの
Ａｕ層の積層膜３７ｂとの積層金属膜として形成されて
いる。伝熱体３８は、樹脂絶縁層１８を貫通する孔に、
伝熱性のペースト、例えば一般的に使用する導電ペース
ト（熱硬化性樹脂に銀、銅等の金属粒子を分散させたも
の）を充填して、熱硬化させたものか、または、銅めっ
き加工を施してなる筒状銅めっき層の伝熱体である。基
板中継電極３２と裏面電極２６とは、インターポーザ基
板１２を貫通する導体（図示せず）によって電気的に接
続されている。The back electrode 26, the substrate relay electrode 32, and the heat transfer pad 36 are made of a copper pattern 37a having a thickness of 20 μm to 50 μm, and a nickel plating process, followed by a gold plating process on the copper pattern 37a. It is formed as a laminated metal film with a laminated film 37b of a Ni layer having a thickness of 4 μm to 5 μm and an Au layer having a thickness of 0.03 μm to 0.2 μm. The heat transfer body 38 is formed in a hole penetrating the resin insulation layer 18.
Filled with a heat conductive paste, for example, a commonly used conductive paste (a material in which metal particles such as silver and copper are dispersed in a thermosetting resin) and cured by heat, or a copper plating process It is a heat transfer body of a tubular copper plating layer formed. The substrate relay electrode 32 and the back surface electrode 26 are electrically connected by a conductor (not shown) penetrating the interposer substrate 12.

【００１８】本実施形態例のＣＳＰ１０では、ベアＩＣ
チップ１６で発生した熱は、伝熱パッド３６及び伝熱体
１８によって広い放熱板２２に伝熱され、放熱板２２か
ら外部に放熱される。また、放熱板２２は、ヒートシン
クとしても機能する。しかも、ベアＩＣチップ１６が銅
箔製の放熱板２２によって遮蔽されているので、外部ノ
イズの影響が軽減される。また、樹脂絶縁層１８は、低
内部応力の熱硬化性高純度エポキシ系インキ（モールド
樹脂）により形成されているので、インターポーザ基板
１２の反り等の変形を抑制し、ベアＩＣチップ１６とイ
ンターポーザ基板１２との間の接続信頼性を向上させて
いる。但し、裏面パッド絶縁部２４、裏面チップ間絶縁
部２５、電極間絶縁部３４、チップ間絶縁部３５、及び
エポキシ系樹脂層２０は、作製の際の便宜上から設けて
あるものであって、必ずしも設ける必要はない。また、
逆に、インターポーザ基板１２の裏面の裏面電極２６同
士の間に電極間絶縁部を設けてもよい。In the CSP 10 of this embodiment, a bare IC
The heat generated by the chip 16 is transferred to the wide radiator plate 22 by the heat transfer pad 36 and the heat transfer member 18, and is radiated to the outside from the radiator plate 22. Further, the heat sink 22 also functions as a heat sink. In addition, since the bare IC chip 16 is shielded by the heat radiating plate 22 made of copper foil, the influence of external noise is reduced. Further, since the resin insulating layer 18 is formed of a thermosetting high-purity epoxy-based ink (mold resin) having low internal stress, deformation such as warpage of the interposer substrate 12 is suppressed, and the bare IC chip 16 and the interposer substrate are prevented from deforming. 12 has improved connection reliability. However, the back surface pad insulating portion 24, the back surface inter-chip insulating portion 25, the inter-electrode insulating portion 34, the inter-chip insulating portion 35, and the epoxy-based resin layer 20 are provided for convenience in manufacturing, and are not necessarily provided. No need to provide. Also,
Conversely, an inter-electrode insulating portion may be provided between the back electrodes 26 on the back surface of the interposer substrate 12.

【００１９】ＣＳＰの実施の形態例２ 図２は本実施の形態の別の一例のＣＳＰの構成を示す断
面図である。本実施形の態例のＣＳＰ４０は、ベアＩＣ
チップ１６への入出力信号配線４２がチップ・パッド１
４内に延在することを除いて、実施の形態例１のＣＳＰ
１０の構成と同じ構成を備えている。本実施の形態例で
は、入出力信号配線４２をチップ・パッド１４内に設け
ているので、インターポーザ基板１２上の高密度実装化
が実施の形態例１に示した事例のＣＳＰ１０より更に高
くなる。Second Embodiment of CSP FIG. 2 is a sectional view showing the configuration of another CSP according to the present embodiment. The CSP 40 according to this embodiment is a bare IC.
I / O signal wiring 42 to chip 16 is chip pad 1
4 except that it extends into the CSP.
It has the same configuration as the configuration of No. 10. In the present embodiment, since the input / output signal wiring 42 is provided in the chip pad 14, the high-density mounting on the interposer substrate 12 is higher than the CSP 10 in the case shown in the first embodiment.

【００２０】ＣＳＰの作製方法の実施の形態例 本実施の形態例は、本発明のＣＳＰの作製方法を上述の
実施の形態例１のＣＳＰ１０の作製に適用した実施形態
の一例であって、図３（ａ）から（ｃ）、図４（ｄ）か
ら（ｆ）、及び図５（ｇ）から（ｉ）は、それぞれ、本
実施の形態例方法に従ってＣＳＰを作製する際の工程毎
の断面図である。先ず、図３（ａ）に示すように、両面
に厚さ４０±５μｍのソルダーレジスト層を被着させた
厚さ０．４mmから１．０mmのインターポーザ基板１２を
用意し、インターポーザ基板１２上のソルダーレジスト
層をパターニングして、ベアＩＣチップを搭載するチッ
プ・パッド１４、電極間絶縁部３４、及びチップ間絶縁
部３５をインターポーザ基板１２の表面に形成する。ま
た、チップ・パッド１４及びチップ間絶縁部３５と対向
するインターポーザ基板１２の裏面に裏面パッド絶縁部
２４及び裏面チップ間絶縁部２５を形成する。Embodiment of CSP Fabrication Method This embodiment is an example of an embodiment in which the CSP fabrication method of the present invention is applied to the fabrication of the CSP 10 of the first embodiment. 3 (a) to 3 (c), FIGS. 4 (d) to 4 (f), and FIGS. 5 (g) to 5 (i) are cross-sections for each step in manufacturing a CSP according to the method of the present embodiment. FIG. First, as shown in FIG. 3A, an interposer substrate 12 having a thickness of 0.4 mm to 1.0 mm and a solder resist layer having a thickness of 40 ± 5 μm deposited on both surfaces is prepared. By patterning the solder resist layer, the chip pad 14 on which the bare IC chip is mounted, the inter-electrode insulator 34, and the inter-chip insulator 35 are formed on the surface of the interposer substrate 12. Further, a back surface pad insulating portion 24 and a back surface inter-chip insulating portion 25 are formed on the back surface of the interposer substrate 12 facing the chip pad 14 and the inter-chip insulating portion 35.

【００２１】次いで、チップ・パッド１４と電極間絶縁
部３４との間、及び、電極間絶縁部３４とチップ間絶縁
部３５との間に、２０μｍから５０μｍの厚さの銅パタ
ーン３７ａを形成し、更に銅パターン３７ａ上にニッケ
ルめっき処理、次いで金めっき処理を施して、厚さ４μ
ｍから５μｍのＮｉめっき層と厚さ０．０３μｍから
０．２μｍのＡｕめっき層との積層膜３７ｂを成膜し
て、インターポーザ基板１２の表面に、所要寸法の基板
中継電極３２、及び直径０．２mmから０．５mmの伝熱パ
ッド３６を形成する。基板中継電極３２及び伝熱パッド
３６と同様にして、インターポーザ基板１２の裏面の裏
面パッド絶縁部２４と裏面チップ間絶縁部２５との間に
直径０．３mmから０．５mmの裏面電極２６を所要数（図
３（ａ）では、簡単に一つのベアＩＣチップ当たり４個
のみ図示）形成する。Next, a copper pattern 37a having a thickness of 20 μm to 50 μm is formed between the chip pad 14 and the inter-electrode insulator 34 and between the inter-electrode insulator 34 and the inter-chip insulator 35. Then, a nickel plating process and then a gold plating process are performed on the copper pattern 37a to have a thickness of 4 μm.
A laminated film 37b of a Ni plating layer having a thickness of 5 μm to 5 μm and an Au plating layer having a thickness of 0.03 μm to 0.2 μm is formed on the surface of the interposer substrate 12, the substrate relay electrode 32 having required dimensions, and a diameter of 0 mm. A heat transfer pad 36 of 2 mm to 0.5 mm is formed. A back electrode 26 having a diameter of 0.3 mm to 0.5 mm is required between the back pad insulating portion 24 on the back surface of the interposer substrate 12 and the back chip insulating portion 25 in the same manner as the substrate relay electrode 32 and the heat transfer pad 36. 3 (FIG. 3 (a) simply shows only four per bare IC chip).

【００２２】次いで、図３（ｂ）に示すように、インタ
ーポーザ基板１２のチップ・パッド１４上に熱硬化性接
着剤１５を塗布し、ベアＩＣチップ１６を配置して、１
００℃から１５０℃の温度で３０分から１時間加熱し
て、接着剤１５を硬化させ、ベアＩＣチップ１６をチッ
プ・パッド１４上に固着させる。Next, as shown in FIG. 3B, a thermosetting adhesive 15 is applied onto the chip pads 14 of the interposer substrate 12, and the bare IC chips 16 are arranged.
The adhesive 15 is cured by heating at a temperature of 00 ° C. to 150 ° C. for 30 minutes to 1 hour, and the bare IC chip 16 is fixed on the chip pad 14.

【００２３】次に、図３（ｃ）に示すように、インター
ポーザ基板１２上の基板中継電極３２とベアＩＣチップ
１６のアルミ電極３０とを線径２０〜４０φμｍの金線
２９（Ａｕワイヤー）でボンディングする。Next, as shown in FIG. 3C, the substrate relay electrode 32 on the interposer substrate 12 and the aluminum electrode 30 of the bare IC chip 16 are connected by a gold wire 29 (Au wire) having a wire diameter of 20 to 40 μm. Bonding.

【００２４】続いて、図４（ｄ）に示すように、ベアＩ
Ｃチップ１６上を含めてインターポーザ基板１２の表面
全面に、粘度３００poise から５００poise で、低内部
応力、高純度の熱硬化型エポキシ系インキ（モールド樹
脂）をステンレス鋼製スクリーンを使って印刷する。印
刷後、真空脱泡し、印刷したインキ内部の泡を除去す
る。真空印刷機で行っても同様の効果を得ることができ
る。次いで、１００℃から１２０℃の温度で１時間から
２時間加熱して仮硬化させ、続いて温度１５０℃で３０
分から１時間加熱して本硬化させることにより、硬化樹
脂層からなる樹脂絶縁層１８を形成する。硬化した後の
樹脂絶縁層１８の厚さは、ベアＩＣチップ１６の上面か
ら１００μｍから３００μｍである。Subsequently, as shown in FIG.
On the entire surface of the interposer substrate 12 including the surface of the C chip 16, a low-stress, high-purity thermosetting epoxy-based ink (mold resin) having a viscosity of 300 poise to 500 poise is printed using a stainless steel screen. After printing, vacuum defoaming is performed to remove bubbles inside the printed ink. The same effect can be obtained by performing the operation with a vacuum printer. Next, the mixture is temporarily cured by heating at a temperature of 100 ° C. to 120 ° C. for 1 hour to 2 hours.
The resin insulating layer 18 made of a cured resin layer is formed by performing main curing by heating for a minute to one hour. The thickness of the cured resin insulating layer 18 is 100 μm to 300 μm from the upper surface of the bare IC chip 16.

【００２５】次に、樹脂絶縁層１８上に厚さ１２μｍの
銅箔に厚さ３０μｍから８０μｍの半硬化のエポキシ系
樹脂を成形した樹脂層付き銅箔（ＲＣＣ（レジン・コー
ティング・カッパー））を真空プレス成形によって、圧
着し、図４（ｅ）に示すように、エポキシ系樹脂層２０
と放熱板２２を形成する。銅箔の厚さは、１８μｍで
も、３５μｍでも良い。また、樹脂は、ポリイミド樹
脂、又はその他の熱硬化性有機樹脂でも良い。樹脂層付
き銅箔は、松下電工（株）、住友ベークライト（株）、
日立化成（株）等で製造、販売されている。真空プレス
成形の条件は、例えば２０ｋｇ／ｃｍ2から４０ｋｇ／
ｃｍ2のプレス圧力で樹脂層付き銅箔を樹脂絶縁層１８
に押圧しつつ、真空度７４０〜７５０ｍｍＨｇの下で、
１７０℃から１８０℃の温度で１時間加熱する。Next, on the resin insulating layer 18, a copper foil with a resin layer (RCC (Resin Coating Copper)) in which a 30 μm to 80 μm thick semi-cured epoxy resin is molded on a 12 μm thick copper foil. It is pressure-bonded by vacuum press molding, and as shown in FIG.
And a radiator plate 22 are formed. The thickness of the copper foil may be 18 μm or 35 μm. Further, the resin may be a polyimide resin or another thermosetting organic resin. Copper foil with resin layer is available from Matsushita Electric Works, Sumitomo Bakelite,
Manufactured and sold by Hitachi Chemical Co., Ltd. and others. The conditions for vacuum press molding are, for example, from 20 kg / cm 2 to 40 kg / cm 2.
A copper foil with a resin layer is applied to the resin insulation layer 18 with a pressing pressure of 2 cm 2.
While pressing under a vacuum of 740 to 750 mmHg,
Heat at 170 ° C to 180 ° C for 1 hour.

【００２６】放熱板２２を塩化第２鉄又は塩化第２銅水
溶液でエッチングして、図４（ｆ）に示すように、伝熱
パッド３６の直上位置で、放熱板２２に直径０．１mmか
ら０．４mmの窓４４を開口する。The heat radiating plate 22 is etched with an aqueous solution of ferric chloride or cupric chloride, and as shown in FIG. A 0.4 mm window 44 is opened.

【００２７】窓４４を開口した放熱板２２をマスクに
し、ＣＯ2ガスレーザ光又はＵＶレーザ光を照射して、
エポキシ系樹脂層２０及び樹脂絶縁層１８をエッチング
して、図５（ｇ）に示すように、エポキシ系樹脂層２０
及び樹脂絶縁層１８を貫通して伝熱パッド３６を露出さ
せる孔４６を開口する。放熱板２２の窓４４の孔径は、
孔４６の孔径より１０μｍから３０μｍ大きい方が良好
な形状で孔４６を明けることができる。尚、レーザ光に
よる孔明け後、伝熱パッド３６上に大きさ２μｍ以下の
樹脂薄膜およびカスが残る場合は、温度８０℃から９０
℃の過マンガン酸水溶液で洗浄して除去する。Using the radiator plate 22 having the window 44 opened as a mask, a CO 2 gas laser beam or a UV laser beam is irradiated,
The epoxy-based resin layer 20 and the resin insulation layer 18 are etched, and as shown in FIG.
Then, a hole 46 that penetrates through the resin insulating layer 18 and exposes the heat transfer pad 36 is opened. The hole diameter of the window 44 of the heat sink 22 is
It is possible to form the hole 46 with a good shape when the hole diameter is larger by 10 μm to 30 μm than the hole diameter. When a resin thin film and a residue having a size of 2 μm or less remain on the heat transfer pad 36 after the laser beam is formed, the temperature is reduced from 80 ° C. to 90 ° C.
It is removed by washing with an aqueous solution of permanganic acid at ° C.

【００２８】熱硬化性樹脂に銀、銅、その他の金属粒子
を分散させた導電ペーストを孔４６に充填し、温度１５
０℃から１７０℃で２０分から４０分加熱して硬化さ
せ、図５（ｈ）に示すように、熱の伝熱経路を構成し、
伝熱パッド３６と放熱板２２とを熱的に接続する伝熱体
３８を形成する。導電ペーストに代えて、化学めっきと
電気めっきと行う銅めっき処理を孔４６に施し、孔４６
の孔壁に沿って１５μｍから２０μｍの厚さの円筒状伝
熱体を形成しても良い。導電ペーストの充填は、スクリ
ーン印刷法による転写、又はディスペンサ、シリンジ針
等による注入により行う。硬化後、ブラシ研磨又はバフ
研磨で伝熱体３８の上面を平滑にする。A hole 46 is filled with a conductive paste in which silver, copper, and other metal particles are dispersed in a thermosetting resin.
It is cured by heating at 0 to 170 ° C. for 20 to 40 minutes, and as shown in FIG.
A heat transfer body for thermally connecting the heat transfer pad and the heat radiating plate 22 is formed. In place of the conductive paste, a copper plating process for performing chemical plating and electroplating is performed on the hole 46.
A cylindrical heat transfer body having a thickness of 15 μm to 20 μm may be formed along the hole wall. The filling of the conductive paste is performed by transfer using a screen printing method or injection using a dispenser, a syringe needle, or the like. After curing, the upper surface of the heat transfer body 38 is smoothed by brush polishing or buff polishing.

【００２９】次に、塩化第２鉄又は塩化第２銅水溶液で
放熱板２２をエッチングし、各ベアＩＣチップ１６毎に
切断する際のガイドとなる、幅０．１mmから１．０mmの
ガイド溝４８を、図５（ｉ）に示すように、チップ間絶
縁部３５の直上の位置に形成する。続いて、形成した積
層構造体をガイド溝４８に沿ってダイサーで切断するこ
とにより、図１に示す所定の大きさのＣＳＰ１０を作製
することができる。必要に応じて、図１に示すように、
ＣＳＰ１０をマザー基板（図示せず）に接続する裏面電
極２６にはんだボール２８を固着し、ＢＧＡ（ボールグ
リッドアレイ）１０としても良い。Next, a guide groove having a width of 0.1 mm to 1.0 mm serving as a guide when the heat radiating plate 22 is etched with an aqueous ferric chloride or cupric chloride solution and cut for each bare IC chip 16. As shown in FIG. 5 (i), 48 is formed immediately above the inter-chip insulating portion 35. Subsequently, the formed laminated structure is cut along a guide groove 48 with a dicer, whereby the CSP 10 having a predetermined size shown in FIG. 1 can be manufactured. If necessary, as shown in FIG.
A BGA (ball grid array) 10 may be formed by fixing a solder ball 28 to a back electrode 26 connecting the CSP 10 to a mother substrate (not shown).

【００３０】本実施の形態例では、インターポーザ基板
１２上に３個のチップ・パッド１４を設ける例を挙げて
説明しているが、チップ・パッド１４の数は任意であっ
て、また、横方向に加えて縦方向にチップ・パッド１４
をアレイ状又は格子状に配置したものでも良い。In this embodiment, an example in which three chip pads 14 are provided on the interposer substrate 12 has been described. However, the number of chip pads 14 is arbitrary, and the number of chip pads 14 is not limited. In addition to the vertical chip pads 14
May be arranged in an array or a lattice.

【００３１】[0031]

【発明の効果】本発明によれば、インターポーザ基板上
にベアＩＣチップ及び伝熱パッドを搭載し、その上に樹
脂絶縁層及び金属製放熱板を設け、かつ樹脂絶縁層を貫
通し、下端で伝熱パッドに、上端で放熱板に接触して、
伝熱パッドから放熱板に熱を伝熱する伝熱体を備える。
即ち、本発明では、放熱板をＣＳＰの上面全面に備えて
いるので、放熱性に優れ、しかも放熱板によってノイズ
を遮蔽するので、外部ノイズの影響を軽減することがで
きると共にインターポーザ基板の高密度実装化を図るこ
とができる。樹脂絶縁層として、ワイヤーボンディング
ＣＳＰ用の封止樹脂として一般に使用される低内部応
力、高純度エポキシ系熱硬化性モールド樹脂を使用する
ため、品質信頼性の高いＣＳＰを作製することができ
る。本発明方法は、高放熱性及びノイズ遮蔽性に優れ、
高品質で、しかも高密度実装に適したＣＳＰをシンプル
な作製プロセスによって経済的に作製できる方法を実現
している。According to the present invention, a bare IC chip and a heat transfer pad are mounted on an interposer substrate, a resin insulating layer and a metal radiating plate are provided thereon, and the resin insulating layer is penetrated. Contact the heat transfer pad with the heat sink at the upper end,
A heat transfer body that transfers heat from the heat transfer pad to the heat sink is provided.
That is, according to the present invention, since the heat sink is provided on the entire upper surface of the CSP, the heat dissipation is excellent, and the noise is shielded by the heat sink, so that the influence of external noise can be reduced and the high density of the interposer substrate can be achieved. Implementation can be achieved. As the resin insulating layer, a low-internal-stress, high-purity epoxy-based thermosetting mold resin generally used as a sealing resin for a wire bonding CSP is used, so that a CSP with high quality reliability can be manufactured. The method of the present invention is excellent in high heat dissipation and noise shielding,
A method of economically producing a CSP suitable for high-density mounting with high quality has been realized by a simple production process.

【図面の簡単な説明】[Brief description of the drawings]

【図１】実施の形態例１のＣＳＰの構成を示す断面図で
ある。FIG. 1 is a cross-sectional view illustrating a configuration of a CSP according to a first embodiment.

【図２】実施の形態例２のＣＳＰの構成を示す断面図で
ある。FIG. 2 is a cross-sectional view illustrating a configuration of a CSP according to a second embodiment.

【図３】図３（ａ）から（ｃ）は、それぞれ、実施の形
態例方法に従ってＣＳＰを作製する際の工程毎の断面図
である。3 (a) to 3 (c) are cross-sectional views for respective steps when manufacturing a CSP according to the method of the embodiment.

【図４】図４（ｄ）から（ｆ）は、それぞれ、図３
（ｃ）に続いて、実施の形態例方法に従ってＣＳＰを作
製する際の工程毎の断面図である。FIGS. 4 (d) to 4 (f) correspond to FIGS.
It is sectional drawing for every process at the time of manufacturing a CSP according to the method of an embodiment, following (c).

【図５】図５（ｇ）から（ｉ）は、それぞれ、図４
（ｆ）に続いて、実施の形態例方法に従ってＣＳＰを作
製する際の工程毎の断面図である。FIGS. 5 (g) to 5 (i) correspond to FIGS.
It is sectional drawing for every process at the time of manufacturing a CSP according to the method of an embodiment, following (f).

【図６】従来のＣＳＰの構成を示す断面図である。FIG. 6 is a cross-sectional view showing a configuration of a conventional CSP.

【符号の説明】[Explanation of symbols]

１０……実施の形態例１のＣＳＰ、１２……インターポ
ーザ基板、１４……チップ・パッド、１５……接着剤
層、１６……ベアＩＣチップ、１８……樹脂絶縁層、２
０……エポキシ系樹脂層、２２……放熱板、２４……裏
面パッド絶縁部、２５……チップ間絶縁部、２６……裏
面電極、２８……はんだボール、２９……金線、３０…
…ベアＩＣチップの電極、３２……基板中継電極、３４
……電極間絶縁部、３５……チップ間絶縁部、３６……
伝熱パッド、３７ａ……銅パターン、３７ｂ……Ｎｉ層
及びＡｕ層の積層膜、３８……伝熱体、４０……実施の
形態例２のＣＳＰ、４２……入出力信号配線、４４……
窓、４６……孔、４８……ガイド溝、５０……従来のＣ
ＳＰ、５２……インターポーザ基板、５４……チップ・
パッド、５６……ベアＩＣチップ、５８……樹脂絶縁
層、６０……はんだボール、６２……裏面電極、６４…
…放熱板、６６……伝熱体、６８……金線、７０……ベ
アＩＣチップの電極、７２……基板中継電極、７４……
配線パターン。10 CSP of Embodiment 1, 12 interposer substrate, 14 chip pad, 15 adhesive layer, 16 bare IC chip, 18 resin insulating layer, 2
0 ... epoxy resin layer, 22 ... heat sink, 24 ... back pad insulating part, 25 ... inter-chip insulating part, 26 ... back electrode, 28 ... solder ball, 29 ... gold wire, 30 ...
… Bare IC chip electrode, 32… board relay electrode, 34
…… Insulation part between electrodes, 35 …… Insulation part between chips, 36 ……
Heat transfer pad, 37a ... copper pattern, 37b ... laminated film of Ni layer and Au layer, 38 ... heat transfer body, 40 ... CSP of the second embodiment, 42 ... input / output signal wiring, 44 ... …
Window, 46: Hole, 48: Guide groove, 50: Conventional C
SP, 52 ... interposer substrate, 54 ... chip
Pad, 56: Bare IC chip, 58: Resin insulating layer, 60: Solder ball, 62: Back electrode, 64:
... heat sink, 66 ... heat conductor, 68 ... gold wire, 70 ... electrode of bare IC chip, 72 ... board relay electrode, 74 ...
Wiring pattern.

Claims (9)

【特許請求の範囲】[Claims] 【請求項１】 インターポーザ基板上に搭載されたベア
ＩＣチップ及びインターポーザ基板上に設けられた金属
製伝熱パッドと、 インターポーザ基板上に形成され、ベアＩＣチップ及び
金属製伝熱パッドを樹脂封止する樹脂絶縁層と、 樹脂絶縁層上に設けられた金属製放熱板と、 樹脂絶縁層を貫通し、下端で伝熱パッドに、上端で放熱
板に、それぞれ接触して、伝熱パッドから放熱板に熱を
伝熱する伝熱体とを備えていることを特徴とするチップ
サイズ・パッケージ。1. A bare IC chip mounted on an interposer substrate and a metal heat transfer pad provided on the interposer substrate; and a bare IC chip formed on the interposer substrate and a metal heat transfer pad sealed with a resin. The resin insulation layer, the metal heat sink provided on the resin insulation layer, and the resin insulation layer penetrate and contact the heat transfer pad at the lower end and the heat sink at the upper end to release heat from the heat transfer pad. A chip size package comprising a plate and a heat transfer body for transferring heat. 【請求項２】 前記樹脂絶縁層が、低内部応力のエポキ
シ系熱硬化性樹脂で形成されていることを特徴とする請
求項１に記載のチップサイズ・パッケージ（ＣＳＰ）。2. The chip size package (CSP) according to claim 1, wherein the resin insulating layer is formed of a low internal stress epoxy-based thermosetting resin. 【請求項３】 前記ベアＩＣチップが、前記インターポ
ーザ基板に形成されたソルダーレジストからなる絶縁性
チップ・パッド上に搭載され、かつ、ベアＩＣチップへ
の入出力配線がチップ・パッド内に延在することを特徴
とする請求項１に記載のチップサイズ・パッケージ。3. The bare IC chip is mounted on an insulating chip pad made of a solder resist formed on the interposer substrate, and input / output wiring to the bare IC chip extends into the chip pad. The chip size package according to claim 1, wherein 【請求項４】 前記放熱板が、樹脂付き銅箔（レジン・
コーティング・カッパー（ＲＣＣ））の樹脂側を前記樹
脂絶縁層に接着させてなる銅箔で形成されていることを
特徴とする請求項１に記載のチップサイズ・パッケー
ジ。4. The heat radiation plate is made of a resin-coated copper foil (a resin
The chip size package according to claim 1, wherein the resin side of the coating copper (RCC) is formed of a copper foil adhered to the resin insulating layer. 【請求項５】 前記伝熱体は、前記樹脂絶縁層を貫通す
る孔に導電性ペーストを充填してなる充填体として形成
されているか、又は樹脂絶縁層を貫通する孔の孔壁に沿
って設けられた金属めっき層として形成されていること
を特徴とする請求項１に記載のチップサイズ・パッケー
ジ。5. The heat transfer body is formed as a filling body in which a hole penetrating the resin insulating layer is filled with a conductive paste, or along a hole wall of the hole penetrating the resin insulating layer. The chip size package according to claim 1, wherein the chip size package is formed as a provided metal plating layer. 【請求項６】 ベアＩＣチップをパッケージしたチップ
サイズ・パッケージ（ＣＳＰ）の作製方法であって、 ベアＩＣチップを搭載するチップ・パッドをインターポ
ーザ基板の表面に形成する工程と、 インターポーザ基板の表面に金属製伝熱パッドを形成す
る工程と、 インターポーザ基板のチップ・パッド上にベアＩＣチッ
プを固着させる工程と、 インターポーザ基板のベアＩＣチップ側に樹脂絶縁層を
形成して、ベアＩＣチップを樹脂封止する工程と、 樹脂層付き銅箔（ＲＣＣ（レジン・コーティング・カッ
パー））の樹脂層を樹脂絶縁層に圧着し、銅箔からなる
放熱板をインターポーザ基板全面に形成する工程と、 放熱板をエッチングして、伝熱パッドの直上位置に伝熱
パッドより小さい窓を開口する工程と、 窓を開口した放熱板をマスクにして樹脂絶縁層をエッチ
ングし、樹脂絶縁層を貫通して伝熱パッドを露出させる
孔を開口する工程と、 孔に導電ペーストを充填してなる伝熱体、又は孔にめっ
き加工を施して、孔の孔壁に沿った金属めっき層からな
る筒状の伝熱体を形成する工程とを備えることを特徴と
するチップサイズ・パッケージの作製方法。6. A method of manufacturing a chip size package (CSP) in which a bare IC chip is packaged, comprising: forming a chip pad on which a bare IC chip is mounted on a surface of an interposer substrate; Forming a metal heat transfer pad, fixing a bare IC chip on the chip pad of the interposer substrate, forming a resin insulating layer on the bare IC chip side of the interposer substrate, and sealing the bare IC chip with a resin A step of stopping, a step of pressing a resin layer of a copper foil with a resin layer (RCC (Resin Coating Copper)) on a resin insulating layer, and forming a heat sink made of copper foil on the entire interposer substrate; Etching and opening a window smaller than the heat transfer pad directly above the heat transfer pad; A step of opening a hole for exposing the heat transfer pad through the resin insulation layer by etching the resin insulation layer as a mask, and performing a plating process on the heat transfer body or the hole formed by filling the hole with a conductive paste. Forming a cylindrical heat conductor formed of a metal plating layer along the hole wall of the hole. 【請求項７】 伝熱パッドを形成する工程では、インタ
ーポーザ基板の表面に伝熱パッドから離隔して基板中継
電極を形成し、 ベアＩＣチップを樹脂封止する工程の前に、基板中継電
極とベアＩＣチップの電極とをワイヤーボンディングす
る工程を備えていることを特徴とする請求項６に記載の
チップサイズ・パッケージ（ＣＳＰ）の作製方法。7. A step of forming a heat transfer pad, forming a board relay electrode on the surface of the interposer substrate at a distance from the heat transfer pad, and forming the board relay electrode before the step of resin-sealing the bare IC chip. 7. The method of manufacturing a chip-size package (CSP) according to claim 6, further comprising a step of wire-bonding the electrodes of the bare IC chip. 【請求項８】 チップ・パッドを形成する工程では、ソ
ルダーレジスト層を被着させたインターポーザ基板のソ
ルダーレジスト層をパターニングして、チップ・パッ
ド、及び基板中継電極と伝熱パッドとを隔てる電極間絶
縁部を形成することを特徴とする請求項７に記載のチッ
プサイズ・パッケージの作製方法。8. The step of forming a chip pad includes patterning the solder resist layer of the interposer substrate on which the solder resist layer is applied, and forming a chip pad and an electrode between the substrate relay electrode and the heat transfer pad. 8. The method according to claim 7, wherein an insulating portion is formed. 【請求項９】 基板中継電極及び伝熱パッドを形成する
工程では、基板中継電極と接続する裏面電極をインター
ポーザ基板の裏面に形成することを特徴とする請求項７
に記載のチップサイズ・パッケージの作製方法。9. The step of forming a substrate relay electrode and a heat transfer pad, wherein a back electrode connected to the substrate relay electrode is formed on a back surface of the interposer substrate.
3. The method for manufacturing a chip size package described in 1.
JP11116509A 1999-04-23 1999-04-23 Chip size package(csp) and manufacture thereof Pending JP2000307038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11116509A JP2000307038A (en) 1999-04-23 1999-04-23 Chip size package(csp) and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11116509A JP2000307038A (en) 1999-04-23 1999-04-23 Chip size package(csp) and manufacture thereof

Publications (1)

Publication Number Publication Date
JP2000307038A true JP2000307038A (en) 2000-11-02

Family

ID=14688914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11116509A Pending JP2000307038A (en) 1999-04-23 1999-04-23 Chip size package(csp) and manufacture thereof

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Country Link
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165498A (en) * 2004-11-10 2006-06-22 Fuji Electric Holdings Co Ltd Semiconductor device and manufacturing method thereof
CN103441106A (en) * 2013-08-28 2013-12-11 江苏长电科技股份有限公司 Chip flip-mounting BGA encapsulating structure
CN107369662A (en) * 2017-06-19 2017-11-21 北京嘉楠捷思信息技术有限公司 Heat radiator

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006165498A (en) * 2004-11-10 2006-06-22 Fuji Electric Holdings Co Ltd Semiconductor device and manufacturing method thereof
CN103441106A (en) * 2013-08-28 2013-12-11 江苏长电科技股份有限公司 Chip flip-mounting BGA encapsulating structure
CN107369662A (en) * 2017-06-19 2017-11-21 北京嘉楠捷思信息技术有限公司 Heat radiator
CN107369662B (en) * 2017-06-19 2020-11-24 北京嘉楠捷思信息技术有限公司 Heat radiator

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