JP2000306923A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device suitable for driving an electric capacitor microphone by making at one end high in resistance, for the parasitic capacitance caused by an extended electrode requiring a large area. SOLUTION: A semiconductor substrate 21 whose specific resistance is 100-5,000 Ω.cm is prepared. An epitaxial layer 23 is formed on the substrate 21, and an island region 25 is formed. An NPN transistor and a junction field- effect transistor are formed in the region 25. An extended electrode 43 is formed to be continuous to the gate electrode of the junction field-effect transistor. The specific resistance of a portion of the substrate 21 under the electrode 43 is made high. A P-type diffusion region 44 is formed on a surface of the substrate 21, which is under each circuit element so that the region 44 will play the role of junction isolation. Since capacitors C1 and C2 reach the high specific resistance portion of the substrate 21, a substantially isolated state is achieved, which can hence prevent the flowing of a current from the electrode 43 to a ground potential GND.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device suitable for driving an electric condenser microphone.

[0002]

2. Description of the Related Art A condenser microphone (ECM) is
It is an element for converting air vibration such as voice into an electric signal of change in capacitance value. The output signal is extremely weak, and an element for amplifying the output signal is required to have characteristics such as high input impedance, high gain, and low noise.

[0003] As an element suitable for such a demand, a junction type F
Examples include an ET element (J-FET) and a MOS type FET element. Among them, the J-FET element has features such as easy integration into a BIP type IC. (For example,
JP-A-58-197885).

FIG. 8 shows this type of J-FET (P-channel type) device. First, an N-type epitaxial layer 2 is laminated on a P-type semiconductor substrate 1, and an N + -type buried layer 3 is formed therebetween. A P + type isolation region 4 is formed to penetrate the semiconductor substrate 1 from the surface of the epitaxial layer 2 so as to surround the buried layer 3, thereby forming an island region 5.

[0005] An N + type top gate region 6 is formed on the surface of the island region 5, and a P type channel region 7 is formed below the top gate region 6. A P-type source region 8 and a P-type drain region 9 are formed at both ends of the channel region, and a high-concentration gate contact region 10 is formed outside.

Further, the source electrode 11 is interposed via an insulating film.
S, a drain electrode 11D, and a gate electrode 11G are formed to constitute a P-channel J-FET.

Since a PN junction is formed in the gate region, the PN junction is reverse-biased, and the drain current is controlled by the size of the depletion layer.

When integrated, the other island region 5 has a P-type base region 12 and an N + -type emitter region 13.
And an N + type collector contact region 14. Elements such as NPN transistors form an integrated network that processes the signals received by the J-FET.

[0009]

However, when such an element is used for signal amplification of an electric microphone capacitor, it is necessary to provide an extended electrode 15 having a much larger area than an electrode pad on a semiconductor integrated circuit. May be done.

In such a case, the capacitance C1 formed by the extension electrode 15 and the epitaxial layer 2 with the insulating film 16 interposed therebetween,
And PN formed by epitaxial layer 2 and substrate 1
Junction capacitances C2 are generated parasitically, and these are connected to the substrate-biased ground potential GND. These capacitance values reach several tens of pF, which are values that cannot be ignored.

FIG. 9 shows a circuit diagram including the capacitors C1 and C2. One end of the electric condenser microphone ECM is connected to the gate (input terminal) of the J-FET 17 and
The source of the FET 17 is grounded, and the drain is the output terminal O.
Connected to UT. The output terminal OUT is connected to an integrated circuit network including NPN transistors and the like formed on the same substrate. The capacitors C1 and C2 are connected in series between the gate of the J-FET 17 and the ground potential GND. Then, the electric condenser microphone ECM
Is output to the ground potential GND via the capacitors C1 and C2 (current i shown in the figure), and the signal level applied to the gate of the J-FET 17 is reduced, so that a desirable output voltage cannot be obtained. was there.

[0012]

SUMMARY OF THE INVENTION The present invention has been made in view of the aforementioned problems, and has a semiconductor substrate of one conductivity type, a semiconductor layer of the opposite conductivity type formed on the substrate, and the semiconductor layer. An island region, an input transistor formed in the island region, an insulating film covering a surface of the semiconductor layer, and an extended electrode connected to an input terminal of the input transistor and extending over the insulating film. The specific resistance of the semiconductor substrate below the extension electrode is partially set high, thereby preventing a signal from flowing from the extension electrode to the ground potential GND. .

[0013]

Embodiments of the present invention will be described below in detail.

FIG. 1 is a sectional view showing a semiconductor device of the present invention. An N-channel element is formed as a field-effect transistor J-FET, and further integrated with the NPN transistor on the same substrate.

In FIG. 1, reference numeral 21 denotes a single crystal silicon semiconductor substrate. The specific resistance of a substrate used for a general bipolar integrated circuit is about 2 to 4 Ω · cm,
Semiconductor substrate 2 of the present application.
For 1, a material having a high specific resistance of 100 to 5000 Ω · cm is used.

An N + buried layer 22 is formed on the surface of a semiconductor substrate 21, and a plurality of island regions 25 are formed by bonding and separating an N-type epitaxial layer 23 formed thereon on a P + isolation region 24. In one of the island regions 25, a P + buried layer 26 is provided so as to overlap the N + buried layer 22.
The buried layer 26 is connected to a P-well region 27 formed by diffusion from the surface of the island region 25. P well region 2
An N-type channel region 28 and a P + -type top gate region 29 are provided on the surface 7, and the N-type channel region 28 constituting a channel is buried below the surface of the epitaxial layer 23. P well region 27 becomes a back gate.

Channel region 28 and top gate region 29
P + type gate contact region 30 is formed so as to cover the low-concentration diffusion surface of well region 27 so as to overlap with the end portion of the well region 27. Further, an N + type source region 31 and a drain region 32 are formed so as to penetrate the channel region 28. This transistor forms a depletion layer in the channel region 28 according to the potential applied to the gate, and controls the channel current between the source and the drain. Reference numeral 33 denotes a source electrode, reference numeral 34 denotes a drain electrode, and reference numeral 35 denotes the same.
Is a gate electrode.

In the other island region 25, a P-type base region 36 is formed on the surface, and an N + emitter region 37 is formed on the surface of the base region 36, thereby forming an NPN transistor using the island region 25 as a collector. Reference numeral 38 denotes an N + collector contact region. Reference numeral 39 denotes an emitter electrode,
Reference numeral 40 is a base electrode, and reference numeral 41 is a collector electrode.

These electrode groups make ohmic contact with the surface of each corresponding diffusion region, and the epitaxial layer 2
The circuit extends over the silicon oxide film 42 covering the three surfaces and connects each circuit element to form an integrated circuit network. Among them, the gate electrode 35 connected to the gate of the J-FET
Is expanded on the oxide film 42 to have a diameter of, for example, 1.0
It is continuous with the extended electrode 43 having a circular pattern of about 1.5 mm. The extension electrode 43 is connected to the electric condenser microphone.

Under the extension electrode 43, one of the island regions 25 surrounded by the P + isolation region 24 with the oxide film 42 interposed therebetween is located, and further below the extension region 43, the semiconductor substrate 21 having a high specific resistance is located. No N + buried layer 22 is provided. Also, there is no need to house circuit elements. A P-type diffusion region 44 is formed on the surface of the semiconductor substrate 21 except for the lower part of the extension electrode 43 so that a specific resistance lower than the specific resistance of the semiconductor substrate 21 is obtained. Thereby, the P + isolation region 24
Reach the P-type diffusion region 44 from the surface of the epitaxial layer 23.

The diffusion region 44 is formed to play the role of a conventional semiconductor substrate. The diffusion depth is 10 to 20 μm, and the peak impurity concentration is 1E.
About 16 atoms / cm-3, specific resistance ρ is 1 to 4Ω · c
The diffusion region has a profile of about m. By providing the diffusion region having such a high impurity concentration, a leak current between the island regions 25 is prevented. Further, the ground potential GND to be provided for junction separation with respect to the diffusion region 44 is configured to be supplied through the separation region 24 by an electrode 45 formed on the surface of the P + separation region 24. The island region 25 below the extension electrode 44 is configured to be used in a floating state where no potential is applied. Similarly, the island region 25 in which the J-FET element is formed is used in a floating state. Note that the semiconductor substrate 21 has a thickness of 200 to 400 μm. Whether the ground potential is applied to the back electrode of the substrate 21 is arbitrary.

FIG. 2 is a plan view showing an overall image of the semiconductor device. A semiconductor chip 50 having a chip size of about 2.5 × 3.0 mm has a diameter of 1.0 to
An extension electrode 43 of about 1.5 mm is provided, and a part of the extension electrode 43 extends and is connected to the gate electrode 35 of the J-FET element 51. At the periphery of the semiconductor chip 50, a plurality of bonding pads 52 for external connection are arranged. The bonding pad 52 has 10 sides.
It has a square of 0-300 μm. Other circuit elements, for example, an NPN transistor, a resistance element, a capacitance element, and the like are arranged in a region excluding the extension electrode 43 so as to surround the extension electrode 43.

As described above, by setting the semiconductor substrate 21 below the extension electrode 44 to have a high specific resistance, the series resistance R of the semiconductor substrate 21 becomes extremely large, so that the circuit is almost insulated. Not too much. Therefore, even if the capacitor C1 formed by the extended electrode 43 and the island region 25 using the oxide film 42 as a dielectric and the capacitor C2 formed by the PN junction between the island region 25 and the semiconductor substrate 21 are formed, By the action of the series resistor R, the connection beyond the capacitor C2 can be substantially insulated. The capacitance C3 is also generated by the PN junction between the island region 25 and the P + isolation region 24, and connects between the capacitance C1 and the ground potential GND, but the capacitance C3 can be neglected in consideration of the area ratio. Within (several tens of pF
Is several mpF). If the capacitance C3 is also taken into consideration, a pattern design in which no ground electrode is arranged at least on the surface of the isolation region 24 surrounding the extension electrode 43 is desirable.

In this way, by making the path to the ground potential GND substantially insulated, the extended electrode is connected to the ground potential G.
It is possible to prevent the occurrence of a parasitic current to the ND and prevent the amplitude level of the input signal from decreasing.

Hereinafter, the manufacturing method of the present invention will be described with reference to FIGS.

First step: See FIG. 3A A semiconductor substrate 21 having a high specific resistance as described above is prepared. The starting point is the P type, for example, 1000Ω · c
If it is more than m, it is difficult to define the conductivity type, and it may be referred to as an intrinsic (i) layer. An oxide film 60 is formed by thermally oxidizing the surface, and a resist mask 61 is formed thereon. The resist mask 61 selectively introduces boron (B) to the entire surface of the substrate 21 except for the region where the extension electrode 43 is to be arranged.

Second step: See FIG. 3B. The whole is subjected to a heat treatment at 1100 ° C. for several hours, and the introduced boron is thermally diffused to form a P-type diffusion region 4 on the surface of substrate 21.
4 is formed. The diffusion depth and impurity concentration are as described above. Third step: See FIG. 4A. The surface is thermally oxidized to form an oxide film, and an opening is formed in the oxide film by a photoetching technique. Antimony (Sb) is diffused on the surface of the semiconductor substrate 21 exposed at the opening to form an N + type buried layer 22. Subsequently, the oxide film is formed again, an opening is formed in the oxide film again by a photoetching technique, and boron (B) is formed on the surface of the substrate 21.
Implanted into the P + type buried layer 26 and the isolation region 2
4a is formed.

Fourth Step: See FIG. 4B Subsequently, after removing the oxide film mask for ion implantation, an N-type epitaxial layer 23 is formed by a vapor phase growth method. The film thickness is 5 to 12 μm, and the specific resistance ρ = 5 to 2
0 Ω · cm.

After the formation of the epitaxial layer, a Si oxide film is formed on the surface of the epitaxial layer 23, and an opening is formed in the Si oxide film by a photo-etching technique. Boron (B, BF2) is ion-implanted through the opening to form a P-type well region 27.
A heat treatment for about 1 to 3 hours is given.

Fifth Step: See FIG. 5A Subsequently, a resist mask for ion implantation is formed on the Si oxide film grown on the surface of the epitaxial layer 23 by the above-described heat treatment, and the resist mask corresponding to the upper isolation region 24b is formed. A P-type impurity, here, boron, is ion-implanted through the opening of the portion to be formed. Then, after removing the resist mask, 1100 ° C., 1 to 3 hours until the upper and lower isolation regions 24 a and 24 b are combined and the P-type buried layer 26 and the P-type well region 27 are combined. Diffuses by about heat treatment. By the isolation region 24, the epitaxial layer 23 is junction-isolated into an island region 25 where a junction field effect transistor (J-FET) or the like is to be formed.

Sixth step: Refer to FIG. 5B. After removing the SiO 2 film grown on the surface of the epitaxial layer 23 by the above heat treatment, the SiO 2 film of about 500 ° is again formed.
2 Reattach the film. A mask for ion implantation is provided on the SiO2 film with a photoresist film, a portion corresponding to the base region 36 and the gate contact region 30 of the NPN transistor is opened, and boron as a base impurity is ion-implanted therein. After removing the resist mask, 1100 ° C.
Base diffusion is performed by heat treatment for 1 to 2 hours. The base region 36 and the gate contact region 30 are the P-type well region 2
7 as a diffusion region shallower than the gate contact region 30.
Are arranged so as to cover the upper part of the PN junction between the P-type well region 27 and the N-type island region 25. That is, the gate contact region 30 annularly surrounds the peripheral portion of the P-type well region 27. Then, a mask for ion implantation is reattached, and portions corresponding to the emitter region 37, the source region 31, the drain region 32, and the collector contact region 38 to be formed are opened, and arsenic or phosphorus, which is an N-type impurity, is filled therein. Ions are implanted.

Seventh step: Refer to FIG. 6 (A).
A mask layer 63 having an opening 62 is formed on a portion of the Si oxide film corresponding to. The end of the opening 62 is located above the gate contact region 30 to expose the surface of the well region 27 and the surface near the inner peripheral end of the annularly formed gate contact region 30. Then, arsenic or phosphorus, which is an N-type impurity, is added through the opening of the mask layer 63 to 1.
Ion implantation is performed at × 10 ¹² to 10 ¹³ atoms / cm ³ to form a channel region 28.

While the mask layer 63 is kept as it is, B or BF ₂ which is a P-type impurity is passed through the opening 62 to 1 × 10 ¹³ to
Ion implantation at 10 ¹⁴ atoms / cm ³ , top gate region 2
9 is formed.

After that, the ion implantation mask is removed, and the emitter is diffused at 1000 ° C. for 30 to 1 hour to form an emitter region 37, a source region 31, and a drain region 32.
And the channel region 28 and the top gate region 29 are thermally diffused. After the emitter thermal diffusion, ion implantation and heat treatment of the channel region 28 and the top gate region 29 may be performed.

Eighth Step: See FIG. 6B A contact hole 65 is formed in the silicon oxide film 64 formed on the surface of the epitaxial layer 23 by these heat treatments by a general photo etching technique. In the region where the extension electrode 43 is to be formed, a film thickness of 8000 to 200
A silicon oxide film 64 of 00 ° is formed. CVD oxide film, SiN
A film or the like may be formed.

Then, an aluminum material is formed on the entire surface to a thickness of 1.0 to 3.0 μm by a sputtering or vapor deposition technique, and is photo-etched by a general photo-etching technique to form a source electrode 33 and a drain electrode 34. The gate electrode 35, the emitter electrode 39, the base electrode 40, the collector electrode 41, the ground electrode 45, and the extension electrode 43 are formed to obtain the configuration shown in FIG.

FIG. 7 is a sectional view showing a second embodiment of the manufacturing method. In the above-described manufacturing method, the lower part of the extension electrode is set to the high specific resistance state using the high specific resistance substrate 21. In this example, an N-type impurity (arsenic,
This is a method of diffusing antimony and the like, thereby offsetting the conductivity type as a result and increasing the specific resistance.

That is, as shown in FIG. 7A, the specific resistance which is frequently used in a normal bipolar type integrated circuit is 2.
A P-type substrate 21 of about 4 Ω · cm is prepared, a selection mask is formed on the surface of the substrate 21, and N-type impurities (arsenic, antimony, etc.) are selectively ion-implanted into a region below the extension electrode 43. Is thermally diffused to form a high resistivity region 70.
To form The specific resistance of the high specific resistance region 70 is 100 to 50.
The dose and the heat treatment are selected so as to be 00 Ω · cm.

Thereafter, through the same steps as the steps from FIG. 4A to FIG. 6B, as shown in FIG. 6B, a high specific resistance is formed on the surface of the substrate 21 below the extension electrode. Area 7
0 can be obtained.

In the above embodiment, an N-channel type J-FET is taken as an example. However, a P-channel type J-FET can be formed. In addition, J as an input transistor
-N-channel, P-channel type M
A device using an OSFET device may be used.

[0041]

According to the present invention, a large value capacitor C1,
Since the substrate 21 below the extension electrode 43 that inevitably generates C2 is selectively brought into a high resistivity state, the capacitance C2
Can be made substantially insulated, thereby eliminating the conventional problem that the signal input from the electric condenser microphone flows out and lowers the signal level.

When a high-resistivity substrate is used as the substrate 21, the nucleic acid region 44 is provided below the circuit element to replace the role of the conventional substrate and prevent leakage between the island regions 25. The junction separation between the circuit elements can be achieved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining the present invention.

FIG. 2 is a plan view for explaining the present invention.

FIG. 3 is a cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 4 is a cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 5 is a cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 6 is a cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 7 is a cross-sectional view for explaining the manufacturing method of the present invention.

FIG. 8 is a sectional view for explaining a conventional example.

FIG. 9 is a circuit diagram for explaining a conventional example.

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Claims (8)

[Claims] 1. A semiconductor substrate, a semiconductor layer formed on the substrate, an input transistor formed on the semiconductor layer, an insulating film covering a surface of the semiconductor layer, and an input terminal of the input transistor. And an extended electrode extending over the insulating film, wherein the specific resistance of the semiconductor layer below the extended electrode is partially set high. 2. The semiconductor device according to claim 1, wherein said input transistor is a junction field effect transistor. 3. The semiconductor device according to claim 1, wherein a specific resistance of the partially set semiconductor substrate is 100 to 5000 Ω · cm. 4. A semiconductor substrate, a semiconductor layer formed on the substrate, an island region separating the semiconductor layer, an input transistor formed in the island region, and an insulating film covering a surface of the semiconductor layer And an extended electrode that is connected to the input terminal of the input transistor and extends on the insulating film. The semiconductor substrate has a specific resistance of 100 Ω · cm or more, and the lower part of the field effect transistor. A semiconductor device having a diffusion region of one conductivity type formed on a surface of a substrate. 5. The semiconductor device according to claim 4, wherein said input transistor is a junction field effect transistor. 6. The semiconductor substrate having a specific resistance of 100 to 50.
5. The semiconductor device according to claim 4, wherein the resistance is set to 00 Ω · cm. 7. The semiconductor device according to claim 4, wherein an electrode wiring for applying a ground potential to said one conductivity type diffusion region is formed. 8. An electrode wiring for applying the ground potential is formed on a surface of a one-conductivity type separation region extending from a surface of the semiconductor layer to a surface of the one-conductivity type diffusion region. The semiconductor device according to claim 7.