JP2000306835A - Manufacture of insulated gate field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the throughput of an insulated gate field effect transistor manufacturing method by making an amorphous silicon film crystallizable at a relatively low temperature through formation of island-like films containing specific metals on the amorphous silicon film and annealing the island-like films at a specific temperature. SOLUTION: A base silicon oxide film 1B is formed on a substrate 1A by the plasma CVD method, and an amorphous silicon film 1 is formed on the film 1B by the CVD method. Then the film 1 is dehydrogenated by annealing the film 1 for 0.1-2 hours at a temperature of 350-450 deg.C and island-like films, dots, particles, clusters, lines, etc., containing nickel, iron, cobalt, and platinum are formed on or under the film 1 and annealed at a temperature, which is lower than the crystallization temperature of ordinary amorphous silicon by, preferably, 20-150 deg.C, namely for example, at 580 deg.C or lower. Therefore, the crystallization started from two island-like nickel films, etc., come into collision with each other and the crystallization ends by leaving nickel silicide 3A in the middle.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for obtaining a crystalline semiconductor used for a thin film device such as a thin film insulated gate field effect transistor (thin film transistor or TFT).

[0002]

2. Description of the Related Art Conventionally, a crystalline silicon semiconductor thin film used for a thin film device such as an insulated gate type field effect transistor (TFT) is formed on an insulating surface such as an insulating substrate by a plasma CVD method or a thermal CVD method. The obtained amorphous silicon film was crystallized in a device such as an electric furnace at a temperature of 600 ° C. or more for a long time of 12 hours or more. In particular, a longer heat treatment has been required to obtain sufficient characteristics (high electrolytic effect mobility and high reliability).

[0003]

However, such a conventional method has many problems. One is lower throughput and therefore higher cost. For example, assuming that the crystallization step requires 24 hours, if the processing time per substrate is 2 minutes, 720 substrates must be processed simultaneously. However, for example, in a commonly used tubular furnace, at most 50 substrates can be processed at a time, and when only one apparatus (reaction tube) is used, it takes 30 minutes per substrate. I have. That is, 1
In order to achieve a processing time of 2 minutes per sheet, as many as 15 reaction tubes had to be used. This meant that the size of the investment would increase, and that the investment would be significantly depreciated, which would return to the cost of the product.

[0004] Another problem was the temperature of the heat treatment. In general, substrates used for manufacturing TFTs are roughly classified into those made of pure silicon oxide such as quartz glass and non-alkali borosilicate glass such as Corning No. 7059 (hereinafter referred to as Corning 7059). Among them, the former has excellent heat resistance and can be handled in the same manner as a wafer process of a normal semiconductor integrated circuit, so that there is no problem regarding the temperature. However, its cost is high, and it increases exponentially rapidly as the substrate area increases. Therefore, at present, a relatively small area T
Used only for FT integrated circuits.

On the other hand, alkali-free glass has a sufficiently low cost as compared with quartz, but has a problem in terms of heat resistance, and generally has a strain point of about 550 to 650 ° C. Therefore, the heat treatment at 600 ° C. caused a problem of irreversible shrinkage and warpage of the substrate. In particular, it was remarkable for a large substrate having a diagonal exceeding 10 inches. For the above reasons, regarding crystallization of a silicon semiconductor film, a heat treatment condition of 550 ° C. or lower and within 4 hours has been indispensable for cost reduction. An object of the present invention is to provide a method for manufacturing a semiconductor which satisfies such a condition and a method for manufacturing a semiconductor device using such a semiconductor.

[0006]

SUMMARY OF THE INVENTION The present invention relates to an amorphous state or a disordered crystalline state that can be said to be substantially amorphous (for example, a state in which a portion having good crystallinity and an amorphous portion are mixed). ) An island-like film, dots, particles, clusters, lines, etc. containing nickel, iron, cobalt, and platinum are formed above or below the silicon film in), which are lower than the crystallization temperature of normal amorphous silicon. A crystalline silicon film is obtained by annealing at a temperature, preferably 20 to 150 ° C. lower, for example, 580 ° C. or lower.

With respect to the conventional crystallization of a silicon film, a method of solid-phase epitaxial growth using a crystalline island-like film as a nucleus and using this as a seed crystal (for example, Japanese Patent Laid-Open No. 1-21)
4110). However, in such a method, crystal growth hardly proceeded at a temperature of 600 ° C. or less. In a silicon system, generally, in order to transition from an amorphous state to a crystalline state, a molecular chain in an amorphous state is divided, and furthermore, the divided molecule is brought into a state where it does not bind to another molecule again. It goes through the process of recombining a molecule into a part of the crystal in accordance with some crystalline molecule. However, during this process, the energy required to break the initial molecular chain and keep it unbound to other molecules is large,
This is a barrier in the crystallization reaction. In order to provide this energy, at a temperature of about 1000 ° C. for several minutes,
Alternatively, at a temperature of about 600 ° C., several tens of hours are required, and since the time depends exponentially on the temperature (= energy), at 600 ° C. or less, for example, at 550 ° C., the crystallization reaction hardly progresses. It could not be observed. The conventional idea of solid phase epitaxial crystallization did not provide a solution to this problem.

The present inventor has considered, apart from the conventional idea of solid-phase crystallization, to reduce the barrier energy of the above-mentioned process by some catalytic action. The present inventor has reported that nickel (Ni), platinum (Pt), iron (Fe), and cobalt (Co) combine with silicon to form a silicide.
Regarding nickel, nickel silicide (chemical formula Ni
_{Si x, 0.4 ≦ x ≦ 2.5} ) becomes and, the lattice constants of nickel silicide is noticed that close to that of silicon crystal. Thus, as a result of simulating the energy of a ternary system such as crystalline silicon-nickel silicide-amorphous silicon, amorphous silicon easily reacts at the interface with nickel silicide, and amorphous silicon (silicon A) + nickel silicide (silicon B) → It became clear that the reaction of nickel silicide (silicon A) + crystalline silicon (silicon B) (silicon A and B indicate the position of silicon) occurs. The potential barrier for this reaction is sufficiently low and the temperature of the reaction is low.

This reaction equation shows that nickel proceeds while converting amorphous silicon into crystalline silicon. In fact, it was found that the reaction started below 580 ° C., and that the reaction was observed even at 450 ° C. Typically, it has been shown that crystallization can be performed at a temperature 20 to 150 ° C. lower than the crystallization temperature of normal amorphous silicon. Naturally, the higher the temperature, the faster the reaction proceeds. This is shown in FIG. 3 (see Example). The same effect is obtained by using platinum (Pt),
Iron (Fe) and cobalt (Co) were also observed.

A feature of the present invention is that crystal growth progresses in a circular shape. This is because the movement of nickel and the like in the above-described reaction proceeds isotropically, which is different from the conventional crystallization that grows linearly along the crystal lattice plane.

In the present invention, island-like, stripe-like, linear,
Starting from a film, particle, cluster, or the like containing at least one of nickel, iron, cobalt, and platinum such as dot-like nickel, iron, cobalt, and platinum alone or a silicide thereof, nickel, iron, cobalt, The platinum expands to the surroundings with the above reaction, thereby expanding the region of crystalline silicon. Note that an oxide is not preferable as a material containing nickel, iron, cobalt, and platinum. This is because oxides are stable compounds and cannot initiate the above reaction.

The crystalline silicon expanded from a specific place is different from the conventional solid phase epitaxial growth, but has a good continuity in crystallinity and a structure close to a single crystal. It is convenient for use in an element. When a material containing nickel, iron, cobalt, and platinum is uniformly provided on the substrate, there are numerous starting points for crystallization, and it has been difficult to obtain a film having good crystallinity. The difference typically appears clearly in Raman scattering spectroscopy and X-ray diffraction, and in the present invention, good crystallinity was clarified by these partial means.

The amorphous silicon film as a starting material for this crystallization had better results as the hydrogen concentration was lower. However, since hydrogen is released as the crystallization progresses, the hydrogen concentration in the obtained silicon film did not show a clear correlation with the hydrogen concentration in the starting amorphous silicon film. The hydrogen concentration in the crystalline silicon according to the present invention was typically 0.01 atomic% or more and 5 atomic% or less. Furthermore, in order to obtain good crystallinity, the lower the concentration of carbon, nitrogen, and oxygen in the amorphous silicon film, the better, and it is desirable that the concentration be 1 × 10 ¹⁹ cm ⁻³ or less. Therefore, a material containing nickel, iron, cobalt, and platinum used in the present invention should be selected in consideration of this point.

However, nickel, iron, cobalt and platinum themselves are not preferable for silicon as a semiconductor material. So it is necessary to remove this,
As for nickel, as a result of the above-described reaction, nickel silicide that has reached the end of crystallization is easily dissolved in hydrofluoric acid or hydrochloric acid. Therefore, nickel can be reduced from the substrate by treatment with these acids. The concentration of nickel in the silicon film according to the present invention was typically not more than 0.005% and not more than 1 atomic%.

In utilizing the crystalline silicon film produced according to the present invention for a semiconductor device such as a TFT, as is apparent from the above description, the termination of crystallization (here, the crystallization started from a plurality of starting points) Is where it hits)
There are large grain boundaries (crystal discontinuities),
It is not preferable to provide a semiconductor element because the concentration of nickel is high. Therefore, in forming a semiconductor device using the present invention, the pattern of the nickel-containing film and the pattern of the semiconductor device, which are the starting points of crystallization, must be optimized. Hereinafter, the present invention will be described in more detail with reference to Examples.

[0016]

EXAMPLE In this example, a plurality of island-shaped nickel films were formed on a Corning 7059 glass substrate, an amorphous silicon film was crystallized starting from these, and a TFT was formed using the obtained crystalline silicon film. The method for producing the is described. There are two methods for forming an island-like nickel film in terms of whether to provide it above or below an amorphous silicon film. FIG. 2 (A-
1) is a method provided below, and FIG. 2 (A-2) is a method provided above. In particular, the latter must be noted because nickel is formed on the entire surface of the amorphous silicon film and then this is selectively etched, so that nickel and amorphous silicon react in a small amount to form silicide. Nickel is formed. If this is left as it is, a silicon film having good crystallinity as intended by the present invention cannot be obtained. Therefore, it is required to sufficiently remove the nickel silicide with hydrochloric acid, hydrofluoric acid, or the like. . Therefore, the amorphous silicon becomes thinner than the initial state.

In any case, nickel (or nickel silicide) is patterned by a conventionally known etch-off method (a photoresist is patterned by a photolithography method after forming a nickel film, and a portion without the photoresist is formed). (A method of selectively forming a nickel film by etching a nickel film) or a lift-off method (a photoresist is patterned by a photolithography method, a nickel film is formed thereon, and the underlying photoresist is removed. In this case, a method of selectively forming a nickel film may be used.

On the other hand, the former does not cause such a problem, but in this case, it is desired that the nickel film other than the island portions is completely removed by etching. Further, in order to suppress the influence of the remaining nickel, the substrate may be treated with oxygen plasma, ozone, or the like to oxidize nickel in regions other than the island region.

In each case, the substrate (Corning 705)
9) On top of 1A, underlying silicon oxide film 1B having a thickness of 2000
Was formed by a plasma CVD method. The amorphous silicon film 1 has a thickness of 200 to 3000 °, preferably 500 to 1500 °, and is manufactured by a plasma CVD method or a low pressure CVD method. The amorphous silicon film is dehydrogenated by annealing at 350 to 450 ° C. for 0.1 to 2 hours to reduce the hydrogen concentration in the film to 5%.
Crystallization was easy when the content was less than atomic%. FIG. 2 (A
In the case of -1), a nickel film having a thickness of 50 to 100 is formed by a sputtering method before the formation of the amorphous silicon film 1.
0 °, preferably 100 to 500 °, was deposited and then patterned to form island-shaped nickel regions 2.

On the other hand, in the case of FIG. 2A-2, after the formation of the amorphous silicon film 1, a nickel film is formed by sputtering to a thickness of 50 to 1000 Å, preferably 100 to 1000 Å.
An island-shaped nickel region 2 was formed by depositing 500 ° and patterning it. Figure 1 shows this situation viewed from above.
It is shown in (A).

The island nickel was a square having a side of 2 μm, and the interval was 5 to 50 μm, for example, 20 μm. Similar effects can be obtained by using nickel silicide instead of nickel. When depositing nickel, the substrate should be 100 to 5 mm.
Good results were obtained by heating to 00 ° C, preferably 180-250 ° C. This is because the adhesion between the underlying silicon oxide film and the nickel film is improved, and the silicon oxide reacts with the nickel to produce nickel silicide. Similar effects can be obtained by using silicon nitride, silicon carbide, or silicon instead of silicon oxide.

Next, this is heated at 450-580 ° C., for example, at 5 ° C.
Annealing was performed at 50 ° C. for 8 hours in a nitrogen atmosphere. FIG.
FIG. 2B shows the intermediate state. In FIG. 2A, nickel proceeds from the island-like nickel film at the end to the central portion as nickel silicide 3A, and the portion 3 through which nickel has passed is crystal. It is silicon. Eventually, FIG.
As shown in (C), the crystallization starting from the two island-shaped nickel films hits, leaving nickel silicide 3A in the middle, and the crystallization ends. FIGS. 4 and 5 show Raman scattering spectroscopy of the crystalline silicon film obtained according to this embodiment and X-ray diffraction.
The result of a line diffraction is shown. C-Si in FIG. 4 is a spectrum of single crystal silicon as a standard sample, (a) is a crystal region obtained by the present example, and (b) is a Raman spectrum of an uncrystallized region. Both the Raman spectrum and the X-ray diffraction of the crystal region indicate that good crystals were obtained.

FIG. 1B shows a state of the substrate in this state viewed from above. The nickel silicide 3 shown in FIG.
A is the grain boundary 4. If the annealing is further continued, nickel moves along the grain boundaries 4 and gathers in the intermediate region 5 of these island-like nickel regions (although the original shape is not retained at this stage).

Although crystalline silicon can be obtained by the above steps, it is not preferable that nickel diffuses from the nickel silicide 3A generated at this time into the semiconductor film. Therefore, it is desired to perform etching with hydrofluoric acid or hydrochloric acid. Note that neither hydrofluoric acid nor hydrochloric acid affects the silicon film. FIG. 2D shows the state after the etching. The portion having the grain boundary becomes the groove 4A. T so as to sandwich this groove
It is not preferable to form an FT semiconductor region (such as an active layer). As for the arrangement of TFTs, an example is shown in FIG.
As shown in FIG. 3, the semiconductor region 6 was arranged so as not to cross the grain boundary 4. On the other hand, the gate wiring 7 may cross the grain boundary 4.

When the amorphous silicon film was crystallized by the above method, the dependence of the rate at which crystallization progressed from the nickel region of 2 μm square on the annealing temperature was examined. Here, the tip of crystallization is 10 to 50 μm from the nickel region.
The crystallization rate was calculated from the annealing time required to reach the distance. FIG. 3 shows an example. In the figure, there are two types of amorphous silicon film thickness (500 ° and 1500 °).
Prepared and compared. As a matter of course,
The higher the annealing temperature, the higher the crystallization rate.
In addition, it was found that depending on the thickness of the amorphous silicon film, the thicker the film, the easier it is to crystallize. Since the typical size of one actual semiconductor device is 50 μm or less, if the annealing time is 5 hours, the crystallization speed is 20 μm /
Assuming that the temperature is at least hr and the silicon film thickness is 1500 °, the data in FIG. 3 indicates that a temperature of 550 ° C. or more is required.

[0026]

As described above, the present invention is epoch-making in that it promotes lowering the temperature and shortening the time of crystallization of amorphous silicon.
Since the apparatus and the method are very general and excellent in mass productivity, the profits brought to the industry are invaluable.

For example, in the conventional solid-phase growth method, since annealing for at least 24 hours was required,
Assuming that the substrate processing time per substrate is 2 minutes, as many as 15 annealing furnaces were required.
Since the number of annealing furnaces can be reduced to less than 1/6, the number of annealing furnaces can be reduced to 1/6 or less. Improvement in productivity and reduction in capital investment due to this leads to a reduction in substrate processing cost, which in turn leads to a reduction in TFT price and thus a new demand. Thus, the present invention is industrially useful and deserves a patent.

[Brief description of the drawings]

FIG. 1 shows a top view of the steps of an embodiment. (Crystallization and TFT arrangement)

FIG. 2 shows a cross-sectional view of a process of the embodiment. (Step of selective crystallization)

FIG. 3 shows the relationship between crystallization speed and temperature.

FIG. 4 shows Raman scattering spectroscopy results of crystalline silicon obtained in an example.

FIG. 5 shows an X-ray diffraction result of crystalline silicon obtained in the example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Amorphous silicon 2 ... Nickel-shaped nickel film 3 ... Crystal silicon 4 ... Grain boundary 5 ... A region where crystallization has not progressed 6 ... Semiconductor region 7 ... Gate wiring

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shunpei Yamazaki 398 Hase, Atsugi-shi, Kanagawa Prefecture Inside Semi-Conductor Energy Laboratory Co., Ltd.

Claims (9)

[Claims] 1. A substantially amorphous silicon film is formed on an insulating surface of a substrate, and a material containing at least one metal element of nickel, iron, cobalt, and platinum is contacted with the surface of the silicon film. Forming, heating the silicon film to react the metal element of the material with the silicon film to crystallize the silicon film, patterning the crystallized silicon film, and forming an active layer on the patterned silicon film. Forming an insulating gate type field effect transistor, wherein, by the heating, an amorphous portion of the silicon film in contact with the material reacts with the metal element to form a metal silicide, and the metal silicide The amorphous portion of the silicon film that is in contact with the metal silicide reacts to convert the amorphous silicon portion into a metal silicide. And silicon atoms of the metal silicide are bonded to form silicon crystals, the method for manufacturing an insulated gate field effect transistor. 2. Nickel, iron,
Forming a material containing at least one metal element of cobalt and platinum; forming a silicon film in a substantially amorphous state in contact with the material; heat-treating the silicon film to form a metal element of the material and the silicon A method of manufacturing an insulated gate field effect transistor, wherein the silicon film is crystallized by reacting a film, the crystallized silicon film is patterned, and an active layer is formed on the patterned silicon film. By heating, the amorphous portion of the silicon film in contact with the material reacts with the metal element to form a metal silicide, and the metal silicide reacts with the amorphous portion of the silicon film in contact with the metal silicide. Then, the amorphous silicon portion is made into a metal silicide, and silicon atoms of the metal silicide combine to form a silicon silicide. Insulated gate field effect method for producing a transistor, wherein a down of crystals are produced. 3. A substantially amorphous silicon film is formed on an insulating surface of a substrate, and nickel is selectively contacted with the surface of the silicon film.
Forming a material containing at least one metal element of iron, cobalt and platinum, heat treating the silicon film, and crystallizing the silicon film by reacting the metal element of the material with the silicon film; A method for manufacturing an insulated gate field effect transistor in which an active layer is formed on the patterned silicon film by patterning the patterned silicon film, wherein the heating causes the amorphous portion of the silicon film to be in contact with the material. Reacts with the metal element to form a metal silicide, and the metal silicide reacts with an amorphous portion of the silicon film in contact with the metal silicide to turn the amorphous silicon portion into a metal silicide, Gate-type field effect characterized by formation of silicon crystals by bonding of silicon atoms Method of manufacturing a transistor. 4. A method for forming a material containing at least one metal element of nickel, iron, cobalt and platinum by selectively contacting an insulating surface of a substrate, and forming a substantially amorphous silicon film in contact with said material. Forming, heat-treating the silicon film, crystallizing the silicon film by reacting the metal element of the material with the silicon film, patterning the crystallized silicon film, A method of manufacturing an insulated gate field effect transistor forming an active layer, wherein the heating causes an amorphous portion of the silicon film in contact with the material to react with the metal element to form a metal silicide, and the metal silicide is formed. And the amorphous portion of the silicon film in contact with the metal silicide reacts to form the amorphous silicon portion. A method for manufacturing an insulated gate field effect transistor, wherein a metal silicide is formed, and silicon atoms of the metal silicide combine to form a silicon crystal. 5. The method according to claim 1, wherein:
The heating temperature for crystallizing the silicon film is 450 ° C. to 5 ° C.
A method for producing an insulated gate field effect transistor, wherein the temperature is in the range of 80 ° C. 6. The method according to claim 1, wherein:
The material containing the metal element is NiSi _x (0.4 ≦ X ≦
2.5. A method for manufacturing an insulated gate field effect transistor, comprising nickel silicide as described in 2.5). 7. The method according to claim 1, wherein
The method for manufacturing an insulated gate field effect transistor, wherein the material is a film containing the metal element formed by a sputtering method. 8. The method according to claim 1, wherein
A method for manufacturing an insulated gate field effect transistor, wherein the concentration of oxygen, carbon and nitrogen in the substantially amorphous silicon film is in a range of 1 × 10 ¹⁹ cm ⁻³ or less, respectively. 9. The method according to claim 1, wherein:
The crystallized silicon film has a concentration of the metal element.
A method for manufacturing an insulated gate field effect transistor, wherein the content is 0.005 to 1 atomic%.