JP2000305918A - System and method for multiprocessor supervisory control - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiprocessor supervisory control system which places a small load over a monitored processor and has simple constitution by connecting multiple supervisory controlled devices to a single supervisory control processor through a common bus and handling the multiple supervisory controlled devices as a single supervisory controlled device from the supervisory control device. SOLUTION: In the constitution wherein the supervisory control processor 11 and multiple supervisory controlled devices 21 to 2m are connected by the common bus 3, processors 211 to 2m1, and 212 to 2m2 constituting the supervisory controlled devices 21 to 2m are connected by leased communication lines 41 to 4m. In a single logically composition state, supervisory control is performed from the supervisory processor 11. Consequently, the number of wires between the supervisory control processor 11 and multiple supervisory controlled devices 21 to 2m is decreased, an I/O memory map for communication is reduced, and the load on the supervisory processor 11 can be lightened by load decentralization.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor control technique, and more particularly to a supervisory control processor for monitoring and controlling the state between a plurality of monitored control devices, and a multiprocessor having a simple configuration with a small load on the monitored processor. The present invention relates to a supervisory control system and a multiprocessor supervisory control method.

[0002]

2. Description of the Related Art In a conventional multiprocessor supervisory control system, a supervisory control processor and a plurality of monitored control devices are generally connected on a one-to-one basis. Accordingly, there has been a problem that the number of wires between the monitoring control processor and the plurality of monitored control devices increases.

As a prior art for solving such a problem, for example, Japanese Patent Application Laid-Open No.
No. 0 publication. FIG. 5 is a functional block diagram for explaining a conventional multiprocessor supervisory control system. A conventional multiprocessor supervisory control system configured for a base station wireless device for mobile communications comprises:
As shown in FIG. 5, a plurality of processors {811, 812} ({821, 822},...) Constituting the monitoring control processor 711 and the monitored control device 81 (82,.
{8m1, 8m2}) are connected in parallel via an interface circuit 713. The common storage area memory 7 is located between the monitoring control processor 711 of the monitoring control unit 71 and the plurality of monitored control devices 81,.
12 and the monitored control device 81 (82,..., 8m)
, 8 m, and polls the common storage area memory 712 from among the plurality of monitored control devices 81,..., 8 m to read a message corresponding to the address assigned to itself, or By adding the address and writing, the monitoring control processor 711 and the plurality of monitored control devices 81,.
It is disclosed to reduce wiring between them.

[0004]

However, the prior art has the following problems. First, a first problem is that a common storage area memory 712 must be added as a peripheral device of the monitoring control processor 711. The second problem is that a plurality of monitored control devices 8
In order to access the common storage area memory 712 between 1, 2,..., 8 m, an interface circuit 713 for performing bus arbitration control must be added. The third problem is that since the common storage area memory 712 must be polled from the side between the plurality of monitored control devices 81,..., 8m, the plurality of monitored control devices 81,.
An extra load is applied between m.

The present invention has been made in view of the above problems, and has as its object to reduce the load on a supervisory control processor that monitors and controls the state between a plurality of monitored controllers and a load on the monitored processor. An object of the present invention is to provide a multiprocessor supervisory control system and a multiprocessor supervisory control method which are small and simple in configuration.

[0006]

The gist of the present invention is to provide a monitoring control processor for monitoring and controlling the state between a plurality of monitored control devices and a multi-processor having a simple configuration with a small load on the monitored processor. A processor monitoring and control system, wherein a plurality of monitored control devices, each of which includes a plurality of processors and constitutes one unit, are connected to a single monitoring and control processor via a common bus, and the monitoring and control processor A multiprocessor monitoring and control system is characterized in that each of the plurality of monitored and controlled devices is configured to be treated as a single monitored and controlled device. The gist of the invention described in claim 2 is that the plurality of monitored control devices are configured as one monitored control device so as to perform monitoring control from the monitoring control processor. 1 is a multiprocessor monitoring and control system. The gist of the invention described in claim 3 is that the monitored control device sets one of the plurality of processors connected by a dedicated communication path as a master processor, and always sends the state information to the master processor via the dedicated communication line. Are configured as slave processors, and the monitoring control processor performs monitoring control as a single state obtained by logically synthesizing the states of the master processor and the slave processors. 2. The multiprocessor supervisory control system according to claim 1, wherein: The gist of the invention according to claim 4 is that the master processor outputs to the monitoring control processor a status of the monitored control device that is generated by processing status information constantly supplied from the slave processor. 4. The multiprocessor supervisory control system according to claim 3, further comprising an O port. The gist of the invention described in claim 5 is that the supervisory control processor writes the control instruction to the I / O port of the monitored device by using the dedicated communication path between the processors. 5. The multiprocessor monitoring and control system according to claim 4, wherein the written state of the master processor and the slave processor in the monitored and controlled device is changed. The gist of the invention described in claim 6 is that the supervisory control processor determines a state as the monitored control device obtained by calculating a state of the master processor and the slave processor in the monitored control device. 5. The multiprocessor monitoring and control system according to claim 4, wherein the monitoring is performed by reading the I / O port of the monitored and controlled device. According to another aspect of the present invention, there is provided a supervisory control processor that monitors and controls a state between a plurality of monitored control devices, and a multiprocessor supervisory control method having a simple configuration with a small load on the monitored processor. Connecting a plurality of monitored control devices, each of which constitutes one unit by integrating a plurality of processors, to a single monitoring control processor via a common bus; The present invention resides in a multiprocessor supervisory control method including a step of treating each of them as a single monitored controller. The gist of the invention described in claim 8 is to have a step of performing monitoring control from the monitoring control processor as one monitored control device between the plurality of monitored control devices. Multi-processor monitoring and control method. The gist of the invention according to claim 9 is that the monitored control device includes:
One of the plurality of processors in the monitored control device connected by a dedicated communication path is used as a master processor, and the other of the plurality of processors, to which status information is always supplied to the master processor via the dedicated communication line, is used as a slave. 8. The multiprocessor monitor according to claim 7, further comprising: a processor; and a monitor control from the monitor control processor as a single state obtained by logically combining states of the master processor and the slave processor. It lies in the control method. The gist of the invention according to claim 10 is that the state of the monitored control device, which is generated by processing the state information constantly supplied from the slave processor, is determined by the master processor by setting the I / O port to the monitor control processor. The method according to claim 9, further comprising the step of outputting the data via a multiprocessor. According to another aspect of the present invention, the supervisory control processor writes a control command to the I / O port of the monitored device and writes the control command using the dedicated communication path between the processors. The multiprocessor monitoring and control method according to claim 10, further comprising a step of changing states of the master processor and the slave processor in the monitored control device. The gist of the invention according to claim 12 is that the state as the monitored control device obtained by calculating the states of the master processor and the slave processor in the monitored control device is the same as the monitored control device. 11. The method according to claim 10, further comprising a step of monitoring an I / O port by reading the I / O port by the supervisory control processor.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The feature of each embodiment described below is that a plurality of monitored control devices, each of which comprises a plurality of processors collectively forming one unit, are connected to the monitoring control processor via a common bus, and the monitoring is performed. The control processor treats each of the plurality of monitored control devices as a single monitored control device, thereby reducing the number of wires between the monitored control processor and the plurality of monitored control devices, and controlling the communication I / O.
An object of the present invention is to reduce the load on the supervisory control processor by reducing the / O memory map, and further by distributing the load. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
It is a functional block diagram for explaining the multiprocessor supervisory control system according to the embodiment. In FIG. 1, 1 is a monitoring control unit, 3 is a common bus, 11 is a monitoring and control processor, 21, 22,...
, 2m0 are I / O ports, 211,
21,..., 2m1 are master processors, 212, 22
2, ..., 2m2 are slave processors, 41, 42,
.., 4 m are dedicated communication paths. Referring to FIG. 1, the multiprocessor supervisory control system of the present embodiment can be used to monitor and control a signal processing unit in a mobile communication base station radio apparatus. From the monitoring control processor 11 in the monitoring target control device 21 (2
2,..., 2m).

As shown in FIG. 1, a supervisory control processor 1
, 2m are connected by a common bus 3 to the monitored control device 21,..., 2m.
(22,..., 2m)
1,212} ({221,222}, ..., {2m1,2
m2｝) are respectively assigned to the dedicated communication paths 41 (42,..., 4).
m).

In the multiprocessor monitoring and control system, a plurality of processors {211, 212} ({221, 212) connected by a dedicated communication path 41 (42,.
, {2m1, 2m2}) as a master processor, and a plurality of processors {211, 212} connected by a dedicated communication path 41 (42,..., 4m).
({221, 222},..., {2m1, 2m2}) are supervised and controlled by the supervisory control processor 11 as a single state that is logically synthesized.

On the other hand, a plurality of monitored control devices 21,.
The control signals from the interval m are monitored control devices 21 (22,...,
2m) within the master processor 211 (221,..., 2m).
1), and the monitored control device 21 (22,..., 2)
m), dedicated communication paths 41 (42,...) between the processors.
4m), the slave processor 212 (222,...,
2m2).

The slave processor 212 (22)
, 2m2) to the master processor 211 (22
1,..., 2m1) have dedicated communication paths 41 (42,.
m) is constantly supplied with the status information, and the master processor 211 (221,..., 2m1) processes the information and sets the status of the monitored control device 21 (22,. Output to the I / O port 210 (220,..., 2m0) that can be read.

Thus, the number of wires between the supervisory control processor 11 and the plurality of monitored control devices 21,..., 2m is reduced, the I / O memory map for communication is reduced, and the supervisory control processor 11 Load can be reduced.

FIG. 2 shows the monitored control device 21 (22, 22
, 2m) are functional block diagrams for explaining one configuration. In FIG. 2, 210, 220,...
, 2m1 are master processors, 212, 222,..., 2m2 are slave processors, 53 is a BLK signal (BLK), 54 is a UBLK signal (UBLK), 55 is an ALM signal (ALM), 56 is an ACTST signal (ACTST), 57 is a BLKST signal (BLKST), 58 is an ALMST signal (ALMST)
It is. Referring to FIG. 2, the monitored control device 21 of FIG.
(22,..., 2m) are configured as follows. That is, the master processor 211 (221,..., 2m
1) is an I / O port 210 (220, 220
, 2m0) are prepared, and the master processor 21
1 (221,..., 2m1) to the slave processor 21
2 (222,..., 2m2)
A BLK signal (BLK) 53 representing block control, an UBLK signal (UBLK) 54 representing block release control, and an ALM signal (ALM) 55 representing forced alarm control are provided, and the slave processor 212 (222,..., 2m2).
As a notification signal for notifying the master processor 211 (221,..., 2m1) of the state, A indicating the normal state
CTST signal (ACTST) 56, BL indicating closed state
KST signal (BLKST) 57, A indicating alarm status
An LMST signal (ALMST) 58 is provided.

Next, the operation of the multiprocessor supervisory control system (multiprocessor supervisory control method) will be described. FIG. 3 is a flowchart for explaining the multiprocessor monitoring control method according to the first embodiment of the present invention. As shown in the flowchart of FIG. 3, the supervisory control processor 11 executes a supervisory control operation using a communication method based on polling / selection, and determines whether or not control of the monitored control device 21 (22,..., 2m) is necessary. (Step 1), and if control is necessary (YES in step 1), the corresponding monitored control device 21
The I / O port 210 (2
, 2m0) (step 2). If there is no need for control (N in step 1)
O), the operation shifts to the monitoring operation, and the I /
Monitoring is performed by sequentially reading out status information from the O port 210 (220,..., 2m0) (step 3).

On the other hand, the monitored control device 21 (22,..., 2)
m) are slave processors 212 (222,..., 2m).
The signal potential “L” of the ACTST signal (ACTST) 56 indicating the state of 2) is in a normal state, and the BLKST signal (BLKS)
T) The signal potential “L” of 57 is transmitted to the master processor as a closed state, and the signal potential “L” of the ALMST signal (ALMST) 58 as an abnormal state is transmitted to the master processor. Monitored control device 21 (2
,..., 2m) change in the slave processor 2
2 (2m2) and the operation of the state of the master processor 211 (221,..., 2m1) are performed according to the state table of Table 1.
1,..., 2m1). Monitored control device 21 generated in this manner
The change in the state of (22,..., 2m) is caused by the I / O port 210
(220,..., 2m0).

[0017]

[Table 1]

The master processor 211 (221, 221)
, 2m1) I / O port 210 (220, ..., 2m)
The control processor 11 writes the control data to the address (I / O port address) 0), and the master processor 211 (221,..., 2m1) changes its own state in accordance with the control data, and the slave processor 212
By transmitting each control by outputting a pulse to the control signal line to (222,..., 2m2), the monitoring control sequence from the monitoring control processor 11 is executed.

As described above, according to the first embodiment, the following effects can be obtained. First, the first effect is
The dedicated communication path 41 between the master processor 211 (221,..., 2m1) and the slave processor 212 (222,..., 2m2) of the monitored controller 21 (22,.
By providing (42,..., 4m), the monitoring and control processor 11 can monitor or control a unified state as the monitored control device 21 (22,..., 2m). The second effect is that, since the monitoring control operation using polling and selecting is performed, bus arbitration in access using the common bus 3 can be omitted, and the monitoring control processor 11 and the monitored control devices 21 and 22 can be omitted. ,…,
That is, the wiring between 2 m can be reduced. The third effect is that the load between the monitoring control processor 11 and the plurality of monitored control devices 21,..., 2m can be reduced, and the processing speed can be increased.

(Second Embodiment) FIG. 4 is a functional block diagram for explaining another configuration of the monitored control device 21 (22,..., 2m) in FIG. The second embodiment has the same basic configuration as the first embodiment, but
The monitored control device 21 (22,..., 2m) is further devised. The configuration is shown in FIG. The same portions as those already described in the first embodiment are denoted by the same reference numerals, and duplicate description will be omitted. FIG.
, 2m0 are I / O ports, 211, 221,..., 2m1 are master processors,
, 2m2 are slave processors, 2m2
13, 223,..., 2m3 are sub master processors, 6
11, 621 are BLK signals (BLK), 612, 622
Is the UBLK signal (UBLK), 613 and 623 are ALM
Signals (ALM), 614 and 624 are ACTST signals (A
CTST), 615 and 625 are BLKST signals (BLK
ST), 616 and 626 are ALMST signals (ALMS
T). In the present embodiment, as shown in FIG.
One processor to one monitored control device 21 (22,
.., 2m). The three processors are called a master processor 211 (221,..., 2m1), a sub-master processor 213 (223,..., 2m3), and a slave processor 212 (222,.

The sub-master processor 213 (223, 223)
, 2m3) and the slave processor 212 (222, 222,
, 2m2), the submaster processor 213 (2
, 2m3) to the slave processor 212 (2
, 2m2), a BLK signal (BLK) 621 indicating block control, a UBLK signal (UBLK) 622 indicating block release control, and an ALM signal (ALM) 623 indicating forced alarm control are prepared. ing. The slave processor 212 (222,..., 2)
m2) is the submaster processor 213 (223,..., 2)
As notification signals for notifying the state to m3), an ACTST signal (ACTST) 624 indicating a normal state, a BLKST signal (BLKST) 625 indicating a closed state, and an ALMST signal (ALMST) 626 indicating an abnormal state are prepared. Further, the master processor 211 (221,...,
2m1) to the submaster processor 213 (223, 223).
.., 2m3), a BLK signal (BLK) 611 representing block control and U representing block release control.
A BLK signal (UBLK) 612 and an ALM signal (ALM) 613 representing forced alarm control are prepared, and the sub master processor 213 (223,..., 2m3) notifies the master processor 211 (221,. An ACTST signal (ACTST) 614 indicating a normal state, a BLKST signal (BLKST) 615 indicating a closed state, and an ALMST signal (ALMST) 616 indicating an abnormal state are prepared as notification signals to be performed.

The master processor 211 (221,..., 2)
m1) and the submaster processor 213 (223,..., 2)
m3) and the sub-master processor 213 (223, 223)
, 2m3) and the slave processor 212 (222, 222,
, 2m2) are exchanged in the same manner as in the previous embodiment. Thereby, the master processor 211
(221,..., 2m1) are I / O ports 210 (22
0,..., 2m0) to the monitored control device 21 (22,.
m) can be prepared, and the control from the monitoring control processor 11 is controlled by the monitored control device 21 (22,..., 2).
m) all the processors {211, 212, 213}
({221, 222, 223}, ..., {2m1, 2m
2,2m3｝).

It should be noted that the present invention is not limited to the above embodiments, and it is clear that the embodiments can be appropriately modified within the scope of the technical idea of the present invention. Further, the number, position, shape, and the like of the constituent members are not limited to the above-described embodiment, and can be set to numbers, positions, shapes, and the like suitable for carrying out the present invention. In each drawing, the same components are denoted by the same reference numerals.

[0024]

Since the present invention is configured as described above, the following effects can be obtained. First, the first effect is that a dedicated signal line is provided between the master processor and the slave processor of the monitored control device, so that a state unified as the monitored control device can be monitored or controlled from the monitoring control processor. . The second effect is that since the monitoring control operation using polling and selecting is performed, bus arbitration in access using the common bus 3 can be omitted, and wiring between the monitoring control processor and the monitored control device can be reduced. It can be reduced. The third effect is that the load between the monitoring control processor and the plurality of monitored control devices can be reduced, and the processing speed can be increased.

[Brief description of the drawings]

FIG. 1 is a functional block diagram for explaining a multiprocessor supervisory control system according to a first embodiment of the present invention.

FIG. 2 is a functional block diagram for explaining one configuration of the monitored control device of FIG. 1;

FIG. 3 is a flowchart for explaining a multiprocessor supervisory control method according to the first embodiment of the present invention.

FIG. 4 is a functional block diagram for explaining another configuration of the monitored control device of FIG. 1;

FIG. 5 is a functional block diagram for explaining a conventional multiprocessor supervisory control system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Monitoring control part 3 ... Common bus 11 ... Monitoring control processor 21, 22, ..., 2m ... Monitored control device 210,220, ..., 2m0 ... I / O port 211,221, ..., 2m1 ... Master processor 212, , 2m2 ... slave processors 213, 223, ..., 2m3 ... submaster processors 41, 42, ..., 4m ... dedicated communication paths 53, 611, 621 ... BLK signals (BLK) 54, 612, 622 ... UBLK signals ( UBLK) 55,613,623 ... ALM signal (ALM) 56,614,624 ... ACTST signal (ACTST) 57,615,625 ... BLKST signal (BLKST) 58,616,626 ... ALMST signal (ALMST)

Claims (12)

[Claims] 1. A monitoring control processor for monitoring and controlling the state between a plurality of monitored control devices, and a multiprocessor monitoring and control system having a simple configuration with a small load on the monitored processor. A plurality of monitored control devices constituting one unit are connected to a single monitoring control processor via a common bus, and each of the plurality of monitored control devices is controlled by the monitoring control processor from a single monitored control device. A multiprocessor supervisory control system configured to be handled as a device. 2. The multiprocessor monitor according to claim 1, wherein the plurality of monitored control devices are configured as one monitored control device so as to perform monitoring control from the monitoring control processor. Control system. 3. The monitored control device, wherein one of the plurality of processors connected via a dedicated communication path is a master processor, and the plurality of status information is always supplied to the master processor via the dedicated communication line. The other processor is a slave processor, and the monitor control processor is configured to perform supervisory control as a single state obtained by logically synthesizing the states of the master processor and the slave processor. 2. The multiprocessor monitoring and control system according to 1. 4. The monitor processor according to claim 1, wherein the master processor has an I / O port for outputting a state of the monitored control device, which is generated by processing state information constantly supplied from the slave processor, to the monitor control processor. The multiprocessor supervisory control system according to claim 3, wherein 5. The monitored control processor writes a control command to the I / O port of the monitored control device, and writes the control command using the dedicated communication path between the processors. 5. The multiprocessor supervisory control system according to claim 4, wherein the system is configured to change states of the master processor and the slave processor. 6. The monitored control processor is configured to calculate a status of the monitored control device obtained by calculating a status of the master processor and the slave processor in the monitored control device. 5. The multiprocessor monitoring and control system according to claim 4, wherein the monitoring is performed by reading an I / O port. 7. A monitoring and control processor for monitoring and controlling a state between a plurality of monitored control devices and a multiprocessor monitoring and control method having a simple configuration with a small load on the monitored processor. Connecting a plurality of monitored control devices constituting one unit to a single monitoring control processor via a common bus, and from the monitoring control processor, each of the plurality of monitored control devices is controlled by a single monitored A method for monitoring and controlling a multiprocessor, comprising a step of handling as a control device. 8. The multiprocessor supervisory control method according to claim 7, further comprising a step of performing supervisory control from said supervisory control processor between said plurality of supervisory control devices as one supervisory control device. 9. The monitored control device, wherein one of a plurality of processors in the monitored control device connected by a dedicated communication path is used as a master processor, and status information is always sent to the master processor via the dedicated communication line. And a step of performing monitoring control from the monitoring control processor as a single state obtained by logically synthesizing the states of the master processor and the slave processor. The method for monitoring and controlling a multiprocessor according to claim 7, wherein 10. The master processor outputs a status of the monitored control device, which is generated by processing status information constantly supplied from the slave processor, to the monitoring control processor via an I / O port. The method according to claim 9, wherein: 11. The monitored control processor writes a control command to the I / O port of the monitored control device, and writes the control command using the dedicated communication path between the processors in the monitored control device. The method according to claim 10, further comprising a step of changing states of a master processor and the slave processor. 12. A status as the monitored control device obtained by calculating a status of the master processor and the slave processor in the monitored control device, monitors the I / O port of the monitored control device. 11. The multiprocessor monitoring and control method according to claim 10, further comprising a step of monitoring by reading by a control processor.