JP2000305109A - Manufacture of electrooptical device and electrooptical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress lowering of a production yield due to flattening treatment by facilitating flattening of pixel electrodes in an electrooptical device such as a liquid crystal device. SOLUTION: A thin film transistor(TFT) 30 is formed on a TFT array substrate 10. A dense insulating film is formed on its upper side by high temperature sintering treatment at >=700 deg.C and subsequently it is flattened by polishing treatment to form a first interlayer insulating film 4. A data line 6a is formed thereon so as to be connected with a source of the TFT via a contact hole 5. The data line is formed with a low-melting metal with an excellent time constant. Furthermore, a second interlayer insulating film 7 is formed on it and a pixel electrode 9a is formed thereon so as to be connected with a drain of the TFT via a contact hole 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an electro-optical device and a technical field of the electro-optical device, and more particularly, to a method of manufacturing a thin film transistor between a substrate and a pixel electrode.
sistor: hereinafter, appropriately referred to as TFT), thin-film diode (T
An electro-optic type in which pixel switching elements such as hin film diodes (hereinafter, appropriately referred to as TFDs) and wirings such as data lines, scanning lines, and capacitance lines connected thereto are stacked via an interlayer insulating film. It belongs to the technical field of the device manufacturing method and the electro-optical device.

[0002]

2. Description of the Related Art Conventionally, in this type of electro-optical device, an electro-optical material such as a liquid crystal is sandwiched between a pair of substrates, and one substrate is provided with a plurality of pixel electrodes in a matrix.
Here, if there is a step or unevenness on the surface of the pixel electrode, a display defect due to a liquid crystal alignment defect or the like is caused. More specifically,
Such steps and irregularities become steps and irregularities on the surface of the alignment film provided on the pixel electrode surface, causing uneven rubbing at the time of the rubbing treatment, and causing poor alignment of the liquid crystal defined by the rubbing treatment. Eventually, the image display quality is degraded. Usually, in order to minimize rubbing unevenness due to such steps and unevenness, rubbing processing is performed along the largest step (for example, a step along the data line) determined depending on the device configuration in the pixel portion. Is done. However, when the rubbing process is performed in this manner, especially in the case of a double-plate type color projector using three electro-optical devices in combination as three light valves, three light valves are used to combine three lights. Because one of the light valves is used in reverse, the color unevenness due to the rubbing unevenness that is invisible to a single light valve is increased by combining the three light valves, and the visible color is increased. This leads to an uneven situation.

For this reason, it is preferable to planarize the surface of the uppermost interlayer insulating film, which serves as a base film for a pixel electrode, on one substrate. That is, if the uppermost interlayer insulating film is planarized, rubbing unevenness can be basically reduced. Further, also in the case of the above-mentioned double-plate type color projector, a rubbing direction in which the same tendency of rubbing unevenness is selected between one light valve used in reverse and two other light valves is selected. Because of this, it is also possible to suppress the above-described effect of increasing display unevenness during photosynthesis.
In addition, if an alignment film having no steps is provided, good vertical alignment is possible, which leads to high-contrast display.

Therefore, conventionally, the surface of the uppermost interlayer insulating film is formed from a flattening film obtained by spin-coating an organic film such as an organic SOG (Spin On Glass) or an organic polyimide film.

[0005]

However, in the case of flattening by the technique of spin coating an organic film, there is a fundamental problem that the organic film is significantly deteriorated by light during use of the apparatus. In particular, in the case of a projector application using strong light, this problem becomes very serious.

[0006] Therefore, CMP (Chemical Mechanical Polishing) used in the technical field of semiconductor manufacturing equipment and the like.
g) It is conceivable to apply a polishing technique such as processing to planarize an interlayer insulating film in this type of electro-optical device.

However, when the interlayer insulating film in this type of electro-optical device is polished by a CMP process or the like, cracks occur in the interlayer insulating film during polishing, and the defective product rate increases. is there. Further, since the polishing amount is different between the vicinity of the center and the periphery of the mother substrate, it is difficult to perform uniform film thickness control, and it is finally difficult to manufacture a device of a constant quality. There are points. In particular, in the case of a high-definition electro-optical device, the driving frequency becomes extremely high and the wiring pitch becomes fine. Therefore, a data line for supplying an image signal is generally made of Al ( Aluminum) film. However, since Al is a low melting point metal, heat treatment at 500 ° C. or higher cannot be performed after the formation of the data line. Therefore, a dense interlayer insulating film sufficiently subjected to thermal firing at a higher temperature cannot be generally formed. As a result, since it is inevitable to polish the non-dense interlayer insulating film, cracks occur during the above polishing,
Deterioration of reliability and difficulty in uniform film thickness control are very serious problems in practical use.

The present invention has been made in view of the above-described problems, and has high quality images capable of relatively easily flattening a pixel electrode and suppressing a reduction in manufacturing yield due to the flattening process. It is an object to provide a method for manufacturing an electro-optical device capable of displaying and an electro-optical device manufactured by the method.

[0009]

According to a first aspect of the invention, there is provided a method of manufacturing an electro-optical device, comprising the steps of: forming a pixel switching element on a substrate; Forming one interlayer insulating film, flattening the one interlayer insulating film, and forming the pixel switching element through the one contact hole on the flattened one interlayer insulating film. Forming a data line so as to be connected to one terminal, forming another interlayer insulating film on the data line, and switching the pixel via another contact hole on the other interlayer insulating film. Forming a pixel electrode so as to be connected to another terminal of the device.

According to the method of manufacturing an electro-optical device of the present invention, first, a pixel switching element such as a TFT element or a TFD element is formed on a substrate, and an interlayer is provided above the pixel switching element. An insulating film is formed.
Therefore, at this point, a step is formed on the surface of the one interlayer insulating film due to the pixel switching element and its wiring existing between the substrate and the one interlayer insulating film. Subsequently, one interlayer insulating film is planarized. Next, a data line is formed on one planarized interlayer insulating film so as to be connected to one terminal (for example, a source in a TFT) of the pixel switching element via one contact hole. .
Next, another interlayer insulating film is formed on the data line. Finally, a pixel electrode is formed on another interlayer insulating film formed in this way so as to be connected to another terminal (for example, a drain in a TFT) of the pixel switching element via another contact hole. You.

As described above, even when a data line is formed from a low melting point metal such as Al (although it has an excellent time constant) after flattening one interlayer insulating film, the one interlayer insulating film may have On the other hand, heat treatment can be performed regardless of the melting point of the material forming the data line. That is, it is possible to form one dense interlayer insulating film by thermal baking performed before forming the data lines. As a result, even if a single dense interlayer insulating film is flattened by polishing or the like, the possibility of cracks being generated by polishing or the like is reduced, and finally the yield of non-defective devices can be improved. In addition, since the dense one interlayer insulating film is flattened, the difference in the amount of polishing between the vicinity of the center and the periphery of the mother substrate is reduced, and the thickness of the one interlayer insulating film after the flattening is reduced. Can be homogenized within.

As a result, according to the method of manufacturing an electro-optical device of the present invention, a pixel electrode can be relatively easily flattened, and a material having an excellent time constant can be used for a high-definition electro-optical device. It is possible to suppress a decrease in manufacturing yield due to the planarization process while using the data line. As a result, it is possible to manufacture an electro-optical device capable of displaying a particularly high-definition image using the pixel electrode having almost no step.

In one aspect of the method of manufacturing an electro-optical device according to the present invention, the step of flattening includes a step of flattening by a polishing process.

According to this aspect, one interlayer insulating film is flattened by the polishing process. In this case, particularly, even if one dense interlayer insulating film that can be formed by thermal baking performed before forming the data line is flattened by the polishing process, the possibility that cracks are generated by the polishing is reduced. In addition, since one dense interlayer insulating film is flattened by polishing,
The difference in the amount of polishing between the vicinity of the center and the periphery of the mother substrate is also reduced.

In this embodiment, the polishing process is performed by CMP (Chem).
ical Mechanical Polishing) processing.

In this case, in particular, even if one dense interlayer insulating film that can be formed by thermal baking is flattened by the CMP process, the possibility of cracking is reduced.

In another aspect of the method for manufacturing an electro-optical device according to the present invention, the one interlayer insulating film is made of a silicon oxide film.

According to this aspect, it is possible to form one dense interlayer insulating film by performing thermal baking on the one interlayer insulating film made of the silicon oxide film. Further, the one interlayer insulating film made of a silicon oxide film can be satisfactorily planarized while reducing the occurrence of cracks due to polishing or the like.

In this aspect, the step of forming the one interlayer insulating film may include a step of forming the silicon oxide film using TEOS (tetraethoxyorthosilicate) as a raw material.

Thus, one interlayer insulating film composed of a silicon oxide film is formed using TEOS as a raw material.
If TEOS is used as a raw material, it becomes possible to stack one interlayer insulating film, which becomes dense by performing thermal firing, very thickly. For this reason, even if the step caused by the presence of the pixel switching element and the like is relatively large, it is possible to sufficiently planarize using the one interlayer insulating film.

In another aspect of the method of manufacturing an electro-optical device according to the present invention, the step of forming the one interlayer insulating film and the step of flattening the first interlayer insulating film by 700
The method further includes a step of performing a heat treatment at a temperature of not less than ° C.

According to this aspect, after forming one interlayer insulating film made of a silicon oxide film using TEOS as a raw material, the one interlayer insulating film is subjected to a heat treatment at 700 ° C. or higher. That is, a very dense film can be obtained by subjecting a silicon oxide film made of TEOS to thermal baking at 700 ° C. or higher. Further, since the data line is formed after the heat treatment and the planarization, there is no problem even if the data line is formed from a material that is melted by the heat treatment at 700 ° C. or more.

In another aspect of the method of manufacturing an electro-optical device according to the present invention, the method further includes a step of forming a non-light-transmitting film which covers the data line at least partially in plan view.

According to this aspect, the non-light-transmitting film that covers the data line at least partially as viewed in plan is formed. Such a non-light-transmitting film is formed between the substrate and the pixel switching element, between the pixel switching element and one interlayer insulating film, between one interlayer insulating film and another in the laminated structure of the electro-optical device. It may be formed between an interlayer insulating film and a counter substrate facing the substrate. Due to the non-light-transmitting film formed in this way, due to a step caused by the presence or absence of the data line formed on one interlayer insulating film, a display defect portion such as light leakage in an image display area along the data line, It can be hidden by the non-light transmitting film. As a result, a high-contrast image can be displayed.

In this aspect of forming the non-light-transmitting film, between the step of forming the pixel switching element and the step of forming the pixel electrode, the step of forming the non-light-transmitting film is performed simultaneously with the step of forming the non-light-transmitting film. The method may further include forming a conductive film for connecting the pixel electrode and another terminal of the pixel switching element from the same film as the non-light-transmitting film.

According to this structure, simultaneously with the step of forming the non-light-transmitting film and from the same film as the non-light-transmitting film, the other terminals of the pixel electrode and the pixel switching element (for example,
A conductive film for connecting to the drain of the TFT is formed. That is, the conductive film allows the pixel electrode and the other terminal of the pixel switching element to be relayed, so that the contact hole can be easily opened and the contact can be easily made, compared to a case where both are directly connected by a deep contact hole. The diameter of the hole can be reduced. Therefore, even when one interlayer insulating film to be planarized is thickly deposited, the opening of the contact hole does not pose a problem.

In the aspect of forming the non-light-transmitting film, at the same time as the step of forming the non-light-transmitting film and from the same film as the non-light-transmitting film, at least a channel region of the thin film transistor constituting the pixel switching element and The method may further include a step of forming a light-shielding film that covers the junction between the channel region and the drain region in plan view.

According to this structure, at least the channel region of the thin film transistor constituting the pixel switching element and the channel region and the drain region are formed simultaneously with the step of forming the non-light-transmitting film and from the same film as the non-light-transmitting film. A light-shielding film is formed to cover the joint portion of FIG. That is, the light-shielding film can prevent a leak current due to light of the thin film transistor due to a photoelectric effect in the channel region and the junction.

In this aspect of forming the non-light-transmitting film, in the step of forming the non-light-transmitting film, the non-light-transmitting film and the pixel electrode overlap each other at least partially in plan view. A light transmitting film may be formed.

With this configuration, the non-light-transmitting film and the pixel electrode overlap at least partially in plan view, and the overlapping non-light-transmitting film at least partially defines the contour of the opening region of each pixel. Can be specified.

In this case, in particular, in the step of forming the data line and the step of forming the pixel electrode, the data line and the pixel electrode are formed so that the data line and the pixel electrode do not overlap at least partially in plan view. The pixel electrode may be formed.

In this case, since the data line and the pixel electrode do not at least partially overlap in a plan view, the data line and the pixel electrode are generated by opposing each other via another interlayer insulating film. Parasitic capacitance (for example, parasitic capacitance between a source and a drain in a TFT) can be extremely reduced. As a result, image quality can be improved by preventing the occurrence of ghosts and unevenness.

In another aspect of the method of manufacturing an electro-optical device according to the present invention, the one contact hole is opened and the data line is simultaneously connected between the flattening step and the data line forming step. The method further includes the step of opening a hole portion serving as an alignment mark when forming.

According to this aspect, when one contact hole is opened in one planarized interlayer insulating film, an opening part serving as an alignment mark for forming a data line is also opened at the same time. Drilled. That is, an alignment mark is opened in one of the planarized interlayer insulating films, and when the Al film or the like is formed on the entire surface, a depression is formed in the Al film or the like corresponding to the alignment mark.
Using this as a positioning reference, a data line can be formed.

In another aspect of the method of manufacturing an electro-optical device according to the present invention, the thickness of the data line is substantially equal to the thickness of the pixel electrode.

According to this aspect, since the thickness of the data line and the thickness of the pixel electrode can be substantially offset, the surface of the alignment film can be made substantially flat.

In order to solve the above problems, an electro-optical device according to the present invention includes a pixel switching element on a substrate, an interlayer insulating film formed above the pixel switching element and flattened, A data line formed on the one interlayer insulating film and connected to one terminal of the pixel switching element via one contact hole; another interlayer insulating film formed on the data line; A pixel electrode formed on another interlayer insulating film and connected to another terminal of the pixel switching element via another contact hole.

According to the electro-optical device of the present invention, the one interlayer insulating film is formed above the pixel switching element and is flattened. The data line is formed on one interlayer insulating film, and is connected to one terminal of the pixel switching element via one contact hole. The pixel electrode is formed on another interlayer insulating film, and is connected to another terminal of the pixel switching element via another contact hole.

Therefore, the electro-optical device of the present invention can be suitably manufactured by the above-described method of manufacturing an electro-optical device of the present invention, has relatively low cost, has high device reliability, and has particularly high image quality. Display becomes possible.

The operation and other advantages of the present invention will become more apparent from the embodiments explained below.

[0041]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) The structure of an electro-optical device according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming an image display area of the electro-optical device. FIG. 2 is a diagram illustrating data lines, scanning lines, pixel electrodes, and the like. FIG. 3 is a cross-sectional view taken along line AA ′ of FIG. 2 and FIG. 4 is a cross-sectional view taken along line BB ′ of FIG. 2. . In FIGS. 3 and 4, the scale of each layer and each member is made different so that each layer and each member have a size recognizable in the drawings.

In FIG. 1, a plurality of pixels formed in a matrix forming an image display area of the electro-optical device according to the present embodiment include a pixel electrode 9a and a TFT 30 for controlling the pixel electrode 9a in a matrix. A plurality of data lines 6a to which image signals are supplied are connected to the T
It is electrically connected to the source of FT30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. good. The scanning line 3a is connected to the gate of the TFT 30.
Are electrically connected to each other, and at predetermined timing, the scanning signals G1, G2,...
It is configured to apply in this order in a line-sequential manner. The pixel electrode 9a is electrically connected to the drain of the TFT 30. By closing the switch of the TFT 30, which is a switching element, for a certain period, the image signals S1, S2,... Write at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal as an example of the electro-optical material via the pixel electrode 9a are transmitted between the counter electrode (described later) formed on the counter substrate (described later). For a certain period. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gray scale display. In the normally white mode,
According to the applied voltage, the incident light cannot pass through the liquid crystal portion. In the normally black mode, the incident light can pass through the liquid crystal portion according to the applied voltage. Light having a contrast corresponding to the image signal is emitted from the optical device. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added between the capacitor line 3b and the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode in parallel.

In FIG. 2, a plurality of transparent pixel electrodes 9 are arranged in a matrix on a TFT array substrate of an electro-optical device.
a (the outline is indicated by a dotted line portion 9a '), and the data line 6a, the scanning line 3a, and the capacitor line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a. The data line 6a is electrically connected to a source region described later in the semiconductor layer 1a made of, for example, a polysilicon film via the contact hole 5. The pixel electrode 9a is electrically connected to a drain region described later in the semiconductor layer 1a via the contact hole 8. In addition, the channel region 1 of the semiconductor layer 1a, which is indicated by a hatched region falling rightward in FIG.
The scanning line 3a is arranged so as to face a ′, and the scanning line 3a functions as a gate electrode. As described above, pixel switching TFTs 30 in which the scanning lines 3a are opposed to each other as gate electrodes in the channel region 1a 'are provided at intersections of the scanning lines 3a and the data lines 6a.

The capacitance line 3b has a main line extending substantially linearly along the scanning line 3a, and a protruding portion protruding upward in the figure along the data line 6a from a position intersecting the data line 6a.

Next, as shown in the cross-sectional view of FIG. 3, the electro-optical device includes a TFT array substrate 10 which constitutes an example of one transparent substrate and an example of another transparent substrate which is arranged to face the TFT array substrate. And the opposing substrate 20 that constitutes it. TFT
The array substrate 10 is made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is made of, for example, a glass substrate or a quartz substrate. A pixel electrode 9a is provided on the TFT array substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrode 9a. The pixel electrode 9a is made of, for example, ITO (Indium Tin O
xide) A transparent conductive thin film such as a film. Also, alignment film 1
6 is made of, for example, an organic thin film such as a polyimide thin film.

On the other hand, a counter electrode (common electrode) 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode. Is provided. The counter electrode 21 is, for example, I
It is made of a transparent conductive thin film such as a TO film. Also, the alignment film 22
Consists of an organic thin film such as a polyimide thin film.

Each pixel electrode 9 is provided on the TFT array substrate 10.
A pixel switching TFT 30 that performs switching control of each pixel electrode 9a is provided at a position adjacent to the pixel electrode 9a.

As shown in FIG. 3, the opposing substrate 20 is further provided with a second light-shielding film 23 generally called a black mask or a black matrix in a non-opening region of each pixel. Therefore, incident light does not enter the channel region 1a 'of the semiconductor layer 1a of the pixel switching TFT 30 from the side of the counter substrate 20. Further, the second light-shielding film 23 has a function of improving contrast, preventing color mixture of color materials when a color filter is formed, and the like.

The space between the TFT array substrate 10 and the opposing substrate 20 having the above-described structure, in which the pixel electrode 9a and the opposing electrode 21 face each other, is provided in a space surrounded by a sealing material described later. A liquid crystal, which is an example of an optical material, is sealed, and a liquid crystal layer 50 is formed. The liquid crystal layer 50 has the alignment film 16 in a state where no electric field is applied from the pixel electrode 9a.
A predetermined orientation state is obtained by means of and. The liquid crystal layer 50
For example, it is composed of a liquid crystal in which one or several kinds of nematic liquid crystals are mixed. The sealing material is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the TFT array substrate 10 and the counter substrate 20 around them,
A gap material (spacer) such as glass fiber or glass beads is mixed to make the distance between the two substrates a predetermined value.

Further, a base insulating film 12 is provided between the TFT array substrate 10 and the plurality of pixel switching TFTs 30.
Is provided. The base insulating film 12 is formed on the entire surface of the TFT array substrate 10 to prevent deterioration of the characteristics of the pixel switching TFT 30 due to roughening of the surface of the TFT array substrate 10 during polishing, dirt remaining after cleaning, and the like. Having. The base insulating film 12 is made of, for example, NS.
It is made of a highly insulating glass such as G (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorous silicate glass), a silicon oxide film, a silicon nitride film, or the like.

In this embodiment, the semiconductor layer 1a extends from the high-concentration drain region 1e to form a first storage capacitor electrode 1f, and a part of the capacitor line 3b opposed to the first storage capacitor electrode 1f serves as a second storage capacitor electrode. The insulating thin film 2 including the film is connected to the scanning line 3a.
The storage capacitor 70 is formed by extending from a position facing the first dielectric film and forming a first dielectric film sandwiched between these electrodes.

In FIG. 3, the pixel switching TFT
Reference numeral 30 denotes an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a and a channel region 1 of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a.
a ', an insulating thin film 2 including a gate insulating film for insulating the scanning line 3a from the semiconductor layer 1a, a data line 6a, a low-concentration source region 1b and a low-concentration drain region 1c of the semiconductor layer 1a, and a high-concentration source of the semiconductor layer 1a. A region 1d and a high-concentration drain region 1e are provided. A corresponding one of the plurality of pixel electrodes 9a is connected to the high-concentration drain region 1e via the contact hole 8. Also, scanning line 3
A first interlayer insulating film 4 having a contact hole 5 leading to the high-concentration source region 1d and a contact hole 8 leading to the high-concentration drain region 1e is formed on the capacitor line 3a and the capacitor line 3b. Further, the data line 6a and the first
On the interlayer insulating film 4, a second interlayer insulating film 7 in which a contact hole 8 to the high-concentration drain region 1e is formed. The above-described pixel electrode 9a is provided on the upper surface of the second interlayer insulating film 7 configured as described above.

As shown in FIG. 4, a data line 6a is provided in a non-opening region of each pixel located in a gap between pixel electrodes 9a adjacent to each other on the left and right in FIG. A portion along the data line 6a in the outline of the opening region is defined, and light leakage in the non-opening region is prevented by the data line 6a. In addition, a storage capacitor 70 is formed below the data line 6a, and the non-opening area is effectively used.

In this embodiment, in particular, as shown in FIGS. 3 and 4, the upper surface of the first interlayer insulating film 4 is flattened, and the TFTs 30 located below the first interlayer insulating film 4
It is configured to absorb a step on the base surface of the first interlayer insulating film 4 due to the presence of the storage capacitor 70, the scanning line 3a, and the capacitor line 3b. That is, the first interlayer insulating film 4 is first piled up to a thickness equal to or more than the step of the base surface in a later-described manufacturing process, and is polished by a polishing process such as a CMP method after a thermal baking process. Polished until
Furthermore, the surface is formed to be almost completely flat by being polished to such a thickness that the scanning lines 3a and the capacitance lines 3b are not exposed. A data line 6a is formed on the thus planarized first interlayer insulating film 4 so as to be connected to the high-concentration source region 1d of the TFT 30 via the contact hole 5.

In particular, in such a manufacturing process, after the first interlayer insulating film 4 is planarized, the first interlayer insulating film 4 has no relation to the melting point of Al which is a low melting point metal constituting the data line 6a. Is subjected to a heat treatment (thermal baking) at 700 ° C. or higher, so that the first interlayer insulating film 4 is formed as a dense insulating film. As a result, when the first interlayer insulating film 4 is flattened by the polishing treatment, the possibility of cracks is reduced, and a high device non-defective rate is finally realized.
Further, since the dense first interlayer insulating film 4 is flattened, the difference in the amount of polishing between the vicinity of the center and the vicinity of the periphery of the mother substrate is reduced, and the film of the first interlayer insulating film 4 after the flattening is formed. The thickness is made uniform within the mother substrate surface.

As a result, according to the present embodiment, the data line 6a is made of a low melting point metal material such as Al having an excellent time constant, but is subjected to a high-temperature thermal sintering process irrespective of the melting point. As a result, a reduction in the manufacturing yield due to the planarization process in the densified first interlayer insulating film 4 is suppressed, and a low-cost and high-definition electro-optical device is finally realized.

Further, since the first interlayer insulating film 4 is flattened as described above and the alignment film 16 formed on the pixel electrode 9a having almost no level difference may be subjected to the rubbing treatment, the rubbing direction is set at the level difference. There is no need to be restricted by direction. For this reason, in particular, TN (Twisted Ne
matic) When a liquid crystal is used, the direction of the data line 6a (FIG. 2)
Rubbing in a direction of 45 degrees with respect to the vertical direction (in the vertical direction), so that even in the above-described double-plate type color projector, one light valve used in reverse and two other light valves are used. Since the clear visual direction can be made the same, it is also possible to prevent a situation where color unevenness is increased by combining three light valves. In addition, an electro-optical device having such a configuration is referred to as a VA (Vertically Alig
If the present invention is applied to a liquid crystal device of the ned) mode, a highly accurate vertical alignment can be obtained by the pixel electrode 9a having almost no step.

In the first embodiment described above, the pixel switching TFT 30 preferably has an LDD structure as shown in FIG. 3, but implants impurity ions into the low-concentration source region 1b and the low-concentration drain region 1c. It may have an offset structure which is not performed, or a self-aligned TFT in which impurity ions are implanted at a high concentration using a gate electrode formed of a part of the scanning line 3a as a mask to form a high concentration source and drain region in a self-aligned manner. There may be. In this embodiment, the pixel switching TFT 3
Although only one gate electrode is disposed between the high-concentration source region 1d and the high-concentration drain region 1e, two or more gate electrodes may be disposed between them. When a TFT is formed with a dual gate or a triple gate or more as described above, a leak current at a junction between a channel and a source / drain region can be prevented, and a current in an off state can be reduced.

In this embodiment, each contact hole (8
The planar shape of (5) may be circular, square, or other polygonal shapes. The circular shape is particularly useful for preventing cracks in the interlayer insulating film around the contact hole. Then, in order to obtain a good electrical connection, it is preferable that wet etching is performed after dry etching to slightly taper each of these contact holes.

(Manufacturing Process of First Embodiment) Next, a manufacturing process of the TFT array substrate constituting the electro-optical device according to the first embodiment having the above configuration will be described with reference to FIG. . FIG. 5 shows each layer on the TFT array substrate side in each step, as in FIG.
It is a process drawing shown corresponding to -A 'cross section.

First, as shown in step (a) of FIG. 5, a TFT is formed on a TFT array substrate 10 by using a thin film forming technique.
30 and a storage capacitor 70 are formed.

More specifically, first, a TFT array substrate 10 such as a quartz substrate, a hard glass substrate, or a silicon substrate is prepared, and a TEOS gas, a TEB (Tetra. NSG, PSG, BSG, B using Ethyl boat rate) gas, TMOP (Tetra methyl oxy phosphate) gas, etc.
It is composed of a silicate glass film such as PSG, a silicon nitride film, a silicon oxide film, etc., and has a thickness of about 500 to 2000 n.
The underlying insulating film 12 of m is formed. Next, the base insulating film 12
An amorphous silicon film is formed thereon by low-pressure CVD or the like, and an annealing process is performed thereon, so that a polysilicon film is grown in a solid phase. Alternatively, a polysilicon film is directly formed by a low pressure CVD method or the like without passing through the amorphous silicon film. Next, by performing a photolithography process, an etching process, and the like on the polysilicon film,
A semiconductor layer 1a having a predetermined pattern including the first storage capacitor electrode 1f as shown in FIG. 2 is formed. Next, an insulating thin film 2 including a first dielectric film for forming a storage capacitor is formed together with the gate insulating film of the TFT 30 by thermal oxidation or the like. As a result, the thickness of the semiconductor layer 1a is about 30 to 150
nm, preferably about 35-50 nm, and the thickness of the insulating thin film 2 is about 20-150 nm,
Preferably, it has a thickness of about 30 to 100 nm. Next, the polysilicon film is formed to a thickness of about 100 to 500
After the polysilicon film is made conductive by thermally diffusing P (phosphorus) by P (phosphorus), a scanning line 3a having a predetermined pattern as shown in FIG. And the capacitance line 3b. still,
The scanning line 3a and the capacitance line 3b may be formed of a metal alloy film such as a high melting point metal or a metal silicide, or may be a multilayer wiring combined with a polysilicon film or the like. Next, by doping impurity ions in two steps of low concentration and high concentration, the low concentration source region 1b and the low concentration drain region 1c, the high concentration source region 1d and the high concentration
e, LDD-structured pixel switching TFT 30
To form

In parallel with the step (a) in FIG.
Peripheral circuits, such as a data line driving circuit and a scanning line driving circuit, which are formed from the TFT array substrate 10, may be formed in the peripheral portion.

Next, as shown in a step (b) of FIG. 5, for example, the stepped upper surface of the stacked body composed of the scanning lines 3a, the capacitor lines 3b, the insulating thin film 2, and the base insulating film 12 is usually covered, for example. Using a high pressure or low pressure CVD method or a TEOS gas, an interlayer insulating film 4 ′ made of a silicate glass film such as NSG, PSG, BSG, BPSG, etc., a silicon nitride film, a silicon oxide film, etc. 4) is formed. Subsequently, for the interlayer insulating film 4 ',
Thermal firing is performed at a temperature of 700 ° C. or more. The thickness of the interlayer insulating film 4 'is set to a thickness sufficient to absorb such a step on the upper surface of the stacked body. In the present embodiment, in particular, 700 ° C.
By performing the above-described thermal sintering, a high-quality insulating film that is dense and does not easily crack in the subsequent polishing treatment can be obtained even with a relatively thick insulating film of about 2000 nm. Note that, in parallel with or before or after this thermal baking, an annealing process at about 1000 ° C. may be performed to activate the semiconductor layer 1a.

Next, as shown in step (c) of FIG. 5, the interlayer insulating film 4 'is flattened by a polishing process such as a CMP method.
Specifically, for example, a liquid slurry (chemical polishing liquid) containing silica particles is allowed to flow on a polishing pad fixed on a polishing plate, and the surface of the substrate fixed on the spindle (on the side of the interlayer insulating film 4 ') Is polished to make the surface of the interlayer insulating film 4 'by rotating contact. Before the scanning lines 3a and the capacitance lines 3b are exposed, the polishing process is stopped (stopped) by time management or by forming an appropriate stopper layer at a predetermined position on the TFT array substrate 10. As a result, the first interlayer insulating film 4 having a thickness of about 500 to 1500 nm and having a flat upper surface is completed.

Next, as shown in step (d) of FIG. 5, a contact hole 5 for electrically connecting the data line 6a and the high-concentration source region 1d of the semiconductor layer 1a is polished by a first interlayer insulating film. A hole is formed in the film 4 and the insulating thin film 2.
Also, contact holes for connecting the scanning lines 3a and the capacitance lines 3b to wirings (not shown) in the peripheral region of the substrate are provided.
The hole can be opened by the same process as the contact hole 5. Subsequently, a low-resistance metal film such as Al or a metal silicide film is deposited to a thickness of about 100 to 500 nm on the first interlayer insulating film 4 by a sputtering process or the like, and then a photolithography process, an etching process, and the like are performed. The data lines 6a having a predetermined pattern are formed.

Next, as shown in step (e) of FIG. 5, a second interlayer insulating film 7 is formed on the data line 6a, and the pixel electrode 9 is formed.
A contact hole 8 for electrically connecting a to the high-concentration drain region 1e is formed by dry etching such as reactive ion etching, reactive ion beam etching, or wet etching. Subsequently, a transparent conductive thin film such as an ITO film is deposited on the second interlayer insulating film 7 to a thickness of about 50 to 200 nm by a sputtering process or the like, and furthermore, a pixel is formed by a photolithography process and an etching process. An electrode 9a is formed. When the electro-optical device is used as a reflection type, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.

As described above, according to the manufacturing method of this embodiment, after the first interlayer insulating film 4 is flattened, the data lines 6a
Is formed by thermally sintering the first interlayer insulating film 4 at a high temperature that is independent of the melting point of Al or the like, which is a material of the data line 6a and has an excellent time constant, despite being a low melting point metal. Can be sufficiently applied. That is, the dense first interlayer insulating film 4 can be formed by the thermal baking in the step (b) performed before the step (d) for forming the data line 6a. As a result, in step (c),
Even if the first interlayer insulating film 4 is polished, the possibility of occurrence of cracks is reduced, and finally the yield of non-defective devices can be improved.
Further, since the dense first interlayer insulating film 4 is flattened, the difference in the amount of polishing between the vicinity of the center and the periphery of the mother substrate is reduced, and the thickness of the first interlayer insulating film 4 after the flattening is reduced. It can be made uniform within the plane of the substrate. Further, the first interlayer insulating film 4 is
Since it can be formed with a dense film with few defects, it does not penetrate moisture generated at the time of the polishing treatment and deteriorates the characteristics of the TFT 30 and the like, so that high reliability can be realized. In particular, according to the present manufacturing method, a polishing process such as a CMP method may be performed as the flattening process, so that cost increase due to an increase in the number of processes is hardly caused as compared with the conventional manufacturing method.

In the manufacturing method of the present embodiment described above, it is particularly preferable that the second interlayer insulating film is formed of a silicon oxide film. By forming in this manner, it is possible to form a dense first interlayer insulating film 4 by performing thermal baking on the interlayer insulating film 4 ′ made of a silicon oxide film. Further, it is more preferable to form such a silicon oxide film using TEOS as a raw material. Thus TE
If an interlayer insulating film 4 'made of a silicon oxide film is formed using OS as a raw material, the interlayer insulating film 4' which becomes dense by thermal baking becomes very thick (for example, 2000
(up to about nm). Therefore, TF
Even if the step caused by the existence of T30 or the like is large (for example,
Even if the thickness is 1000 nm or more), it is possible to sufficiently planarize using the interlayer insulating film 4 ′ in the steps (b) and (c) of FIG. In particular, if the interlayer insulating film 4 ′ is thickly stacked in the step (b) as described above, the interlayer insulating film 4 ′ can be formed even if a method of stopping the planarization process such as the CMP process in the step (c) by time management is adopted. The possibility of penetration through excessive polishing can also be reduced. In addition, TE
When forming an interlayer insulating film 4 'made of a silicon oxide film using OS as a raw material, a very good insulating film which is very dense and hard to crack by a polishing process can be obtained by performing thermal firing at 700 ° C. or more. Can be done.

In the manufacturing method of the present embodiment described above,
In step (d) of FIG. 5, a contact hole 5 is formed before forming the data line 6a, and an opening portion serving as an alignment mark for forming the data line 6a is formed by TF.
It is preferable to open holes at predetermined positions on the T array substrate 10. However, when an Al thin film or the like is formed on the entire surface of the flattened first interlayer insulating film 4 by sputtering or the like, the Al thin film or the like is non-light-transmitting and has a flat surface. It becomes impossible to determine the positional relationship between the data line 6a and the wiring or the like located below the line. However, if an alignment mark (opening portion) is opened at a predetermined position of the second interlayer insulating film 4 thus flattened, Al
When the thin film or the like is formed on the entire surface, a depression is formed in the Al thin film or the like corresponding to the alignment mark. As a result, the data line 6a can be formed using the depression as a positioning reference, which is convenient. Moreover, if such an alignment mark is opened simultaneously with the contact hole 5, an opening step dedicated to the alignment mark is not required, which is extremely advantageous in the manufacturing process.

(Second Embodiment) The configuration of an electro-optical device according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 6 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed. FIG. FIG. 8 is a sectional view taken along line DD ′ of FIG. Note that FIG.
In FIG. 8 and in FIG. 8, the scale of each layer and each member is made different in order to make each layer and each member a recognizable size in the drawing. In the second embodiment shown in FIGS. 6 to 8, the same components as those in the first embodiment shown in FIGS. 2 to 4 are denoted by the same reference numerals, and the description thereof will be omitted.

The second embodiment differs from the first embodiment in the following points, and the other configuration is the same as that of the first embodiment.

That is, as shown in FIG. 6 and FIG. 7, a region along the scanning line 3a (a region shown by a coarse oblique line falling rightward in FIG. 6) in the gap between the vertically adjacent pixel electrodes 9a respectively. , Island-shaped conductive layer (hereinafter referred to as first barrier layer) 8
0a is provided, and the pixel electrode 9a is electrically connected to the high-concentration drain region 1e via the contact holes 8a and 8b via the first barrier layer 80a. Further, as shown in FIGS. 6 and 8, a region along the data line 6 a (a region indicated by a coarse diagonal line falling to the right in FIG. 6) in the gap between the pixel electrodes 9 a adjacent to each other on the left and right sides respectively corresponds to the second region.
A barrier layer 80b is provided, and the second barrier layer 80b
And the capacitor line 3b are connected via a contact hole 8c.

As shown in FIGS. 6 to 8, in the second embodiment, the capacitance line 3 opposing the first storage capacitance electrode 1f is used.
b is a second storage capacitor electrode, and the insulating thin film 2 including the gate insulating film is extended from a position facing the scanning line 3a to be a first dielectric film sandwiched between these electrodes. Constitute a first storage capacitor 70a. On the other hand, a part of the first barrier layer 80a facing the second storage capacitor electrode is used as a third storage capacitor electrode, and the second dielectric film 81 is provided between these electrodes to form the second storage capacitor 70b. ing. Then, the first storage capacitor 70a and the second
The storage capacitor 70b is connected in parallel via the contact hole 8a to form the storage capacitor 70. As described above, the second dielectric film 81 forming the second storage capacitor 70b may be a silicon oxide film, a silicon nitride film, or the like, or may be a multilayer film. In general, various known techniques (low-pressure CVD) used to form an insulating thin film 2 such as a gate insulating film.
The second dielectric film 81 can be formed by a method such as a plasma CVD method and a thermal oxidation method.

As described above, in the second embodiment, the high-concentration drain region 1e and the pixel electrode 9a are connected to the first barrier layer 80a.
Are electrically connected to each other, so that a contact hole 8a and a contact hole 8 are formed in comparison with a case where one contact hole is opened from the pixel electrode 9a to the drain region.
The diameter of b can be reduced.

The first barrier layer 80a and the second barrier layer 80b are made of, for example, refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum), It is made of a simple metal, an alloy, a metal silicide or the like containing at least one of Pb (lead). Thereby, the first barrier layer 80a and the pixel electrode 9 are formed through the contact hole 8b.
A good electrical connection can be obtained between a.

Further, as shown in FIGS. 6 and 8, since the light-shielding second barrier layer 80b which covers at least partially the data line 6a in plan view is provided, the second interlayer insulating film 4 is formed. A display defect portion such as light leakage in an image display area along the data line 6a due to a step caused by the presence or absence of the data line 6a formed on the second barrier layer 80b
Can be hidden by As a result, a high-contrast image can be displayed. Similarly, a defective display portion such as light leakage in the image display area along the scanning line 3a and the capacitance line 3b can be hidden by the first barrier layer 80a. As a result, a high-contrast image can be displayed. Furthermore, the first barrier layer 80a and the second barrier layer 80b can be simultaneously manufactured from the same film, which is advantageous in the manufacturing process. In particular, FIG.
8, since the second barrier layer 80b and the pixel electrode 9a are formed so as to at least partially overlap in plan view, the overlapped second barrier layer 80b is formed.
By b, the left and right contours of the opening area of each pixel can be defined at least partially.

When manufacturing the electro-optical device according to the second embodiment, the method for manufacturing the electro-optical device according to the first embodiment is performed between the steps (a) and (b) in FIG. Then, the second dielectric film 81 is formed by a low pressure CVD method and a plasma CV.
A relatively thin film having a thickness of about 200 nm or less is deposited from a high-temperature silicon oxide film (HTO film) or a silicon nitride film by a method D or the like, and contact holes 8a and 8c are formed in the film by reactive ion etching, reactive ion beam etching, or the like. The hole is opened by dry etching or wet etching. Further, a metal alloy film such as a metal such as Ti, Cr, W, Ta, Mo and Pb or a metal silicide is deposited thereon by sputtering to form a conductive film having a thickness of about 50 to 500 nm. By subjecting the first barrier layer 80 to a photolithography process and an etching process.
a and the second barrier layer 80b may be formed.

In addition, when the first barrier layer 80a and the second barrier layer 80b are formed in this manner, a stopper layer for polishing is formed from the same layer as the first barrier layer 80a and the second barrier layer 80b.
It may be formed at a predetermined position on zero. If the stopper layer is formed in this manner, the stop control of the CMP process can be performed by the stopper layer instead of the time management. The detection of the surface of the stopper layer in this case includes, for example, a friction detection method for detecting a change in the coefficient of friction when the stopper layer is exposed, a vibration detection method for detecting vibration generated when the stopper layer is exposed, and a stopper layer. It may be performed by an optical method that detects a change in the amount of reflected light when the light is exposed.

(Third Embodiment) The configuration of an electro-optical device according to a third embodiment of the present invention will be described with reference to FIG. FIG. 9 shows BB ′ of FIG. 2 in the first embodiment.
It is sectional drawing of the TFT array substrate side part corresponding to a cross section. Further, in FIG. 9, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawing. In the third embodiment shown in FIG. 9, the same components as those in the first embodiment shown in FIG. 4 are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 9, the third embodiment is different from the first embodiment in that a first light-shielding film 11a is provided on the TFT array substrate 10 at a position facing the data line 6a. In addition, the first light-shielding film 11a formed on the TFT array substrate 10 as described above includes at least the channel region 1a 'of the TFT 30 and the channel region 1a'.
It may be provided at a position that covers the junction between a ′ and the low-concentration drain region 1c in plan view. In this way, the first light-shielding film 11a can prevent the characteristics of the TFT 30 from deteriorating due to the photoelectric effect in the channel region 1a 'and the junction. In particular, if the first light-shielding film 11a is formed between the TFT array substrate 10 and the TFT 30, the TFT
It is possible to shield light such as return light from the array substrate 10 side. Further, as shown in FIG. 9, the first light shielding film 11a
The first light-shielding film 11 is formed such that the edge of the pixel electrode 9a slightly overlaps the edge of the pixel electrode 9a in plan view and the edge of the data line 6a does not overlap with the edge of the pixel electrode 9a in plan view.
a, the pixel electrode 9a and the data line 6a are laid out in a plane. That is, in FIG. 9, the width W of the data line 6a is
1. The distance W2 between the pixel electrodes 9a adjacent to each other on the left and right and the first
These are provided so that the relationship of W1 ≦ W2 <W3 is satisfied for the width W3 of the light shielding film 11a. Other configurations are the same as those in the first embodiment.

As a result, according to the third embodiment, the left and right contours of the opening region of each pixel can be defined by the first light shielding film 11a overlapping the pixel electrode 9a. At the same time, since the data line 6a and the pixel electrode 9a do not overlap with each other, the parasitic capacitance generated when they face each other via the third interlayer insulating film 7, that is, the parasitic capacitance between the source and the drain of the TFT 30 is extremely small. it can. Further, the second interlayer insulating film 4
The step caused by the presence or absence of the data line 6a formed above is
This can be offset by the presence or absence of the pixel electrode 9a. In particular, in FIG. 9, the film thickness D1 of the data line 6a and the film thickness D of the pixel electrode 9a are shown.
If 2 is made equal, both can be almost completely canceled out, so that the surface of the alignment film 16 can be made very flat. Note that there is a gap between the data line 6a and the pixel electrode 9a through which light can pass, but this gap is hidden by the first light shielding film 11a. Therefore, a display defect such as light leakage does not occur between the data line 6a and the pixel electrode 9a. Further, with this configuration, the second light-shielding film 23 (see FIG. 3) is provided on the counter substrate 20 side.
Need not be provided.

When manufacturing the electro-optical device of the third embodiment, in the step (a) of FIG. 5 in the method of manufacturing the electro-optical device of the first embodiment, the entire surface of the TFT array substrate 10 is Ti, Cr, W, Ta, Mo and P
b, a metal alloy film such as a metal or a metal silicide by sputtering, photolithography and etching.
A film thickness of about 100 to 500 nm, preferably about 200 n
The first light-shielding film 11a having a predetermined pattern with a thickness of m may be formed.

The first light-shielding film 11a is formed, for example, on the scanning line 3
a and may extend below the data line 6a and be electrically connected to a constant potential line. With this configuration, the first light shielding film 11
The fluctuation of the potential of the first light-shielding film 11a does not adversely affect the data line 6a and the TFT 30 disposed opposite to the data line 6a. In this case, the constant potential line includes a constant potential line such as a negative power supply or a positive power supply supplied to a peripheral circuit (for example, a scanning line driving circuit, a data line driving circuit, or the like) for driving the electro-optical device, or a ground. A power source, a constant potential line supplied to the counter electrode 21, and the like are included. Further, the planar layout of the first light shielding film 11a may be a lattice shape along the data lines 6a and the scanning lines 3a, or may be an island shape so as to cover the data lines 6a and the TFTs 30.

(Fourth Embodiment) The configuration of an electro-optical device according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 10 is a sectional view taken along line D- in FIG.
It is sectional drawing of the TFT array substrate side part corresponding to D 'cross section. Further, in FIG. 10, the scale of each layer and each member is made different in order to make each layer and each member a recognizable size in the drawing. In the fourth embodiment shown in FIG. 10, the same components as those in the second embodiment shown in FIG. 8 are denoted by the same reference numerals, and the description thereof will be omitted.

In FIG. 10, in the fourth embodiment, the second
Compared to the embodiment, the edge of the light-shielding second barrier layer 80b and the edge of the pixel electrode 9a are slightly overlapped in a plan view, and the edge of the data line 6a and the edge of the pixel electrode 9a are two-dimensionally arranged. The second barrier layer 80b, the pixel electrode 9a and the data line 6a are laid out in a plane so that they do not overlap. That is, in FIG. 10, the width W1 of the data line 6a, the interval W2 between the pixel electrodes 9a adjacent to each other on the right and left, and the barrier layer 8
These are provided so that the relationship of W1 ≦ W2 <W4 is satisfied for the width W4 of 0b. Other configurations are the same as those of the second embodiment.

As a result, according to the fourth embodiment, the left and right contours of the opening region of each pixel can be defined by the second barrier layer 80b overlapping the pixel electrode 9a. At the same time, the data line 6a
And the pixel electrode 9a do not overlap with each other, so that a parasitic capacitance generated when the two oppose each other via the third interlayer insulating film 7,
That is, the parasitic capacitance between the source and the drain in the TFT 30 can be extremely reduced. Further, a step caused by the presence or absence of the data line 6a formed on the second interlayer insulating film 4 can be offset by the presence or absence of the pixel electrode 9a. In particular, FIG.
At 0, if the thickness D1 of the data line 6a and the thickness D2 of the pixel electrode 9a are made equal, both can be completely canceled out, and the surface of the alignment film 16 can be made very flat. Note that there is a gap between the data line 6a and the pixel electrode 9a through which light can pass, but this gap is hidden by the second barrier layer 80b. Therefore, a display defect such as light leakage does not occur between the data line 6a and the pixel electrode 9a. With this configuration, the second light-shielding film 23 (see FIG. 3) does not need to be provided on the counter substrate 20 side.

The method of manufacturing the electro-optical device according to the fourth embodiment is almost the same as that of the second embodiment, and therefore the description is omitted.

(Overall Configuration of Electro-Optical Device) The overall configuration of the electro-optical device in each embodiment configured as described above will be described with reference to FIGS. Note that FIG.
FIG. 12 is a plan view of the TFT array substrate 10 together with the components formed thereon as viewed from the counter substrate 20, and FIG. 12 is a cross-sectional view taken along the line HH ′ of FIG.

In FIG. 11, a sealing material 52 is provided along the edge of the TFT array substrate 10 and is made of, for example, the same or different material as the second light shielding film 23 in parallel with the inside of the sealing material 52. A third light-shielding film 53 is provided as a frame that defines the periphery of the image display area. A data line driving circuit 101 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing and an external circuit connection terminal 1 are provided outside the sealing material 52.
02 is provided along one side of the TFT array substrate 10, and supplies a scanning signal to the scanning lines 3a at a predetermined timing to drive the scanning lines 3a.
4 are provided along two sides adjacent to this one side. If the delay of the scanning signal supplied to the scanning line 3a does not matter, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. In addition, the data line driving circuit 10
1 may be arranged on both sides along the side of the image display area.
For example, the odd-numbered data lines supply image signals from a data line driving circuit disposed along one side of the image display area, and the even-numbered data lines extend along the opposite side of the image display area. The image signal may be supplied from the data line driving circuit provided. If the data lines 6a are driven in a comb-tooth shape in this manner, the area occupied by the data line driving circuit 101 can be expanded, so that a complicated circuit can be formed. Further, on the remaining one side of the TFT array substrate 10, a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the image display area are provided. At least one corner of the counter substrate 20 has a conductive material 10 for electrically connecting the TFT array substrate 10 and the counter substrate 20.
6 are provided. Then, as shown in FIG. 12, the counter substrate 20 having substantially the same contour as the sealing material 52 shown in FIG.
It is stuck to. In addition, on the TFT array substrate 10,
These data line driving circuit 101 and scanning line driving circuit 10
4, a sampling circuit for applying an image signal to the plurality of data lines 6a at a predetermined timing, and a precharge circuit for supplying a precharge signal of a predetermined voltage level to the plurality of data lines 6a in advance of the image signal. Alternatively, an inspection circuit or the like for inspecting the quality, defects, and the like of the electro-optical device during manufacturing or shipping may be formed.

In each of the embodiments described above with reference to FIGS. 1 to 12, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, TAB (Tape Automated Bonding) The driving LSI mounted on the substrate may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. For example, the TN mode, V
A-mode, PDLC (Polymer Dispersed Liquid Crysta
l) A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as a mode or a normally white mode / normally black mode.

Since the electro-optical device in each of the embodiments described above is applied to a projector, three electro-optical devices are used as light valves for RGB, respectively.
The light of each color separated via the dichroic mirror for RGB color separation is incident on each light valve as projection light. Therefore, in each embodiment, the opposing substrate 20 is not provided with a color filter. However, an RGB color filter may be formed on the opposing substrate 20 in a predetermined area facing the pixel electrode 9a where the second light-shielding film 23 is not formed, together with the protective film.
In this way, the electro-optical device according to each embodiment can be applied to a direct-view or reflective color electro-optical device other than the liquid crystal projector. Furthermore, one pixel 1
A micro lens may be formed so as to correspond to each of them. Alternatively, it is also possible to form a color filter layer with a color resist or the like under the pixel electrode 9a facing the RGB on the TFT array substrate 10. With this configuration, a bright electro-optical device can be realized by improving the efficiency of collecting incident light. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with the dichroic filter, a brighter color electro-optical device can be realized.

The present invention is not limited to the above-described embodiments, but can be appropriately modified without departing from the spirit or spirit of the invention which can be read from the claims and the entire specification. Such an electro-optical device manufacturing method or electro-optical device is also included in the technical scope of the present invention.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wiring, and the like provided in a plurality of pixels in a matrix forming an image display area in an electro-optical device according to a first embodiment.

FIG. 2 is a plan view of a plurality of adjacent pixel groups of a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the electro-optical device according to the first embodiment.

FIG. 3 is a sectional view taken along line A-A 'of FIG.

FIG. 4 is a sectional view taken along line B-B 'of FIG.

FIG. 5 is a process chart sequentially illustrating a manufacturing process of the electro-optical device according to the first embodiment.

FIG. 6 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed in the electro-optical device according to the second embodiment.

FIG. 7 is a sectional view taken along line C-C 'of FIG.

8 is a sectional view taken along line D-D 'of FIG.

FIG. 9 is a cross-sectional view of the electro-optical device according to the third embodiment, taken along line BB ′ in FIG. 2;
It is sectional drawing in the location corresponding to a cross section.

FIG. 10 is a sectional view of the electro-optical device according to the fourth embodiment, taken along line D- in FIG. 6;
It is sectional drawing in the location corresponding to D 'cross section.

FIG. 11 is a plan view of a TFT array substrate in the electro-optical device according to each embodiment, together with components formed thereon, as viewed from a counter substrate side.

FIG. 12 is a sectional view taken along line H-H ′ of FIG. 11;

[Explanation of symbols]

 1a Semiconductor layer 1a 'Channel region 1b Low-concentration source region 1c Low-concentration drain region 1d High-concentration source region 1e High-concentration drain region 1f First storage capacitor electrode 2 Insulating thin film 3a Scanning line 3b Capacitance line 4 ... First interlayer insulating film 5 ... Contact hole 6a ... Data line 7 ... Second interlayer insulating film 8 ... Contact hole 8a ... Contact hole 8b ... Contact hole 8c ... Contact hole 9a ... Pixel electrode 10 ... TFT array substrate 11a ... First light shielding film 12 ... Base insulating film 16 ... Alignment film 20 ... Counter substrate 21 ... Counter electrode 22 ... Alignment film 23 ... Second light shielding film 30 ... Pixel switching TFT 50 ... Liquid crystal layer 70 ... Storage capacitance 70a ... First Storage capacitor 70b Second storage capacitor 80a First barrier layer 80b Second barrier layer 81 Second dielectric film

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) G09F 9/30 313 G09F 9/30 313Z 5G435 348 348A 349 349C H01L 29/786 H01L 29/78 619A 619B F term (Ref.) MA29 MA37 MA41 NA29 PA02 PA03 PA04 PA06 PA08 PA09 QA07 RA05 5C094 AA42 BA03 CA19 DA15 EA03 EA04 EA07 FB02 FB15 GB01 HA10 5F110 AA02 AA06 AA18 AA30 BB01 BB02 CC02 DD02 DD03 DD05 DD12 DD13 EE02 FF02 FF02 EE02 FF02 EE02 GG02 GG13 GG24 GG25 GG32 GG47 GG53 HJ12 HJ23 HL02 HL03 HL04 HL05 HL06 HL07 HL14 HL23 HM15 HM18 NN03 NN04 NN22 NN23 NN24 NN25 NN26 NN35 NN40 NN44 NN45 NN46 NN47 NN54 NN72 QQ11 QQ19 QQ30 5G435 AA17 CC09H09

Claims (14)

[Claims] A step of forming a pixel switching element on a substrate; a step of forming one interlayer insulating film above the pixel switching element; a step of flattening the one interlayer insulating film; Forming a data line on the planarized one interlayer insulating film so as to be connected to one terminal of the pixel switching element via one contact hole; and forming another interlayer insulating film on the data line. Forming a film, and forming a pixel electrode on the other interlayer insulating film so as to be connected to another terminal of the pixel switching element via another contact hole. Of manufacturing an electro-optical device. 2. The method for manufacturing an electro-optical device according to claim 1, wherein the step of flattening includes a step of flattening by a polishing process. 3. The polishing process according to claim 1, wherein the polishing process is performed by a CMP (Chemical Mec.).
3. The method of manufacturing an electro-optical device according to claim 2, wherein the method is a hanical polishing process. 4. The method of manufacturing an electro-optical device according to claim 1, wherein said one interlayer insulating film is made of a silicon oxide film. 5. The step of forming the one interlayer insulating film,
The method for manufacturing an electro-optical device according to claim 4, further comprising a step of forming the silicon oxide film using TEOS (tetraethoxyorthosilicate) as a raw material. 6. The method according to claim 1, further comprising, between the step of forming the one interlayer insulating film and the step of planarizing, performing a heat treatment at 700 ° C. or higher on the one interlayer insulating film. A method for manufacturing an electro-optical device according to claim 1. 7. The electro-optical device according to claim 1, further comprising a step of forming a non-light-transmitting film that covers the data line at least partially when viewed in plan. Device manufacturing method. 8. The same film as the non-light-transmitting film having conductivity simultaneously with the step of forming the non-light-transmitting film between the step of forming the pixel switching element and the step of forming the pixel electrode. 8. The method according to claim 7, further comprising forming a conductive film for connecting the pixel electrode to another terminal of the pixel switching element.
3. The method for manufacturing an electro-optical device according to 1. 9. At least simultaneously with the step of forming the non-light-transmitting film and from the same film as the non-light-transmitting film, at least a channel region of a thin film transistor constituting the pixel switching element and a junction between the channel region and the drain region. The method for manufacturing an electro-optical device according to claim 7, further comprising a step of forming a light-shielding film that covers the light-emitting device in a plan view. 10. In the step of forming the non-light-transmitting film,
10. The electric device according to claim 7, wherein the non-light-transmitting film is formed such that the non-light-transmitting film and the pixel electrode overlap at least partially in a plan view. 11. A method for manufacturing an optical device. 11. The step of forming the data line and the step of forming the pixel electrode, wherein the data line and the pixel are arranged such that the data line and the pixel electrode do not at least partially overlap in plan view. The method of manufacturing an electro-optical device according to claim 10, further comprising forming an electrode. 12. A step of opening the one contact hole and simultaneously opening an opening serving as an alignment mark when forming the data line, between the step of flattening and the step of forming the data line. The method of manufacturing an electro-optical device according to claim 1, further comprising a step of forming a hole. 13. The method of manufacturing an electro-optical device according to claim 1, wherein the thickness of the data line is substantially equal to the thickness of the pixel electrode. 14. A pixel switching element on a substrate, an interlayer insulating film formed above the pixel switching element and planarized, and a pixel switching element formed on the one interlayer insulating film and A data line connected to one terminal of the pixel switching element via a contact hole; another interlayer insulating film formed on the data line; and another contact formed on the other interlayer insulating film. An electro-optical device comprising: a pixel electrode connected to another terminal of the pixel switching element via a hole.