JP2000304821A - Data acquisition control device, control method and test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a plurality of electric circuits acquire data easily and promptly. SOLUTION: This device has an identification information allocating part 12C allocating identification information indicating channels 16F of a plurality of electric circuits 16B to the electric circuits 16B, a data output part 10A outputting the data and identification information of channels using the data, and a bus line 26 supplying output data and the identification information to the electric circuits 16B in parallel. The electric circuits 16B have storage parts 16E storing the identification information of the channels of the allocated electric circuits, receiving parts 16C receiving the data and the identifying information supplied through the bus line 26, and a data acquisition part 16D fetching the data to use for processing channels of the identification information when the identification information stored in the storage part 16E and the identification information received by the receiving part 16C are correspondent.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data fetch control device and a data fetch control method for fetching predetermined data used in a channel into an electric circuit having a channel which is a functional block for performing a predetermined process. And a test apparatus for testing an electric component using an electric circuit having a channel.

[0002]

2. Description of the Related Art Conventionally, memory and IC (Integrated Circuit)
2. Description of the Related Art A test apparatus for performing an electric test of an electric component including a semiconductor device such as an it) is known. FIG. 1 is a diagram illustrating an example of a configuration of a conventional test apparatus. The test apparatus includes a plurality of test heads 100 and an interface (I / F: In).
terface) 112 and a tester processor 114.

A test head 100 includes a pattern generator 102 for generating a test pattern to be given to an electrical component (DUT: Device Under Test) to be tested and an expected value pattern expected to be output from the electrical component DUT; A pin data selector 104 for rearranging the test pattern generated by the generator 102 in accordance with the pin arrangement of the electrical terminals of the electrical component DUT;
A waveform shaper 106 for shaping the waveform of the test pattern output from the device 04, and a device plug for receiving the output signal output from the electrical component DUT while providing the test pattern shaped by the waveform shaper 106 to the electric component DUT. And a comparator 110 for comparing the output signal received by the device insertion unit 108 with an expected value pattern output from the pattern generator 102 and received via the pin data selector 104.

The pattern generator 102, the pin data selector 104, the waveform shaper 106, and the comparator 110
It is configured by a board having an SI (Large-Scale Integrated circuit), and the above processing is executed by the LSI of the board. The tester processor 114 includes the pattern generator 102, the pin data selector 104, the waveform shaper 1
06, used for processing of the LSI included in the comparator 110,
For example, a machine word including data (setting data) related to setting is output to the interface 112.

The interface 112 is a functional block that decodes (decodes) a machine word output from the test processor 114 and executes a predetermined process of an LSI to which setting data included in the machine word is transmitted. Identify the channel. The interface 112 outputs a board selection signal so that the board can be operated by a line connected to the board provided with the LSI having the specified destination channel, and outputs the LSI having the specified destination channel. LSI that enables the LSI to operate by a line connected to
A selection signal is output, and a channel selection signal is output through a line connected to the LSI for enabling the specified destination channel to operate, and the setting data is output to the LSI. As a result, the setting data is taken into the LSI. In this test apparatus, the tester processor 114 needs to output a machine word for each of the channels of the LSI to be set.

In such a test apparatus, a plurality of electric components may be tested at the same time. In such a case, it is necessary to set the channels of the plurality of LSIs to the same setting. However, in the above-described test apparatus, it is necessary to output a machine word for each of the channels of the LSI to be set, so that a machine word including the same setting data must be output from the tester processor 114 a plurality of times. Occurs.

Therefore, the interface 112 of the test apparatus shown in FIG. 1 stores, as a define table, information on the channel of the LSI to which the same setting data is fetched, and when a machine word is received from the test apparatus, The channel of the LSI for which the same setting as that of the transmission destination included in the machine word is performed is taken out from the define table, and the same setting is performed.
The same setting data is sequentially taken into each of the SI channels.

[0008]

As described above, in the conventional test apparatus, in order to load data into a predetermined LSI, a board control line connected to a board provided with the LSI, the LSI LSI connected only to
And a channel for controlling the channel connected to the LSI in order to make the channel of the LSI operable, there has been a problem that many lines must be provided. In addition, the interface 112 needs to have a configuration capable of transmitting a control signal to a predetermined line among a plurality of lines, and there has been a problem that the configuration is complicated.

In the interface 112,
Processing such as decoding a machine word to determine a transmission destination and generating a control signal based on the determination must be performed, and it takes a long time to load data into each LSI channel. Had occurred. Such a problem occurs not only in the test apparatus but also in a data acquisition control apparatus that causes a plurality of electric circuits to acquire data. Therefore, an object of the present invention is to provide a data capture control device, a data capture control method, and a test device that can easily and quickly capture data into a plurality of electric circuits. This object is achieved by a combination of features described in the independent claims.
The dependent claims define further advantageous embodiments of the present invention.

[0010]

To achieve the above object, a data capture control device according to a first embodiment of the present invention comprises:
A data capture control device that includes a plurality of electric circuits each having a channel that is a functional block that performs a predetermined process, and causes the channel to receive predetermined data used for a predetermined process, and indicates a channel of the plurality of electric circuits. An identification information allocating unit that allocates identification information to an electric circuit, a data output unit that outputs data and identification information of a channel that uses the data, and supplies the output data and the identification information to a plurality of electric circuits in parallel An electric circuit, an identification information storage unit for storing identification information of a channel of the electric circuit allocated by the identification information allocation unit, and data and identification information supplied through the bus line. If the identification information stored in the identification information storage unit and the identification information received by the reception unit match, the data is received. And having a data acquisition unit for capturing the data used channel of processing of the identification information.

[0011] In the data acquisition control device according to the first aspect of the present invention, a plurality of boards having at least one plurality of electric circuits, and an assignment for storing in-board identification information of a channel of an electric component on each board. And a board selection unit that outputs to the board a board selection signal that enables an electric circuit on the board. The identification information allocating unit further includes any one of the boards in the board selection unit. , And outputs the in-board identification information of the channel of the electric component provided on the board and the identification information to be assigned to the channel, and the bus line transmits the in-board identification information and the identification information to a plurality of electric circuits. Supply in parallel,
The electric circuit further includes an in-board identification information storage unit that stores in-board identification information for specifying a channel of the electric circuit on the board, and the receiving unit includes the in-board identification information supplied via the bus line and Receiving the identification information, the data acquisition unit, if the in-board identification information stored in the in-board identification information storage unit matches the in-board identification information received by the receiving unit, stores the identification information in the board. You may make it take in as identification information of the channel corresponding to identification information in an identification information storage part.

In addition, the apparatus further includes an identical channel information output unit for outputting identification information of another channel using the same data as the channel of the electric circuit, and the receiving unit is further output from the identical channel information output unit. Receiving the identification information, the electric component further includes an identical channel storage unit that stores identification information of another channel that uses the same data as the own channel, and the data acquisition unit further includes an identical channel storage unit. When the identification information stored in the storage unit matches the identification information received together with the data by the receiving unit,
The data may be taken in as data used for processing of a channel corresponding to the identification information. Also,
The electric circuit may be a one-chip integrated circuit.

In order to achieve the above object, a first aspect of the present invention is provided.
The data capture control method according to the embodiment is a data capture control method that captures predetermined data to be used for processing to channels of a plurality of electric circuits having channels that are function blocks that perform predetermined processing, An identification information allocating step of allocating identification information to a channel of an electric circuit, an identification information storage step of storing identification information, a data output step of outputting data and identification information of a channel using the data, and the output data And a parallel supply step of supplying identification information to a plurality of electric circuits in parallel, a reception step of receiving supplied data and identification information in the parallel supply step, an identification information stored in the identification information storage step, and a reception step. If the identification information received in the step matches, the data is used for processing the channel of the identification information. And having a data acquisition step for capturing the electric circuit as the data.

The same channel information output step of outputting identification information of another channel using the same data as the channel of the electric circuit, and the same channel information receiving step of receiving the identification information output by the same channel information output step And the same channel storing step of storing identification information of another channel using the same data as the own channel. The data capturing step further includes the identification information stored in the same channel storing step. When the identification information and the identification information received together with the data in the receiving step match, the data may be taken in as data used for processing of a channel corresponding to the identification information.

[0015] To achieve the above object, the first aspect of the present invention is as follows.
The test apparatus according to the embodiment, a pattern generator that generates a test pattern given to the electrical component and an expected value pattern expected to be output from the electrical component, and a test pattern generated by the pattern generator A pin data selector that rearranges according to the pin arrangement of the electrical terminals,
A waveform shaper for shaping the waveform of the test pattern output from the pin data selector, a device insertion portion for providing the test pattern shaped by the waveform shaper to the electrical component, and receiving an output signal output from the electrical component; A test device comprising a comparator for comparing an output signal received by the device insertion unit with an expected value pattern, wherein the pattern generator, the pin data selector, the waveform shaper, and at least one of the comparator One is provided with an electric circuit having a channel which is a functional block for performing predetermined processing, a data output unit for outputting data used for processing of the channel of the electric circuit and identification information of the channel, A bus line for supplying identification information to the plurality of electric circuits in parallel, wherein the electric circuit has a channel included in the allocated electric circuit. An identification information storage unit that stores the identification information of the channel; a reception unit that receives the data and the identification information supplied via the bus line; an identification information stored in the identification information storage unit; A data capturing unit that captures data as data used for processing the channel of the identification information when the identification information matches. An identification information allocating unit for allocating channel identification information to an electric circuit may be further provided. Note that the above summary of the present invention does not list all of the necessary features of the present invention, and a sub-combination of these features may also be an invention.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described through embodiments of the present invention. However, the following embodiments do not limit the invention according to the claims and are described in the embodiments. Not all combinations of the features described above are essential to the solution of the invention. FIG. 2 shows one embodiment of the present invention.
It is a figure showing the composition of the test device which has the data acquisition control device concerning an embodiment. The test apparatus has a plurality of test heads 14, an interface 12, a tester processor 10, a bus line 26, and a plurality of board selection lines 28. The test head 14 includes a pattern generator 16
, A pin data selector 18, a waveform shaper 20, a device insertion unit 22, and a comparator 24.

The pattern generator 16 generates a test pattern to be applied to an electrical component under test (DUT) and an expected value pattern expected to be output from the electrical component DUT. In the present embodiment, the pattern generator 16 has a board 16A, an LSI 16B provided on the board 16A, and the like. The pin data selector 18 rearranges the test pattern generated by the pattern generator 16 in accordance with the pin arrangement of the electrical terminals of the electric component, and transmits the expected value pattern generated by the pattern generator 16 to the comparing unit 24. Output. In the present embodiment, the pin data selector 18 includes a board 18A,
It has an LSI 18B and the like provided on the board 18A.

The waveform shaper 20 includes a pin data selector 1
The waveform of the test pattern output from 8 is shaped. In the present embodiment, the waveform shaper 20 includes a board 20A and LSIs 20B, 20C, and the like provided on the board 20A. The device insertion unit 22 supplies the test pattern shaped by the waveform shaper 20 to the electric component DUT, and receives an output signal output from the electric component DUT. The comparator 24 compares the output signal received by the device insertion unit 22 with the expected value pattern output from the pin data selector 18. In the present embodiment, the comparator 24 has a board 24A, an LSI 24B provided on the board 24A, and the like.

The tester processor 10 controls a plurality of test heads 14. The interface 12 is mainly
It mediates data between the tester processor 10 and the plurality of test heads 14. The bus line 26 is connected to the interface 12 and the plurality of LSs of the plurality of test heads 14.
I16B, 18B, 20B, etc. are connected. Therefore, the data transmitted from the interface 12 via the bus line 26 corresponds to the LSI 1 of the plurality of test heads 14.
6B, 18B, 20B and so on. The board selection line 28 connects between the interface 12 and one predetermined board 16A18A or 20A. Therefore, a board selection signal described later is supplied only to a predetermined board.

FIG. 3 is a diagram showing in detail the configuration of a part of the test apparatus according to one embodiment of the present invention. The same parts as those in FIG. 2 are denoted by the same reference numerals. Tester processor 1
0 has a data output unit 10A as an example of the same channel information output unit. The data output unit 10A includes a pattern generator 16, a pin data selector 18, and a waveform shaper 2.
0, and outputs the same channel information indicating the channel in which the same setting data is to be fetched among the channels as functional blocks for executing predetermined processing of the plurality of LSIs included in the comparator 24. In the present embodiment, the data output unit 10A outputs, along with the channel identification information, the channel identification information for which the same setting data as that of the channel is taken. In the present embodiment, a pin number, a child number, and an STN number are used as channel identification information.

Here, the pin number is information for identifying a channel in a predetermined test head 14. The child number is information for identifying a plurality of functions in the same channel. For example, when performing simultaneous measurement, one channel is connected to a plurality of DUTs in order to output the same pattern to predetermined pins of a plurality of DUTs.
The pattern will be output to a predetermined pin of the UT,
At this time, the information for identifying the function of outputting a pattern to one DUT is a child number. When performing simultaneous measurement, it is necessary to make settings such that data is output to one DUT but not to another DUT. In such a case, the function within the channel is specified by the child number. Then, settings can be made for each of them. The STN number is information for identifying a test head among the plurality of test heads 14.

The data output unit 10A includes a pattern generator 16, a pin data selector 18, a waveform shaper 20,
And outputs a machine word for setting channels of the LSIs 16B and 18B of the comparator 24 to the interface 12. In the present embodiment, the machine word is
It has identification information for identifying the channel of the LSI to be set and setting data for the channel of the LSI. For example, as setting data for setting the channel of the LSI 20B of the waveform shaper 20, for example, CLK
There are setting data of 1, Dφ, and RZ. This setting data is obtained by converting data Dφ into RZ according to clock CLK1.
(Return Zero) method is shown.

The interface 12 includes an allocation information storage section 12A, a board selection section 12B, and an identification information allocation section 12B.
C and a relay unit 12D. Assignment information storage unit 12
A is a channel 16 such as a plurality of LSIs 16B and 18B.
Information for identifying F etc. in each board (in-board identification information)
Is stored. The board selection unit 12B is provided for a predetermined board 1
6, 18, 20 and the like are operable by a predetermined board 16, 18, 2,
Output to 0 etc.

The identification information allocating unit 12 C
A process of allocating identification information to channels 16F such as B and 18B is performed. In the present embodiment, the board selection unit 12B
To select the respective boards,
LSI stored in the board stored in A
The in-board identification information of the channel and the identification information to be allocated to the channel are output via the bus line 26.

FIG. 4 is a timing chart when assigning an identification number of the test apparatus according to one embodiment of the present invention. The identification information allocating unit 12C causes the board selecting unit 12B to output a board selection signal of a logical value "1" to a predetermined board via a predetermined board selecting line 28, and also outputs a clock (not shown) generated by a clock generator (not shown). BU
SCLK), add1, add2, add3, dat1, dat via the bus line 26 in accordance with the rise of SCLK).
2, dat3 and dat4 are output. add1 includes a command (for example, “#FF”) indicating that the data is data to which identification information is assigned. add2 contains the number of the LSI in the board. a
dd3 contains the number of the channel in the LSI. dat1 to dat4 include a pin number, a child number, and an STN number. In the present embodiment,
Data width 500 ns (nanosecond), clock pulse width 50
ns clock is used.

Returning to FIG. 3, the relay section 12D sends out the machine word and the same channel information output from the data output section 10A of the tester processor 10 to the bus line 26. The LSI 16B of the pattern generator 16
C, a data acquisition unit 16D, an in-board identification information storage unit, a same channel storage unit, a storage unit 16E as an example of the identification information storage unit, and a channel 16F. The receiving unit 16C receives data transmitted via the bus line 26. In the present embodiment, the receiving unit 16
C receives the same channel information, machine word, in-board identification information and identification information.

When the in-board identification information stored in the storage unit 16E matches the in-board identification information received by the receiving unit 16C, the data acquisition unit 16D transmits the identification received together with the in-board identification information. The storage unit 1 stores the information as channel identification information corresponding to the in-board identification information.
6E. Further, when the identification information stored in the storage unit 16E matches the identification information of the same channel information received by the receiving unit 16C, the data capturing unit 16D includes the other information included in the same channel information. Is stored in the storage unit 16E. Further, the data capturing unit 16D matches the identification information of the channel stored in the storage unit 16E or the identification information of another channel using the same data with the identification information of the machine word received by the receiving unit 16C. In this case, the setting data of the machine word is fetched as setting data used for processing the channel of the identification information.

The storage unit 16E stores the LSI in the board.
, The identification information of the channel 16F of the LSI 16 in the test apparatus, and the same channel information of another channel using the same data as the channel 16F. Channel 16F
Performs a predetermined process based on the setting data captured by the data capturing unit 16D. Here, another LSI 18
B, 20B, 20C, 24B, etc.
C, a function unit similar to the data acquisition unit 16D and the storage unit 16E, and a channel for performing a predetermined process. The processes performed by the channels may be the same or different.

The operation of the test apparatus according to one embodiment of the present invention will be described. The test apparatus first performs an identification information allocating process of allocating identification information to channels such as a plurality of LSIs 16B and 18B in the test apparatus.
The same channel information setting process for setting the identification numbers of the channels using the same data is performed on 6B, 18B, etc., and then the channel setting process for setting the channels of a plurality of LSIs 16B, 18B is performed.

In the identification information allocating process, the identification information allocating unit 12C causes the board selecting unit 12B to operably select one board, and the LSI provided on the board stored in the allocation information storage unit 12A. The in-board identification information of the channel and the identification information to be allocated to the channel are output via the bus line 26. Here, it is assumed that the board 16A is selected by the board selection unit 12B. Next, the receiving unit 16C of the operably selected board 16A receives the in-board identification information and the identification information transmitted via the bus line 26, and the data acquisition unit 16D stores the in-board identification information stored in the storage unit 16E. It detects whether or not the identification information matches the in-board identification information received by the receiving unit 16C.

As a result, when it is detected that the in-board identification information stored in the storage unit 16E matches the in-board identification information received by the reception unit 16C, the data acquisition unit 16D sets the data acquisition unit 16D to The identification information received together with the in-board identification information is stored in the storage unit 16E of the same LSI as the identification information of the channel corresponding to the in-board identification information. Next, when there is another channel in the same board, the same processing is repeated for the other channel, and then the same processing is performed for the channel of the other board. The same processing as described above is performed on the channels of the other test heads 14. Thereby, identification information is assigned to each channel in the test apparatus.

In the same channel information setting process, the data output unit 10A outputs to the interface 12 the same channel information having the channel identification information and the identification information of the channel that takes in the same setting data as the channel. Then the interface 12
Relay unit 12D transmits the same channel information to the bus line 26.
To send to. In this processing, each board is operable, and the receiving unit 16C of each board is connected to the bus line 2.
6 to receive the same channel information transmitted through.

Thereafter, the data capturing section 16D and the like detect whether or not the identification information stored in the storage section 16E matches the identification information of the same channel information received by the receiving section 16C. In this case, the identification information of another channel that uses the same data included in the same channel information is stored in the storage unit 16E or the like.

In the channel setting process, the data output unit 1
0A sequentially outputs to the interface 12 a machine word having identification information for identifying the channel of the LSI to be set and setting data for the channel of the LSI. Next, the relay unit 12D of the interface 12
Sends the output machine word to the bus line 26. In this process, each board 16A is operable, and the receiving unit 16C of each board is connected to the bus line 2A.
6 receives the machine word transmitted through the same.

Thereafter, the data capturing unit 16D and the like store the identification information of the channel stored in the storage unit 16E or the identification information of another channel using the same data and the machine information received by the receiving unit 16C and the like. It is detected whether or not the identification information matches the word identification information. If the identification information matches, the setting data of the machine word is taken in as setting data used for processing the channel of the identification information. This allows
Predetermined processing can be performed on each channel 16F and the like.

Therefore, it is not necessary for the interface to select each LSI, channel or the like by the selection signal when setting the channel, and the number of control lines for the selection signal can be reduced. Further, since it is not necessary to select each LSI, channel, and the like by the selection signal, the configuration of the interface is simplified. Also, by transmitting the setting data for a channel only once, a plurality of channels having the same setting can be set at the same time, and the time required for setting can be reduced. Therefore, DUT
The time required for the test can be shortened.

The present invention is not limited to the above embodiment, and various modifications are possible. For example, in the above embodiment, a one-chip LSI is used as the electric circuit. However, the present invention is not limited to this, and may be any electric circuit having a channel that is a functional block that performs a predetermined process. Further, in the above-described embodiment, the identification information allocating unit 12C, the board selecting unit 12B,
Although the present invention includes the assignment information storage unit 12A, the present invention is not limited to this. At least one of the identification information assignment unit 12C, the board selection unit 12B, and the assignment information storage unit 12A is provided in the tester processor 10. It may be provided.

Although the present invention has been described with reference to the embodiment, the technical scope of the present invention is not limited to the scope described in the above embodiment. It is apparent to those skilled in the art that various changes or improvements can be added to the above embodiment. It is apparent from the description of the appended claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

[0039]

As is apparent from the above description, according to the present invention, data can be easily and quickly taken into a plurality of electric circuits.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a test apparatus according to a conventional example.

FIG. 2 is a diagram showing a configuration of a test apparatus having a data acquisition control device according to one embodiment of the present invention.

FIG. 3 is a diagram showing a detailed configuration of a part of a test apparatus according to an embodiment of the present invention.

FIG. 4 is a timing chart when assigning an identification number in a test apparatus according to one embodiment of the present invention.

[Explanation of symbols]

Reference Signs List 10 tester processor 12 interface 12A allocation information storage device 12B board selection unit 12C identification information allocation unit 12D relay unit 14 test head 16 pattern generator 16A board 16B LSI 16C reception unit 16D data acquisition unit 16E storage unit 16F channel 18 pin data Selector 20 Waveform shaper 22 Device insertion unit 24 Comparison unit 26 Bus line 28 Board selection line

Claims (8)

[Claims] 1. A data capture control device comprising: a plurality of electric circuits each having a channel, which is a functional block for performing a predetermined process, wherein the channel captures predetermined data used for the predetermined process. An identification information allocating unit that allocates identification information indicating the channel of the electric circuit to the electric circuit; a data output unit that outputs the data and the identification information of the channel that uses the data; A bus line that supplies data and the identification information to a plurality of the electric circuits in parallel, wherein the electric circuit transmits the identification information of the channel included in the electric circuit allocated by the identification information allocating unit. An identification information storage unit for storing; a reception unit for receiving the data and the identification information supplied via the bus line; Data acquisition that, when the identification information stored in the information storage unit matches the identification information received by the reception unit, captures the data as data used in the processing of the channel of the identification information. And a data acquisition control device. 2. A plurality of boards each having at least one of the plurality of electric circuits; an allocation information storage unit for storing in-board identification information of the channel of the electric component on each of the boards; A board selection unit that outputs a board selection signal that enables the electric circuit to the board, wherein the identification information allocating unit is one of the board selection units.
And selecting one of the boards, and outputting in-board identification information of the channel of the electrical component provided in the board and identification information to be assigned to the channel, wherein the bus line has the in-board identification information and The identification information is supplied to the plurality of electric circuits in parallel, and the electric circuit further includes an in-board identification information storage unit that stores the in-board identification information that specifies the channel of the electric circuit on the board. The receiving unit receives the in-board identification information and the identification information supplied via the bus line, and the data acquisition unit includes the board stored in the in-board identification information storage unit. When the in-board identification information matches the in-board identification information received by the receiving unit, Data acquisition control device according to claim 1, characterized in that incorporated into the identification information storage unit as the identification information of a channel. 3. The same channel information output unit that outputs the identification information of another channel using the same data as the channel of the electric circuit, wherein the receiving unit further outputs the same channel information. Receiving the identification information output from the unit, the electrical component further includes a same channel storage unit that stores the identification information of the other channel that uses the same data as the channel of its own, The data capturing unit further corresponds to the data when the identification information stored in the same channel storage unit matches the identification information received together with the data by the receiving unit. 3. The data capture control device according to claim 1, wherein the data capture control device captures as data used for the processing of the channel. 4. The data capture control device according to claim 1, wherein the electric circuit is a one-chip integrated circuit. 5. A data capture control method for capturing predetermined data to be used in the processing into the channels of a plurality of the electric circuits each having a channel which is a functional block for performing a predetermined process, wherein the electric circuit includes: An identification information allocating step of allocating identification information to the channel; an identification information storing step of storing the identification information; a data output step of outputting the data and the identification information of the channel using the data; A parallel supply step of supplying the data and the identification information to the plurality of electric circuits in parallel, a reception step of receiving the supplied data and the identification information in the parallel supply step, and identification information storage. The identification information stored in the receiving step matches the identification information received in the receiving step A data capturing step of capturing the data as data used in the processing of the channel of the identification information into the electric circuit. 6. An identical channel information output step of outputting the identification information of another channel using the same data as the channel of the electric circuit, and receiving the identification information output by the same channel information output step. The same channel information receiving step, and the same channel storing step of storing the identification information of the other channel using the same data as that of the own channel. The data capturing step further comprises: When the identification information stored in the same channel storage step matches the identification information received together with the data in the reception step, the data is used for the processing of the channel corresponding to the identification information. 6. The data according to claim 5, wherein the data is captured as data to be processed. Write control method. 7. A pattern generator for generating a test pattern to be applied to an electric component and an expected value pattern expected to be output from the electric component, and the test pattern generated by the pattern generator is used for the electric component. A pin data selector for rearranging according to the pin arrangement of the electrical terminals, a waveform shaper for shaping the waveform of the test pattern output from the pin data selector, and the test pattern shaped by the waveform shaper. A test comprising: a device insertion unit that receives an output signal output from the electric component while being provided to the electric component, and a comparator that compares the output signal received by the device insertion unit with the expected value pattern. An apparatus comprising: a small number of the pattern generator, the pin data selector, the waveform shaper, and the comparator. A data output unit that includes an electric circuit having a channel that is a functional block that performs a predetermined process, and that outputs data used for the process of the channel of the electric circuit and the identification information of the channel; A bus line for supplying the output data and the identification information to the plurality of electric circuits in parallel, wherein the electric circuit stores the identification information of the assigned channel of the electric circuit. An identification information storage unit; a reception unit that receives the data and the identification information supplied via the bus line; an identification information stored in the identification information storage unit; When the identification information matches, a data capturing unit that captures the data as data used for the processing of the channel of the identification information. A test apparatus comprising: 8. The test apparatus according to claim 7, further comprising an identification information allocating unit that allocates the identification information of the channel to the electric circuit.