JP2000295536A - Ccd driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize transfer efficiency of electric charges by adopting variable output characteristics of a plurality of drive pulses to drive a charge transfer CCD so as to make the output characteristics of the drive pulses adjustable in an operating state of the CCD. SOLUTION: The driver consists of a timing pulse generating circuit 12 that generates timing pulses PH1, PH2 to drive a horizontal transfer CCD 20 and of drive circuits 14, 16 that generate required drive pulses H1, H2 on the basis of the timing pulses PH1, PH2 and provide an output of the drive pulses H1, H2 to a transfer electrode of the horizontal transfer CCD 20. Each of the drive circuits 14, 16 is provided with a characteristic changeover means that can stepwise switch the output characteristic of the drive pulses H1, H2 and with a control means that controls a switching step number of the characteristic changeover means. Thus, the output characteristics of the drive pulses H1, H2 can mutually be adjusted in the operating state of the horizontal transfer CCD 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CCD driving device, and more particularly to a CCD driving device for generating a driving pulse for driving a charge transfer CCD such as a CCD area sensor or a CCD line sensor.

[0002]

2. Description of the Related Art In general, this kind of CCD driving device is manufactured as a large-scale integrated circuit (LSI), and the output characteristics of various driving pulses are determined in consideration of a combination with a CCD driven at the time of design.

[0003]

Problems to be Solved by the Invention
The conventional CCD driving device described in Japanese Patent Application Publication No.
By making the rising speed and the falling speed of the driving pulse for driving D different from each other, it is possible to suppress the decrease in the maximum amount of handled charges, to improve the transfer efficiency of the charge transfer and to achieve the high-speed transfer drive. However, once the rising speed or the falling speed of the drive pulse is set, it cannot be freely changed thereafter.

Accordingly, a CCD or a CCD driving device (LS
After mounting I) on a printed circuit board, there is a problem that the output characteristics of the driving pulse cannot be optimized while the CCD is actually operated. In addition, a digital camera using a CCD has a drive mode for driving a CCD, a drive mode for a movie, a drive mode for auto-focusing, and the like in addition to a drive mode for driving a CCD. However, in such a system, there is a problem that the output characteristics of the drive pulse cannot be optimized for each frequency.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has various output characteristics of a plurality of drive pulses for driving a charge transfer CCD. Can be adjusted, the transfer efficiency can be optimized, and the output characteristics of the drive pulse can be optimized according to the drive frequency.
It is an object to provide a CD drive.

[0006]

According to a first aspect of the present invention, there is provided a timing pulse generating circuit for generating a plurality of timing pulses for driving a charge transfer CCD; A plurality of drive circuits for generating required drive pulses based on the timing pulses and outputting the drive pulses to the transfer electrodes of the charge transfer CCD, wherein each of the drive circuits steps output characteristics of the drive pulses. Characteristic switching means that can be selectively switched;
Control means for controlling the number of switching stages in the characteristic switching means.

That is, the control means can arbitrarily adjust the number of switching stages (ie, the output characteristics of the driving pulse) by the characteristic switching means, thereby mutually adjusting the output characteristics of each driving pulse while the CCD is operated. To be able to. The characteristic switching means has a plurality of output means for generating the drive pulse based on the timing pulse as shown in claim 2 of the present application, and the drive is performed based on the number of operating of the plurality of output means. It is characterized in that the output characteristics of the pulse can be switched stepwise. Therefore, when adjusting the output characteristics of the drive pulse, the control means may change the number of the plurality of output means to be operated.

According to a third aspect of the present invention, the number of switching stages controlled by the control means is changed according to the transfer electrode of the charge transfer CCD. That is, since the load capacitance of the transfer electrode of the charge transfer CCD differs depending on the type, the output characteristics of the drive pulse applied to each transfer electrode are individually adjusted.

As set forth in claim 4 of the present application, the timing pulse generating circuit switches and outputs timing pulses having different frequencies in order to switch a transfer rate, and the number of switching stages in the characteristic switching means controlled by the control means is as follows. The present invention is characterized in that the output characteristics are varied so as to obtain appropriate output characteristics in accordance with the frequency of the timing pulse output from the timing pulse generation circuit. That is, the output characteristics of the drive pulse can be optimized according to the drive frequency.

The drive circuit has rewritable storage means for storing information indicating the number of switching stages in the characteristic switching means, and the control means is stored in the storage means. It is characterized in that the number of switching stages in the characteristic switching means is controlled based on information. Further, the timing pulse generating circuit and the plurality of driving circuits are configured by a one-chip integrated circuit as described in claim 6 of the present application.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a CCD driving device according to the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of a CCD driving device according to the present invention. As shown in FIG. 1, the CCD driving device 10 includes a timing pulse generation circuit 12, a driving circuit 1
4, 16 and an interface 18, etc., and are manufactured as a one-chip CCD driving LSI.

The timing pulse generation circuit 12 includes a CCD
This embodiment generates various timing pulses for driving the two-phase horizontal transfer CCD 20 in this embodiment.
_Is generated in the case where two-phase timing pulses P _H1 and P _H2 for driving are generated. The timing pulse generation circuit 12 includes, for example, a counter that counts a reference clock f, and a ROM that stores “1” and “0” indicating various timing pulse patterns as count addresses of the counter. By reading "1" or "0" from the ROM based on the counter value, various timing pulses are generated.

The drive circuit 14 generates a drive pulse H1 having required output characteristics (slew rate, output current) based on the input timing pulse P _H1 , and transfers the drive pulse H1 to one of the transfer electrodes of the horizontal transfer CCD 20. 22, and the drive circuit 16 similarly drives the drive pulse H having required output characteristics based on the input timing pulse P _H2.
2 and the driving pulse H2 is transferred to the horizontal transfer CCD 20
Is output to the other transfer electrode 24.

The driving circuits 14 and 16
The output characteristics of the drive pulses H1 and H2 can be switched stepwise based on control information applied from the system controller 30 via the interface 18. Next, the drive circuit 14
And 16 will be described in detail.

FIG. 2 is a block diagram showing the configuration of the drive circuit 14. The drive circuit 16 has the same configuration as the drive circuit 14 and is omitted in FIG. As shown in FIG. 2, the drive circuit 14 includes a plurality of tri-state buffers B1, B2.
.. Bn, a control circuit 40, and an SRAM 42 as a rewritable memory.

A plurality of tri-state buffers B1, B2
,... Bn generate a drive pulse H1 based on the timing pulse P _H1 and are connected in parallel. The control circuit 40 controls each tri-state buffer B1
, B2,... Bn are controlled in advance via the interface 18 and the control circuit 40.
Based on the number information (control information) of the tristate buffers stored in the AM 42, only the number of tristate buffers indicated by the number information is operated.

Accordingly, the output characteristics of the driving pulse can be switched stepwise according to the number information of the tri-state buffers stored in the SRAM 42. Next, a method of adjusting the drive pulses H1 and H2 will be described. Since the load capacitance differs between the transfer electrode 22 and the transfer electrode 24 of the horizontal transfer CCD 20, and the capacitance due to the pattern of the printed circuit board also differs, when adjusting the drive pulses H1 and H2, C is required.
After mounting the CD drive device 10 (LSI) and the CCD having the horizontal transfer CCD 20 on a printed circuit board, the horizontal transfer CCD 20 is actually operated.

Then, the output waveforms of the drive pulses H1 and H2 are displayed on an oscilloscope, and first, the output characteristics (slew rate and output current) of one of the drive pulses are adjusted. This adjustment is performed by writing the information on the number of tri-state buffers to be operated in the SRAM 42 and switching the output characteristics of the drive pulse in a stepwise manner as described above.

Next, the output characteristics of the other drive pulse are adjusted while observing the output waveform of the one drive pulse thus adjusted. That is, as shown in FIG. 3, the adjustment is performed so that the waveform is symmetric and the cross point is located at an intermediate position. This allows
The output characteristics of the two-phase drive pulses H1 and H2 can be optimized. The information on the number of tri-state buffers adjusted as described above can be written in the SRAM 42 when the system is started.

FIG. 4 is a block diagram showing another embodiment of the CCD driving apparatus according to the present invention, and shows a case where the present invention is applied to a digital camera. The digital camera shown in the figure mainly includes a CCD driving device 50, a system controller 60, a photographic lens 62, a CCD 64, an analog processing circuit 66 including a preamplifier, an A / D converter 68, a digital processing circuit 70, a recording device 72, and the like. Have been.

The electric charges accumulated in the CCD 64 via the photographing lens 62 are transferred based on various driving pulses applied from the CCD driving device 50, and are sequentially read out as voltage signals (image signals) corresponding to the signal charges. CCD6
4 is applied to an analog processing circuit 66 including a preamplifier, a CDS circuit, etc., and the processed image signal is converted into R, G, B digital signals by an A / D converter 68. Then, it is added to the digital processing circuit 70.

The digital processing circuit 70 includes a gamma correction circuit, a YC signal generation circuit, and the like. The gamma correction of the R, G, B digital signals, the YC signals of the R, G, B signals (the luminance signal Y and the chroma signal Perform processing such as conversion to C), and
The C signal is stored in the frame memory. The recording device 72 compresses the YC signal stored in the frame memory into a predetermined format and records the compressed signal on a memory card that is detachable from the camera.

This digital camera has a drive mode for driving the CCD, a drive mode for movie shooting, a drive mode for autofocus, etc. in addition to a drive mode for normal photographing. f
By switching between ₁ and f ₂ , the reading speed of the CCD 64 can be switched. The CCD driving device 50 includes a timing pulse generation circuit 51, a driving circuit 5
, 53, 54,..., An interface 55, a changeover switch 56, and the like.

The system controller 60 controls the circuits of the camera based on a signal input from a release switch or the like (not shown) and controls the CCD driving device 50. The system controller 60 controls the reference clock f ₁ according to the driving mode.
An interface command signals for switching between f ₂ 55
, And outputs a reference clock having a frequency corresponding to the drive mode to the timing pulse generation circuit 51.

The timing pulse generation circuit 51 counts a reference clock similarly to the above-described timing pulse generation circuit 12, and is configured to generate various timing pulses based on the count value. When it changes, the frequency of various timing pulses also changes. In this embodiment, the frequency of the reference clock is changed in order to change the frequency of various timing pulses. However, the present invention is not limited to this. Patterns for generating timing pulses having different frequencies are stored. ROM may be prepared, and the frequency of the timing pulse may be changed by switching the pattern to be used according to the drive mode.

The drive circuits 52, 53, 54,... Generate drive pulses having required output characteristics based on each timing pulse input from the timing pulse generation circuit 51, and output these drive pulses to the CCD 64. . The drive circuits 52 and 53 are connected to the horizontal transfer C of the CCD 64.
It outputs two-phase drive pulses H1 and H2 for driving the CD, and is configured similarly to the drive circuit 14 shown in FIG. 2 so that the output characteristics of each drive pulse H1 and H2 can be adjusted. ing. Further, the driving circuits 52 and 5
When the frequency of the timing pulse output from the timing pulse generation circuit 51 is switched according to the driving mode, the driving pulse 3 outputs a driving pulse adjusted to have an optimum output characteristic with respect to the frequency of the timing pulse. . The output characteristics of the drive pulse can also be adjusted as described with reference to FIG. 2. In this case, the number information corresponding to the frequency is stored in the SRAM, and the number information different according to the frequency (drive mode). Will be used.
That is, the drive circuits 52 and 53 can output drive pulses whose output characteristics are optimized according to the frequency of the drive pulse.

The drive circuit 54 for outputting pulses other than the drive pulses H1 and H2 may be configured so that the characteristics of the output pulses can be adjusted. Next, the SRAM shown in FIG.
A method for loading information (number information) for adjusting the output characteristics of the drive pulse into the register 42 will be described. The information (number information in this embodiment) for adjusting the output characteristics of the drive pulse stored in the SRAM 42 of each drive circuit, which was determined at the time of adjustment of the drive pulse, is provided by the system controller 30 of FIG.
4 is stored in the same ROM as the program of the system controller 60 in FIG. 4, and the information stored in the ROM is loaded into the SRAM 42 of each drive circuit when the system is started.

In this embodiment, the output characteristic of the drive pulse is adjusted stepwise by setting the number of tri-start buffers to be operated. However, the present invention is not limited to this. The output resistance and the slew rate of the drive circuit may be changed stepwise by switching / switching. Further, in this embodiment, the output characteristics of the two-phase drive pulse for driving the horizontal transfer CCD are adjusted. However, the present invention is not limited to this. Alternatively, the output characteristics of the drive pulse for driving the vertical transfer CCD may be adjusted.

[0029]

As described above, according to the present invention, the output characteristics of a plurality of drive pulses for driving the charge transfer CCD are varied stepwise, and the output of the drive pulses is performed while the CCD is operating. Since the characteristics can be adjusted, the output characteristics of the drive pulse can be adjusted in consideration of the load capacitance of the transfer electrode, the capacitance due to the pattern of the printed circuit board, and the like, thereby optimizing the transfer efficiency.
Further, in the case of a system in which switching is performed to two or more frequencies as drive pulses, optimization is performed by changing the output characteristics of the drive pulse for each frequency, such as giving priority to the SN ratio or giving priority to the readout speed. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a CCD driving device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a driving circuit shown in FIG.

FIG. 3 is a waveform diagram of two-phase driving pulses for driving a two-phase horizontal transfer CCD.

FIG. 4 is a block diagram showing another embodiment of the CCD driving device according to the present invention.

[Explanation of symbols]

10, 50: CCD driving device, 12, 51: timing pulse generating circuit, 14, 16, 52, 53, 54: driving circuit, 18, 55: interface, 20: horizontal transfer CCD, 22, 24: transfer electrode, 30 , 60 ... System controller, 64 ... CCD

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hiroshi Tamayama 3-11-46 Izumi, Asaka-shi, Saitama F-term in Fujisha Shin Film Co., Ltd. 5C024 AA01 CA25 FA01 FA02 FA11 GA11 JA21 JA32

Claims (6)

[Claims] A timing pulse generating circuit for generating a plurality of timing pulses for driving a charge transfer CCD; generating a required drive pulse based on the plurality of timing pulses; CC
A plurality of drive circuits that output to the transfer electrodes of D. Each of the drive circuits controls a characteristic switching unit capable of switching output characteristics of the drive pulse in a stepwise manner, and controls the number of switching stages in the characteristic switching unit. A CCD driving device, comprising: a control unit. 2. The characteristic switching means has a plurality of output means for generating the drive pulse based on the timing pulse, and outputs the drive pulse based on the number of operating of the plurality of output means. 2. The CCD driving device according to claim 1, wherein the characteristics can be switched stepwise. 3. The number of switching stages in the characteristic switching unit controlled by each control unit is determined by a charge transfer CCD.
2. The CCD driving device according to claim 1, wherein the driving voltage is changed depending on the transfer electrode. 4. The timing pulse generation circuit switches and outputs timing pulses having different frequencies to switch a transfer speed, and the number of switching stages in the characteristic switching unit controlled by the control unit is determined by an output from the timing pulse generation circuit. 2. The CCD driving device according to claim 1, wherein the output is changed so as to obtain an appropriate output characteristic according to the frequency of the timing pulse. 5. The drive circuit has rewritable storage means for storing information indicating the number of switching stages in the characteristic switching means, and the control means controls the characteristic based on the information stored in the storage means. 2. The CCD driving device according to claim 1, wherein the number of switching stages in the switching means is controlled. 6. The CCD driving device according to claim 1, wherein the timing pulse generating circuit and the plurality of driving circuits are formed by a one-chip integrated circuit.