JP2000101934A - Pulse generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a pulse generator which can reduce the size, cost and power consumption of a system. SOLUTION: The DC voltage that is given from the outside, via a phase control input terminal 118 undergoes the A/D conversion via an A/D converter 101, and the output data 102 of the converter 101 are decoded with a decoder 116. Then a control signal 117 of a selector 115 is produced. The signal 117 functions to select and output one of output pulse 104 of a pulse generation circuit 103 and output pulses 106,..., 114 of the delay circuits 105,..., 113 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse generator, and more particularly, to a pulse generator which is extremely suitable for use as a pulse generator for driving and signal processing of an image sensor constituted by a CCD type solid-state image sensor or the like. It concerns the device.

[0002]

2. Description of the Related Art Among CCD driving and signal processing pulses, reset pulses (FR) for horizontal driving pulses (FH1, FH2), sampling pulses (FCDS, FS) for correlated double sampling (CDS), etc. Requires a high speed and a phase relationship of several ns. More specifically, the output signal of the CCD is output after a delay of several ns with respect to the phase of the horizontal CCD shift register driving pulses FH1 and FH2. When a single timing signal generating circuit drives a different CCD (for example, a pixel having a different number of pixels, a different imaging size, or the like) by a single timing signal generation circuit, a slight difference occurs. Therefore, delicate phase adjustment is required.

In order to remove reset noise from the output signal of the CCD, correlated double sampling is performed.
Also in this sampling pulse, the difference between the delay time from the input of the drive pulse of the horizontal CCD shift register to the output of the CCD and the time from the CCD output due to the difference in system design to the input to the correlated double sampling circuit. A time difference occurs, and in this case, fine phase adjustment is required.

Each of the general pulses, that is, horizontal drive pulses (FH1, FH2), reset pulse (FR), C
FIG. 4 shows the timing of the CD output signal and sampling pulses (FCDS, FS) for correlated double sampling. The phases of these high-speed pulses are designed in advance to be optimal values by simulation,
As described above, fine adjustment is required due to variations in the characteristics of the CCD and system design.

In order to solve such a problem, the following fine adjustment method has been conventionally adopted.

FIG. 5 shows an example of such a method in which a phase control data signal is externally supplied to a pulse generator 500 with a phase adjusting circuit. In the figure, a pulse 514 generated by a pulse generation circuit 513 is input to a first delay circuit 515, a second delay circuit 517, and a third delay circuit 519 connected in series. Also, the pulse generation circuit 513
Output pulse 514, and each delay circuit 515, 51
7 and each of the delayed pulses 5 which are output pulses from 519
16, 518 and 520 are input to the selector 521. On the other hand, the phase control data based on the phase control signal is input to the decoder 511, and by using the decoded signal 512, each of the pulses input to the selector 521 having a different delay amount is selected, so that the pulse phase is finely adjusted. Pulse output. As a means for generating an external phase control signal, a method of generating several bits of parallel data by a switch or the like, a method of generating serial data by using a microcomputer, or the like is used.

FIG. 6 shows another example, in which a CR integrator (variable resistor 605, capacitor 606) is externally connected to the timing IC 600 for phase adjustment. In the figure, a pulse 602 generated by a pulse generation circuit 601 is output through a buffer 603, and the output pulse 604 is output using an external CR integration circuit (consisting of a variable resistor 605 and a capacitor 606). And integrate. This integrated signal 607 is sent to the timing IC 60
0 is input again, the waveform is shaped again through the buffer 608, and a desired pulse output 609 is obtained. The fine adjustment of the pulse phase is performed by changing the constant (resistance value) of the integration circuit. FIG. 7 shows how the phase of the pulse obtained in this manner is delayed.

[0008]

When parallel data is used as an external phase control signal as described above for adjusting the phase of a high-speed pulse for driving a CCD, the number of input terminals for phase setting increases. . In addition, when performing finer adjustment, it is necessary to increase the number of stages of the delay circuit, and as a result, the number of input terminals increases, which causes a problem that miniaturization of the system is hindered.

On the other hand, when serial data is used as an external phase control signal, the problem of an increase in the number of input terminals can be solved, but it is necessary to prepare serial data separately outside. Generally, this serial data is created using a microcomputer for control, but it can be easily created in a system that uses a microcomputer for digital signal processing, but in analog signal processing, it is necessary to create serial data externally. Is necessary, and there is a problem in miniaturization and cost reduction of the system.

Further, when a phase adjustment is performed by adding an external CR integrating circuit, in order to integrate a high-frequency pulse,
The current consumption increases (for driving the output buffer and driving the load of the CR). Also, since the number of input / output signals increases,
The number of terminals increases. As a result, there are problems in miniaturization of the system and reduction in power consumption.

The present invention has been made to provide a pulse generator capable of solving the above-mentioned conventional problems.

[0012]

According to a first aspect of the present invention, there is provided a pulse generating apparatus including a pulse generating means and a plurality of delay circuits. Delay pulse generating means for receiving the output pulse and outputting a plurality of delay pulses having different phases,
A pulse selecting device for selecting and outputting one pulse from among the output pulses from the pulse generating means and the delayed pulse generating means based on the control signal. An input terminal for receiving a DC voltage of a predetermined level, and a control signal generating means for outputting the control signal for controlling the pulse selecting means based on the DC voltage of the predetermined level input from the input terminal are provided. It is characterized by the following.

According to a second aspect of the present invention, there is provided the pulse generator according to the first aspect.
A / D conversion means for A / D converting the input DC voltage and outputting digital data of a predetermined number of bits, and controlling the pulse selection means based on output data from the A / D conversion means. And a decoder for outputting a control signal, wherein the control signal generator is provided.

Further, in the pulse generator according to the third aspect of the present invention, in the pulse generator according to the first or second aspect, when the voltage of the input terminal is a power supply voltage or a ground voltage, Output a phase pulse,
Alternatively, the pulse output is stopped.

Further, the pulse generator of the present invention according to claim 4 is the pulse generator according to claim 3, wherein
It is characterized in that an input terminal with a pull-up resistor or a pull-down resistor is provided as the input terminal.

According to the pulse generator of the present invention,
It is possible to adjust the phase of the output pulse by providing only one DC voltage input terminal for one output pulse and without the need for external serial data creation means (control microcomputer, etc.). The system becomes smaller,
The cost can be reduced.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 3 shows a CCD for explaining the present invention.
FIG. 3 is a block diagram of a driving system, and a pulse generator (IC) 301 with a phase adjustment function according to the present invention is provided from outside.
DC input for pulse phase adjustment (FR phase adjustment DC input, FCDS phase adjustment DC input, and FS phase adjustment DC input
) Is input, and F is phase-adjusted by the DC input.
R, FCDS and FS, and FH1 and FH2 are C
It is output to a CD-type solid-state imaging device (IC) 302 and a correlated double sampling (CDS) IC 303.

FIG. 1 is a block diagram showing the internal configuration of a pulse generator (IC) 100 according to an embodiment of the present invention.
The present embodiment is implemented as the CCD driving pulse generator shown in FIG.
FR, FC phase-adjusted according to each input of FCDS phase adjustment DC input and FS phase adjustment DC input
It has the function of outputting DS and FS,
FIG. 1 shows only one pulse circuit.
In other words, two similar circuits are provided, but these are not shown. Further, the DC voltage input terminal in the present embodiment is configured as a terminal with a pull-up resistor.

A pulse generation circuit 103 in the pulse generation device
Each pulse of FR, FCDS or FS generated in 10
Reference numeral 4 denotes five delay circuits 105 to 113 connected in series.
And each of the delay circuits 105, 107, 109, 11
Output delay pulses 106, 108, 11 of 1 and 113
0, 112 and 114 and the output pulse 104 of the pulse generation circuit 103 are input to the selector 115, respectively.

On the other hand, the DC voltage applied to the phase control input terminal 118 is converted into a 3-bit digital data signal 102 by a built-in A / D converter 101. 3-bit digital data signal 1 converted by A / D converter 101
02 is decoded by the decoder 116, and a selector control signal 117, which is a decoded output signal, is input to the selector 115, and one of six types of high-speed pulses having different delay amounts is selected by the control signal 117. Is output.

When the DC voltage input to the phase control input terminal 118 is the power supply voltage or when the input terminal is open, the default phase (optimum phase) is used in a standard system (use environment). (Phase state). Further, when the DC voltage input to the phase control input terminal 118 is the ground voltage, the pulse output is stopped.

FIG. 2 shows a summary of the above contents.

That is, the maximum value (power supply voltage) of the input DC voltage is set to 5 V, and the 3-bit A / D converter 101
Are digital data D0, D1, and D2. Six types of pulses having different delay times are selected by this digital data. For example, when the input voltage is 3 V, D
0, D1. D2 becomes 0, 0, 1 and the third delay circuit 1
09 is selected.

The default phase is set to the second delay circuit 1
07, an output of 1.875 to 2.5 V is applied to the input terminal 118 for phase control, or an output of 4.375 to 5
When V is applied or when the phase control input terminal 118 is in the open state, the second delay circuit 10 is in the default phase.
Select 7.

Furthermore, 0 to 0
When 0.625 V is applied, the output is set to be stopped.

In the above description, the number of conversion bits of the A / D converter is 3 bits. However, the number of conversion bits is not limited to 3 bits, and may be increased or decreased as necessary. Needless to say.

In the above embodiment, the input terminal for phase control is a terminal with a pull-up resistor, but it goes without saying that the input terminal for phase control may be a terminal with a pull-down resistor.

Further, it goes without saying that the present invention can also be effectively implemented in a pulse generator requiring pulse phase adjustment other than the CCD drive pulse generator. .

[0030]

As described in detail above, according to the pulse generator of the present invention, only one DC voltage input terminal is provided for one output pulse, and serial data is generated externally. Without the need for means (control microcomputer etc.) and without increasing power consumption etc.
This makes it possible to adjust the phase of the output pulse, and can reduce the size, cost, and power consumption of the system. Therefore, according to the present invention, it is possible to easily manufacture a small-sized, low-power-consumption, high-quality CCD camera system or the like at low cost.

According to the pulse generator of the third and fourth aspects of the present invention, the power supply (ground) is connected to the DC voltage input terminal.
By applying a voltage or leaving the circuit open, the phase of the output pulse can be set to a default value, so that the number of components can be reduced and the system can be easily miniaturized. In addition, unnecessary pulse output in the system can be stopped, which is effective in reducing power consumption.

[Brief description of the drawings]

FIG. 1 is an internal block diagram of a pulse generator according to an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between a DC input voltage and a pulse output in the embodiment.

FIG. 3 is a block diagram of a CCD drive system for explaining the present invention.

FIG. 4 is a signal waveform diagram of a general CCD drive pulse.

FIG. 5 is an internal block configuration diagram of a conventional pulse generator.

FIG. 6 is a configuration diagram of another conventional pulse generator.

FIG. 7 is an explanatory diagram of a pulse delay in the pulse generator shown in FIG. 6;

[Explanation of symbols]

 Reference Signs List 100 pulse generator 101 A / D converter 103 pulse generator 105,..., 113 delay circuit 115 selector 116 decoder 118 phase control input terminal

Claims (4)

[Claims] 1. A delay pulse generator including a pulse generator, a plurality of delay circuits, receiving a pulse output from the pulse generator, and outputting a plurality of delay pulses having different phases, based on a control signal. A pulse selecting means for selecting and outputting one pulse from the output pulses from the pulse generating means and the delayed pulse generating means. An input terminal for receiving a voltage; and a control signal generating means for outputting the control signal for controlling the pulse selecting means based on the DC voltage of the predetermined level input from the input terminal. Pulse generator. 2. The pulse generator according to claim 1, wherein the input DC voltage is A / D-converted to output digital data of a predetermined number of bits, and the A / D converter. A pulse generator comprising: the control signal generator which comprises: a decoder for outputting the control signal for controlling the pulse selector based on output data from the converter. 3. The pulse generator according to claim 1, wherein a pulse of a default phase is output when the voltage of the input terminal is a power supply voltage or a ground voltage, or
A pulse generator, wherein a pulse output is stopped. 4. The pulse generator according to claim 3, wherein an input terminal with a pull-up resistor or a pull-down resistor is provided as the input terminal.