JP3915416B2 - Imaging apparatus and imaging element driving method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an imaging apparatus and an imaging element driving method using a solid-state imaging element such as a CCD (charge coupled device).
[0002]
[Prior art]
FIG. 5 shows a circuit configuration of a general digital (still) camera. In the figure, reference numeral 10 denotes a digital camera, and the digital camera 10 can set a recording mode and a reproduction mode. In the recording mode state, the CCD 12 arranged behind the lens 11 is scan-driven by a timing generator (TG) 13, a vertical driver 14, and a horizontal driver 15, and outputs a CCD output by photoelectric conversion for every fixed period on one screen. Output minutes.
[0003]
This CCD output is taken in as a voltage signal of an analog value in units of pixels by a sampling pulse from the timing generator 13 in the correlated double circuit (CDS) and the gain control (GC) circuit 16, and for each primary color component of RGB. After the gain is appropriately adjusted, it is sampled and held by the A / D converter 17 and converted into digital data.
[0004]
Color processing including pixel interpolation processing is performed on the digital data by the color processing circuit 18 to generate a digital luminance signal Y and color difference signals Cb and Cr.
[0005]
The color process circuit 18 performs DMA transfer of the generated luminance signal Y and color difference signals Cb and Cr to the DRAM 19 using the generated synchronization signal, memory write enable signal, and clock signal.
[0006]
After completing the DMA transfer of the luminance and color difference signals to the DRAM 19, the CPU 20 reads the luminance and color difference signals from the DRAM 19 and writes them into the VRAM 21.
[0007]
A digital video encoder (hereinafter abbreviated as “video encoder”) 22 periodically reads out the luminance and color difference signals from the VRAM 21 and outputs them to the chroma circuit 23.
[0008]
The chroma circuit 23 performs chroma processing on the transmitted signal to generate a video signal and outputs it to the display unit 24.
[0009]
The display unit 24 is composed of, for example, a backlit color liquid crystal display panel and its drive circuit, and is disposed on the back side of the camera body, and functions as an EVF (Electronic View Finder) in the recording mode. Thus, by performing display based on the video signal from the chroma circuit 23, an image based on the image information fetched from the CCD 12 at that time is displayed.
[0010]
Then, with the image at that time being displayed in real time as a monitor image on the display unit 24 as described above, the shutter keys in the plurality of keys constituting the key input unit 25 are operated at a timing when recording and storage are desired. Then, a trigger signal is generated.
[0011]
In response to the trigger signal, the CPU 20 immediately stops the path from the CCD 12 to the DRAM 19 after the DMA transfer to the DRAM 19 of the luminance and color difference signals for one screen captured from the CCD 12 at that time, and records and saves them. Transition to the state.
[0012]
In this record storage state, the CPU 20 writes the luminance and color difference signals for one frame written in the DRAM 19 to a unit called a basic block of 8 vertical pixels × 8 horizontal pixels for each of Y, Cb, and Cr components. Is read out and written into the JPEG circuit 26.
[0013]
The JPEG circuit 26 compresses the written signal by a process such as ADCT (Adaptive Discrete Cosine Transform), Huffman coding which is an entropy coding method, and the obtained code data is data of one image. The file is read out from the JPEG circuit 26 as a file, and is written into a flash memory 27 which is a non-volatile memory that is detachably mounted as a storage medium of the digital camera 10.
[0014]
Then, the CPU 20 activates the path from the CCD 12 to the DRAM 19 again upon completion of the compression processing of the luminance and color difference signals for one frame and the writing of all the compressed data to the flash memory 27.
[0015]
At this time, the CPU 20 also creates image data in which the number of constituent pixels of the original image data is substantially thinned out, and stores this in the flash memory 27 in association with the original image data as a preview image, also called a thumbnail image. Let
[0016]
In addition to the shutter key described above, the key input unit 25 includes a recording / re-mode switching key for switching between a recording (REC) mode and a reproduction (PLAY) mode, a mode key for selecting various shooting modes, and an image. Consists of cursor keys that specify each of the up / down / left / right directions and the “Enter” key for determining the selection contents for selection and designation of the focus adjustment position on the white balance screen. The signal is sent directly to the CPU 20.
[0017]
In the playback mode, the CPU 20 stops the path from the CCD 12 to the DRAM 19, and the CPU 20 reads the code data for one specific frame from the flash memory 27 in accordance with the operation of the image selection key or the like of the key input unit 25 and performs JPEG The luminance and color difference signals for one frame are developed and stored in the VRAM 21 in units of basic blocks of 8 vertical pixels × 8 horizontal pixels obtained by writing to the circuit 26 and performing the decompression process by the JPEG circuit 26. Then, the video encoder 22 outputs the luminance and color difference signals for one frame developed and stored in the VRAM 21 to the chroma circuit 23, and the original video signal is generated by the chroma circuit 23 and displayed on the display unit 24. .
[0018]
Thus, a detailed method for acquiring image data in the CCD 12 will be described next.
[0019]
FIG. 6 shows a schematic configuration of the CCD 12, and the CCD 12 is mainly composed of an exposure section E composed of a large number of pixels PX arranged in a matrix, and a vertical transfer path VT between these pixel columns.
[0020]
The electric charge obtained by exposure at the exposure unit E is transferred to the vertical transfer paths VT for each field, and further, three types of vertical transfers with different phases are performed on each vertical transfer path VT as shown in FIG. One line is transferred in the vertical (downward in the figure) direction by pulses V1 to V3.
[0021]
Then, the charge on the lowermost line of each vertical transfer path VT is transferred to one horizontal transfer path HT. The charges transferred to the horizontal transfer path HT are sequentially transferred in units of pixels in the horizontal direction until the next charge on the lowermost line of the vertical transfer path VT is transferred again. In the text and in the drawing, it is abbreviated as “FD amplifier” 31) and is output as CCD output to the correlated double circuit and gain control circuit 16 in the next stage.
[0022]
FIG. 8 shows an example of the configuration of the FD amplifier 31. The input of the reset gate RG to which the charge transferred from the horizontal transfer path HT is applied is connected to the other end of the capacitor C whose one end is grounded. The reset drain terminal is connected via a switch SW that is turned on / off in response to a reset pulse.
[0023]
Thus, in the FD amplifier 31, the internal capacitor C is fixed to a certain voltage by the reset pulse and then brought into a floating state, and then the pixel charges transferred from the horizontal transfer path HT are charged, thereby floating. The signal voltage of the pixel is obtained by taking the difference between the voltage across the capacitor C at the time and the voltage across the capacitor C when charging the pixel charge.
[0024]
FIG. 9 shows the operation timing in the FD amplifier 31. 9 (1) and 9 (2) are horizontal transfer pulses 1 and 2 which are supplied from the horizontal driver 15 and serve as a reference for the horizontal transfer operation, and the horizontal transfer pulse 1 obtained by inverting the horizontal transfer pulse 1 as shown in FIG. 2.
[0025]
Charges for one pixel are sent from the horizontal transfer path HT to the FD amplifier 31 in one cycle of the horizontal transfer pulses 1 and 2, and the FD amplifier 31 outputs a waveform signal corresponding to the charge amount.
[0026]
That is, at the timing of the falling edge of the horizontal transfer pulse 1 (the rising edge of the horizontal transfer pulse 2), charge accumulation in the capacitor C is started, and the voltage generated at both ends of the capacitor C is output to the outside through the buffer amplifier. By doing so, it is converted into an electric signal.
[0027]
After the accumulated charge is output to the outside as an electrical signal, the capacitor C is completely discharged at the rising edge of the horizontal transfer pulse 1 (falling edge of the horizontal transfer pulse 2) for each pixel transfer, to a certain voltage Vs. Fixed.
[0028]
FIG. 9 (3) exemplifies the waveform of the voltage signal output from the FD amplifier 31. The reset pulse shown in FIG. 9 (4) is fixed to the voltage Vs by the reset region a and the floating state of the voltage Vf. The reference region b is the data region c in which the charge amount corresponding to the luminance of the pixel is accumulated and becomes the voltage Vd at the timing of the fall of the horizontal transfer pulse 1 (rise of the horizontal transfer pulse 2). .
[0029]
In the correlated double circuit 16 that is the next stage of the FD amplifier 31, the falling timing of the reference sampling pulse shown in FIG. 9 (5) and the timing shown in FIG. 9 (6) with respect to the output waveform of the FD amplifier 31 described above. The voltage Vf of the reference area b and the voltage Vd of the data area c are obtained at each timing of the fall of the data sampling pulse shown, and the difference between them is obtained as an electric signal.
[0030]
Thus, as can be seen in FIG. 9, for one period of the horizontal transfer pulse, the first 1/4 period is the reset area a, the next 1/4 period is the floating reference area b, and the remaining 1 / period is the remaining 1 / period. Two periods are used as a data area c where actual charge is stored. Therefore, a stable voltage Vd can be obtained in the data area c by taking twice as much time as the reference area b.
[0031]
[Problems to be solved by the invention]
However, in the situation of digital still cameras, where the recent increase in the number of pixels of a CCD and a high-quality moving image shooting function at a high frame rate such as 30 [frames / second] are also required, The time required for the transfer and reading of charges per pixel performed by the FD amplifier 31 is also very short. This makes it difficult to obtain a stable voltage Vf particularly in the reference region b, depending on the time constant of the capacitor used.
[0032]
As a result, even if the stable voltage Vd can be obtained in the data area c, the necessary voltage signal is obtained by the difference between the two voltage values Vf and Vd, and therefore corresponds to the charge amount of the pixel. There arises a problem that it is difficult to obtain a voltage signal having an accurate pixel value.
[0033]
The present invention has been made in view of the above circumstances, and the object of the present invention is to always stably and accurately read out pixel values even if the readout time per pixel of the image sensor is shortened. It is an object of the present invention to provide an image pickup apparatus and an image pickup element driving method that can be used.
[0034]
[Means for Solving the Problems]
The invention of claim 1, wherein transfers charges accumulated in the exposed portion which is arranged in a matrix of a plurality of vertical transfer paths, transfer to the horizontal transfer path sequential single charge transfer to the plurality of vertical transfer paths Output the solid-state imaging device, and delay the duty ratio of the horizontal transfer pulse that controls the end timing of the reference region sandwiched between the reset region and the data region during the one-pixel transfer period in the horizontal transfer path of the solid-state imaging device and control means for varying the element, said control means varies the at least one of the duty ratio of the two said horizontal transfer pulses in the opposite phase relation, the imaging apparatus, characterized in that to match the cross-point is there.
[0035]
According to the second aspect of the present invention, the charges accumulated in the exposure units arranged in a matrix are transferred to a plurality of vertical transfer paths, and the charges transferred to the plurality of vertical transfer paths are sequentially transferred to a single horizontal transfer path. Control step of varying the duty ratio of the horizontal transfer pulse by the delay element for controlling the end timing of the reference area sandwiched between the reset area and the data area during one pixel transfer period in the horizontal transfer path of the solid-state image pickup device And the control step is to change the duty ratio of at least one of the two horizontal transfer pulses having an anti-phase relationship so that the cross points coincide with each other.
[0044]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment when the present invention is applied to a digital camera will be described with reference to the drawings.
[0045]
The circuit configuration of the entire digital camera and the configuration of the CCD are substantially the same as those in FIGS. 5 and 6 described above, and the same reference numerals are used for the same portions and their illustration and description are omitted.
[0046]
First, the basic operation contents in the FD amplifier 31 will be mainly described with reference to FIG.
[0047]
1 (1) and 1 (2) show horizontal transfer pulses 1 and 2 given from the horizontal driver 15 to the CCD 12, and the period itself is higher than that shown in FIGS. 9 (1) and 9 (2). This does not change and corresponds to the horizontal transfer period per pixel of the target CCD 12, but the duty ratio in one cycle can be arbitrarily varied within the range indicated by the arrow A in the figure.
[0048]
Thereby, as shown in FIG. 1 (3), the time width of the reference region b sandwiched between the reset region a and the data region c in the output waveform of the FD amplifier 31 can be expanded.
[0049]
Therefore, after resetting the FD amplifier 31 with the reset pulse shown in FIG. 1 (4), the timing R at which the reference voltage Vf is considered to be sufficiently stable in the floating state in the enlarged reference region b is shown in FIG. 1 (5). As shown in FIG. 4, the sampling is performed in synchronization with the fall of the reference sampling pulse.
[0050]
Thereafter, the data voltage Vd decreases corresponding to the amount of charge transferred also in the data region c, and the data sampling pulse falls as shown in FIG. This is sampled in synchronization with.
[0051]
Thus, an accurate pixel value can be obtained by obtaining the difference V between the reference voltage Vf and the data voltage Vd sampled in a stable state.
[0052]
FIG. 2 shows a configuration example of a circuit provided in the horizontal driver 15 'for generating the horizontal transfer pulses 1 and 2 that can vary the duty ratio as described above.
[0053]
In the figure, a reference clock CLK having a duty ratio of 1/2 having a period of 1/2 of the horizontal transfer period for one pixel from the timing generator 13 is directly applied to the 1/2 divider circuit 41 by 1/2. The signals are inverted through the inverter 43 and input to the circuit 42 as the clock CLKB.
[0054]
The 1/2 divider circuit 41 divides the reference clock CLK by 1/2 and sends it to the delay element 44 as the clock CLK1. The delay element 44 can arbitrarily set the delay time, and the delay output is output to the EX-OR circuit 45 and the EX-NOR circuit 46, respectively.
[0055]
Similarly, the ½ divider circuit 42 divides the reference clock CLKB inverted by the inverter 43 by ½ and sends it to the delay element 47 as the clock CLK2. The delay element 47 can also arbitrarily set the delay time, and the delay output is output to the EX-OR circuit 45 and the EX-NOR circuit 46, respectively.
[0056]
Accordingly, the logical output of the EX-OR circuit 45 is supplied to the FD amplifier 31 as the horizontal transfer pulse 1 and the logical output of the EX-NOR circuit 46 is supplied as the horizontal transfer pulse 2, respectively.
[0057]
The delay elements 44 and 47 are described as being capable of arbitrarily setting the delay time. However, the delay elements 44 and 47 have fixed values based on the number of constituent pixels of the CCD 12 to be driven, the time constant of the capacitor to be used, and other physical properties. The delay time may be set in advance.
[0058]
FIG. 3 shows the waveform of each processing signal in such a configuration of the horizontal driver 15 '. From the reference clock CLK as shown in FIG. 3 (1), the clocks CLK1 and CLK2 shown in FIGS. 3 (2) and 3 (3) are generated by the 1/2 frequency divider 41, the inverter 43 and the 1/2 frequency divider 42. Is generated.
[0059]
Therefore, for example, only the delay element 47 side gives a delay of time width D to the clock CLK2, and the delay element 44 does not give a delay to the clock CLK1, and thus the clock CLK1 delayed as necessary is provided. , 2, by using the EX-OR circuit 45 and the EX-NOR circuit 46, horizontal transfer pulses 1 and 2 with variable duty ratios as shown in FIGS. 3 (4) and (5) can be obtained. Become.
[0060]
As described above, since a horizontal transfer pulse with a variable duty ratio can be obtained with an arbitrary time width with a simple circuit configuration, the data area c as shown in FIG. It is possible to sufficiently expand the reference region b within a range where there is no error, and it is possible to always stably and accurately read out pixel values.
[0061]
In the above embodiment, it has been described that the time width of the reference region b is changed by changing the duty ratio of the horizontal transfer pulses 1 and 2 to obtain an optimum output voltage. However, the duty ratio is changed. The means is also effective in optimizing the cross point of two horizontal transfer pulses that are in opposite phase relation to each other.
[0062]
FIG. 4 exemplifies waveforms of such horizontal transfer pulses 1 and 2, and here, the rise and fall of the horizontal transfer pulses 1 and 2, in particular, by expanding the time axis (horizontal axis) of the rising and falling periods. The degree of change in voltage value during the fall period is highlighted.
[0063]
In general, the horizontal transfer pulses 1 and 2 having an opposite phase relationship are drive pulses generated to sequentially transfer charges in the horizontal direction in units of pixels on the horizontal transfer path HT in the CCD 12. Charges for pixels are transferred and sequentially output to the outside by the FD amplifier 31 described above.
[0064]
At this time, the horizontal transfer is performed so that the timing point (hereinafter referred to as “cross point”) at which the same voltage is applied at one rising edge and the other falling edge of the two pulses is the same timing as shown in FIG. All the charges on the path HT can be transferred to the next position without leaving any charge, and the transfer efficiency can be improved.
[0065]
In general, these two horizontal transfer pulses 1 and 2 have different drive currents depending on the characteristics of the CCD 12 to be used, and the values thereof become larger as the number of pixels increases. For this reason, the CCD 12 having a large number of pixels is often used by inserting a drive circuit for generating a high-voltage horizontal transfer pulse in the preceding stage. However, due to individual differences in the drive circuit, the CCD 12 is actually input to the CCD 12. In many cases, the cross points of the two horizontal transfer pulses 1 and 2 are slightly shifted.
[0066]
Therefore, by variably setting the delay amount in the delay elements 44 and 47 shown in FIG. 2 in order to compensate for the deviation of the cross points of the horizontal transfer pulses 1 and 2, a more optimal cross point can be obtained, The transfer efficiency on the horizontal transfer path HT can be improved reliably, and an image with high reproducibility can be obtained.
[0067]
Although the present embodiment has been described with respect to a case where the present invention is applied to a digital camera using a CCD as a solid-state imaging device, the present invention is not limited to this, and a CCD, a CMOS area sensor, or other solid-state imaging device is used. Needless to say, the present invention can be applied to an arbitrary object as a device for driving to obtain an image or a driving method thereof.
[0068]
In addition, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention.
[0069]
Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and described in the column of the effect of the invention. In a case where at least one of the obtained effects can be obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.
[0070]
According to the first aspect of the present invention, the voltage value in the floating state can be sufficiently stabilized even when the readout time per pixel of the image sensor is shortened by expanding the time width of the reference region. Therefore, it is possible to always read stable and accurate pixel values.
Further, since the end timing of the reference area is controlled by changing the duty ratio of the reference horizontal transfer pulse, the reference area can be easily controlled without performing complicated control.
In addition, it is possible to cope with an increase in the number of pixels of the image sensor only by adding a simple circuit.
In addition, it is possible to improve transfer efficiency in the horizontal transfer path and obtain an image with higher reproducibility.
[Brief description of the drawings]
FIG. 1 is a diagram showing basic operation contents mainly in an FD amplifier according to an embodiment of the present invention;
FIG. 2 is a block diagram showing a configuration example of a circuit for generating a horizontal transfer pulse according to the embodiment;
FIG. 3 is a timing chart showing waveforms of processing signals in the horizontal driver according to the embodiment;
FIG. 4 is a timing chart illustrating another waveform of the horizontal transfer pulse according to the embodiment;
FIG. 5 is a block diagram showing a circuit configuration of a general digital still camera.
6 is a diagram showing a detailed configuration of the CCD shown in FIG. 5;
7 is a view showing a waveform of a vertical transfer pulse applied to the CCD shown in FIG. 6;
8 is a diagram showing a circuit configuration of the FD amplifier in FIG. 6;
9 is a diagram showing a horizontal transfer pulse and a drive waveform during one pixel readout period in the FD amplifier of FIG. 8. FIG.
[Explanation of symbols]
10 ... Digital camera 11 ... Lens 12 ... CCD
13 ... Timing generator (TG)
14 ... Vertical driver 15, 15 '... Horizontal driver 16 ... Correlated double circuit and gain control circuit (CDS & GC)
17 ... A / D converter 18 ... color process circuit 19 ... DRAM
20 ... CPU
21 ... VRAM
22 ... Digital video encoder 23 ... Chroma circuit 24 ... Display unit 25 ... Key input unit 26 ... JPEG circuit 27 ... Flash memory 31 ... FD amplifier 41 ... 1/2 divider circuit 42 ... 1/2 divider circuit 43 ... Inverter 44 ... delay element 45 ... EX-OR circuit 46 ... EX-NOR circuit 47 ... delay element E ... exposure section HT ... horizontal transfer path PX ... pixel RG ... reset gate VT ... vertical transfer path

Claims (2)

A solid-state imaging device that transfers charges accumulated in the exposure units arranged in a matrix to a plurality of vertical transfer paths, and sequentially transfers the charges transferred to the plurality of vertical transfer paths to a single horizontal transfer path for output. ,
Control means for varying the duty ratio of a horizontal transfer pulse by a delay element for controlling the end timing of a reference area sandwiched between a reset area and a data area during a one-pixel transfer period in the horizontal transfer path of the solid-state imaging device. and,
The control means varies the duty ratio of at least one of the two horizontal transfer pulses having an antiphase relationship to match the cross point.
An imaging apparatus characterized by that. The charges accumulated in the exposed sections arranged in a matrix is transferred to a plurality of vertical transfer paths, of the solid-state imaging device and outputting the sequentially transferred to one horizontal transfer path of the charges transferred to the plurality of vertical transfer paths A control step of varying a duty ratio of a horizontal transfer pulse by a delay element for controlling an end timing of a reference area sandwiched between a reset area and a data area during a one-pixel transfer period in a horizontal transfer path;
The image pickup element driving method, wherein the control step varies a duty ratio of at least one of the two horizontal transfer pulses having an antiphase relationship so as to match a cross point .

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