JP2000294774A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sufficiently reduce the resistance of a gate and implement higher integration by narrowing the interval between the gate and the corresponding source/drain, in a method of manufacturing a semiconductor device. SOLUTION: A gate insulating film 23 is formed on an Si semiconductor substrate 21, and a first polycrystalline Si layer is formed and an impurity is introduced. Thereafter, a TiN etching stop layer 25, an impurity-containing polycrystalline Si layer and an SiN surface protection layer are laminated one upon another, and the SiN surface protection layer and the impurity- containing polycrystalline Si layer are etched to thereby form an SiN surface protection layer 27G and a second polycrystalline Si gate electrode 26G which are gate-patterned. Then, CoSi layers 28G are formed on the sidewalls of the gate electrode 26G, and the layer 25 and the first polycrystalline Si layer are etched, to thereby generate a TiN etching stop layer 25G and form a first polycrystalline Si gate electrode 24G which are gate-patterned.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device suitable for manufacturing a memory / logic embedded device.

[0002]

2. Description of the Related Art Generally, in order to realize a memory / logic mixed device, it is necessary to reduce the resistance of a gate. For this purpose, a salicide method is applied or a polycrystalline Si gate electrode is formed. Double gate (poly-metal) by stacking gate electrodes made of metal such as W
Gate).

Further, in order to highly integrate the memory section, it is necessary to make the distance between the gate and the source and drain electrode contact holes as small as possible.
Due to the problem of accuracy in the lithography technique, there is a case where the source and drain electrode contact openings are covered on the gate.

FIG. 6 is a cutaway side view showing a main part of a semiconductor device for explaining a conventional technique. Hereinafter, a manufacturing process will be described with reference to the drawings.

FIG. 6 (A) 6- (1) The structure shown in the figure is formed by applying a normal technique, but the main point is that an element isolation insulating layer (not shown) is formed on the Si semiconductor substrate 1.
To form A gate insulating film 2 made of SiO ₂ is formed. Polycrystalline Si layer, TiN layer, W on gate insulating film 2
Layer and a SiN layer, and then etched into a gate pattern to form polycrystalline Si gate electrodes 3G _{1 and} 3G ₂ ,
TiN barrier layers 4G _{1 and} 4G ₂ , W gate electrode 5G
_{1 and} 5G ₂ , SiN surface protective layer 6G _{1 and} 6G ₂
To form Incidentally, SiN surface protective layer 6G ₁ and 6G ₂
Addresses the case where the source and drain electrode contact openings to be formed later shift and cover the gate. LDD (lightly doped drain)
n) Form low impurity concentration regions 7 ₁ and 7 ₂ and low impurity concentration regions 8 ₁ and 8 ₂ in the structure. After forming a SiN layer on the entire surface, anisotropic etching is performed to form side walls 9. High impurity concentration regions 10 ₁ and 1 in LDD structure
O ₂ , the high impurity concentration region 11 is also formed. It is.

6 (B) 6- (2) An interlayer insulating layer 12 made of, for example, SiO ₂ is formed to cover the entire surface.

6- (3) Etching the interlayer insulating layer 12 to form a high impurity concentration region 11
An opening for an electrode contact is formed facing the substrate.

6- (4) High impurity concentration region 1 through the electrode contact opening
1 is formed.

In the semiconductor device formed as described above, there is no problem because the electrode contact opening is formed exactly corresponding to the high impurity concentration region 11 contacted by the metal wiring 13.

FIG. 7 is a cutaway side view showing a main part of a semiconductor device for explaining a conventional technique, in which an electrode contact opening is formed so as to be shifted from a high impurity concentration region 11. In FIG. 7, the same symbols as those used in FIG. 6 represent the same parts or have the same meaning.

As shown in the figure, even if the electrode contact opening is shifted from the high impurity concentration region 11 and formed over the gate, the SiN surface protection layer 6G _{1 is formed.}
Depending on the presence, things like metal wiring 13 is short-circuited with the gate electrode 5G ₁ does not occur.

As described above, the high impurity concentration region 1
In the case of forming the metal wiring 13 contacting the gate electrode ₁ , the gate is covered with the SiN surface protection layers 6 G ₁ and 6 G _{2 and the} like, and a technique for coping with the displacement of the electrode contact opening is provided by a self-aligned contact.
t: SAC).

As described above, the SAC is a very useful means for compensating the accuracy of the lithography technology having a limit. However, when this technology is adopted, the SAC is a technology for lowering the gate resistance. The salicide method, that is, the technique of selectively siliciding the gate cannot be used,
Therefore, in the current development of a memory / logic hybrid device, the technology of a double-structure gate in which a gate electrode made of a metal such as W is laminated on a polycrystalline Si gate electrode as shown in the drawing is the target.

However, when forming a double structure gate, a polycrystalline Si layer, a TiN layer, a W
It is very difficult to etch the layer and the SiN layer into a mesa having a gate pattern.

FIG. 8 is a fragmentary side view showing a semiconductor device at a key point in a process for explaining a problem in forming a double structure gate, and is used in FIGS. 7 and 8. The symbol and the same symbol represent the same part or have the same meaning.

8 (A) 8- (1) A gate insulating film 2 made of SiO ₂ having a thickness of 3 [nm] is formed on a Si semiconductor substrate 1 on which an element isolation insulating film (not shown) is formed. A polycrystalline Si layer 3 having a thickness of 100 [nm] 3 A TiN barrier layer 4 having a thickness of 5 [nm] 4 A W layer 5 having a thickness of 100 [nm] 5 An SiN surface protective layer 6 having a thickness of 100 [nm] is formed. Note that TiN, which is the material of the barrier layer 4, has excellent barrier properties even when thinned, and is conductive unlike SiN.

8 (B) 8- (2) The SiN protective layer 6 to the polycrystalline Si layer 3 are etched in a mesa shape of a gate pattern to form a SiN surface protective layer 6G, a W gate electrode 5G, and a TiN barrier layer 4G. Then, a polycrystalline Si gate electrode 3G is formed.

The state shown in the figure indicates that ideally good mesa etching has been performed, but this is not the case in practice.

8 (C) 8- (3) MOS (met) in a generation having a gate length of 0.1 [μm]
In an oxide semiconductor device, the thickness of the gate insulating film 2 is reduced to 3 [nm] or less. Therefore, when the mesa etching described in the above step 8- (2) is performed, the polycrystalline Si layer and the oxide layer are not combined. The etching rate ratio is required to be extremely high, and in the SiN surface protective layer / metal layer / polycrystalline Si layer structure, it is necessary to simultaneously etch the SiN surface protective layer / metal layer / polycrystalline Si layer.

However, there is almost no etching rate ratio between the metal layer and the polycrystalline Si layer, and the polycrystalline Si layer may be slightly etched during the etching of the metal layer. A distribution will occur in the thickness.

Therefore, when etching the polycrystalline Si layer after the etching of the metal layer is completed, it is necessary to make the over-etching longer than when only the polycrystalline Si layer is etched.

However, since the gate insulating film 2 is thin, it cannot play a role of stopping the etching, and even the underlying Si semiconductor substrate 1 penetrates through the gate insulating film 2 and is etched, as shown in FIG. Around the groove 1G
Is formed.

As described above, the groove 1 is formed in the Si semiconductor substrate 1.
When G is formed, a good source junction /
Of course, a drain junction cannot be formed, and it becomes impossible to produce an integrated circuit device.

[0024]

According to the present invention, for example, in manufacturing a memory / logic mixed device, it is possible to sufficiently reduce the resistance of the gate and to reduce the distance between the gate and the source / drain. So that high integration is possible.

[0025]

According to the present invention, the basic structure of a double-structure gate, namely, a gate insulating film / polycrystalline Si gate electrode / metal gate electrode / metal gate electrode in a SiN surface protection layer is referred to as a first structure. Basically, the mesa conversion is completed after substituting the second polycrystalline Si gate electrode and silicidating only the side wall of the second polycrystalline Si gate electrode during the mesa conversion of each layer.

In the basic structure of the double structure gate, as described in the description of the prior art, a TiN barrier layer is interposed between a polycrystalline Si gate electrode and a metal gate electrode. Is the same in the present invention.

Usually, the etching rate of polycrystalline Si is Ti
In the present invention, when each layer is mesaized into a gate pattern, the mesa from the SiN surface protective layer to the second polycrystalline Si gate electrode layer is significantly higher than N.
Etching stops reliably at the TiN barrier layer.

Therefore, the exposed side wall of the second polycrystalline Si gate electrode layer is silicidized using a metal such as Co, and then the remaining layers are mesa-etched, so that the etching is performed. S through the gate insulating film
An accident such as reaching the i semiconductor substrate is prevented.

The reason why this is possible is that Si
Mesa of N surface protection layer and second polycrystalline Si gate electrode
Etching stops reliably at the TiN barrier layer, and then
Etching is performed again to convert the TiN barrier layer and the first polycrystalline Si gate electrode into mesas, so that accurate etching control can be performed as compared with the case where the entire structure is etched at once.

As described above, in the method of manufacturing a semiconductor device according to the present invention, there are provided: (1) an element isolation insulating layer (for example, a field insulating layer 2);
2) forming a gate insulating film (eg, gate insulating film 23) in the active region of the Si semiconductor substrate (eg, Si semiconductor substrate 21) on which is formed, and then forming a first polycrystalline Si layer on the gate insulating film (For example, a step of forming a polycrystalline Si layer 24), a step of introducing an impurity into the first polycrystalline Si layer, and then at least a heat-resistant metal layer (for example, TiN) on the first polycrystalline Si layer. Etching stop layer 2
5) a step of sequentially forming a second polycrystalline Si layer (for example, an impurity-containing polycrystalline Si layer 26) and a surface protective layer (for example, a SiN surface protective layer 27), and then a surface protective layer and a second polycrystalline Si layer. A surface protection film (eg, a SiN surface protection layer 27) patterned by etching the crystalline Si layer and forming a gate pattern.
G) and a step of forming a second polycrystalline Si gate electrode (for example, a second polycrystalline Si gate electrode 26G), and then forming a silicide layer (for example, a CoSi layer) on a side wall of the second polycrystalline Si gate electrode. 28G);
The refractory metal layer and the first polycrystalline Si layer are then etched to form a gate pattern of the refractory metal layer (eg, a gate patterned TiN etch stop layer 25G).
And forming a first polycrystalline Si gate electrode (for example, first polycrystalline Si gate electrode 24G).

(2) In the step (1), in the step of forming a silicide layer on the side wall of the second polycrystalline Si gate electrode, the second polycrystalline Si gate electrode (for example, the second polycrystalline Si gate electrode) may be used. Removing the native oxide film from the side walls of the polycrystalline Si gate electrode 26G) and then forming a transition metal layer (eg, Co layer 28); and then reacting the transition metal with Si to form a silicide layer (eg, CoSi layer). 28G), a step of removing the unreacted transition metal layer, and a step of subsequently performing a heat treatment for lowering the resistance of the silicide layer. Features.

By adopting the above-mentioned means, the gate can be reduced in resistance to a practically sufficient degree, and when the stacked layers are formed into a mesa into a gate pattern, etching is performed by a gate insulating film. No problem occurs even if the Si semiconductor substrate is damaged by penetrating through the gate electrode, so that there is no problem even if the distance between the gate and the source / drain is reduced to achieve high integration. It is suitable for manufacturing a circuit device.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 to 5 are cutaway side views of a main part of a semiconductor device in a process step for explaining an embodiment of the present invention. It will be explained while doing.

FIG. 1 (A) 1- (1) By applying a normal technique, the Si semiconductor substrate 21 is formed.
The chemical vapor deposition (chemical vapor deposition) is performed by forming a recess in the isolation region between elements.
The field insulating layer 22 is formed by filling with SiO ₂ by an n: CVD method.

1- (2) By applying the thermal oxidation method, a SiO ₂ layer having a thickness of, for example, 3 [nm] is formed on the active region in the Si semiconductor substrate 21.
The gate insulating film 23 made of is formed.

1- (3) The thickness is, for example, 50 [n] by applying the CVD method.
m] is formed.

1- (4) By applying the ion implantation method, the ion acceleration energy is set to, for example, 3 keV and the dose is set to, for example, 1 × 10 ^15.
As [cm ⁻² ], boron ions are implanted into the polycrystalline Si layer 24. Here, since the p-channel transistor is used as an object, boron is used as an impurity.
Normally, phosphorus is used for a channel transistor.

1- (5) A TiN etching stop layer 25 having a thickness of, for example, 5 nm is formed on the polycrystalline Si layer 24 by applying a sputtering method.

1- (6) By applying the CVD method, an impurity-containing polycrystalline Si layer 26 having a thickness of, for example, 100 [nm] on the TiN etching stop layer 25 and a thickness of, for example, 50 [nm] ] S
The iN surface protection layer 27 is sequentially formed by lamination.

Referring to FIG. 1B, 1- (7) a resist process in the lithography technique, and
Reactive ion etching (rea) using an etching gas of CHF ₃ + CF ₄ + Ar (for SiN and Si)
By applying the active ion etching (RIE) method, the SiN surface protection layer 27 and the polycrystalline S
The i-layer 26 is etched into a gate pattern to form a SiN surface protection layer 27G and a second polycrystalline Si gate electrode 26G.
Is formed and then immersed in a resist stripper to remove the resist film.

2 (A) 2- (1) Second polycrystalline Si gate electrode 26G immersed in hydrofluoric acid
After removing the natural oxide film on the side surface, the thickness is, for example, 10 [nm] by applying the sputtering method.
Is formed, and a TiN layer 29 having a thickness of, for example, 30 [nm] is formed. Note that the TiN layer 29 plays a role in preventing oxidation of Co silicide.

2- (2) RTA (Rapid Thermal Anneal)
By applying the method, the temperature is, for example, 500 [° C.],
By performing a heat treatment for a time of, for example, 30 [seconds], the side wall of the second polycrystalline Si gate electrode 26G reacts with the Co layer 28 to generate a CoSi layer 28G.

FIG. 2 (B) 2- (3) TiN layer 29 and unreacted Co layer 28 immersed in sulfuric acid
Is removed to expose a part of the mesaized gate.
At this time, the remaining portion of the TiN etching stop layer 25 other than the portion immediately below the second polycrystalline Si gate electrode 26G is removed, so the remaining TiN etching stop layer is indicated by a symbol 25G.

2- (4) The temperature is set to, for example, 850 by applying the RTA method.
A heat treatment is performed in which [° C.] and [time] are, for example, 30 [seconds].

After completing this heat treatment, the second polycrystalline S
It has been measured that the i-gate electrode 26G has a resistance of 2.5 [Ω / □] when the gate length is 0.1 [μm].

3 (A) 3- (1) RI using CHF ₃ + CF ₄ + Ar as an etching gas
By applying the E method, the polycrystalline Si layer 24 is anisotropically etched using the SiN surface protective layer 27G as a mask to form a first polycrystalline Si gate electrode 24G.

3- (2) By applying the ion implantation method, the ion acceleration energy is set to 1 [keV] and the dose is set to 4 × 10 ^14, for example.
As [cm ⁻² ], BF ₂ ions are implanted using the SiN surface protective layer 27G and the field insulating layer 22 as a mask to form a low impurity concentration source region 30S and a low impurity concentration drain region 30D having an LDD structure.

3- (3) The thickness is, for example, 50 [n] by applying the CVD method.
m], an insulating layer made of SiN is formed. In addition, Si
N may be replaced by SiO ₂ .

3- (4) RI using CHF ₃ + CF ₄ + Ar as an etching gas
By applying the method E, the insulating layer formed in the step 3- (3) is anisotropically etched to form the side wall 31G covering the side surface of the gate.

3- (5) By applying the ion implantation method, the ion acceleration energy is, for example, 5 keV, and the dose is, for example, 2 × 10 ¹⁵
[Cm ^-2 ], the SiN surface protective layer 27G and the side
By implanting boron ions using the wall 31G and the field insulating layer 22 as a mask, the high impurity concentration source region 32S and the high impurity concentration drain region 32D having the LDD structure are formed.
To form

3- (6) By applying the RTA method, the temperature is set to, for example, 1000
A heat treatment is performed in which [° C.] and [time] are, for example, 10 [seconds].

3- (7) Thereafter, by applying a normal technique, formation of an interlayer insulating layer and the like, formation of electrodes and wiring, and the like are performed to complete the process.

FIGS. 4 and 5 are cutaway side views of a main part of a semiconductor device in a process step for explaining another embodiment of the present invention. Referring to FIGS. It will be explained while doing. 1 to 3 represent the same parts or have the same meanings, and the second polycrystalline Si gate electrode 26G has a CoSi film 2
The steps up to the formation of 8G are the same as in the embodiment described with reference to FIGS.

4 (A) 4- (1) By applying the CVD method, the thickness is, for example, 10 [n].
m] of an insulating layer made of SiO ₂ .

4- (2) RI using CHF ₃ + CF ₄ + Ar as an etching gas
By applying the method E, the insulating layer formed in the step 4- (1) is anisotropically etched to form the side walls 33 covering the side surfaces of the SiN surface protective layer 27G and the CoSi layer 28G.

4 (B) 4- (3) SiN surface protection layer by applying RIE method using BCl ₃ + HBr (for TiN) and CHF ₃ + CF ₄ + Ar (for Si) as etching gas Anisotropic etching of the TiN etching stop layer 25 and the polycrystalline Si layer 24 is performed by using the 27G and the side wall 33 as a mask, and the TiN etching stop layer 25G and the first polycrystalline Si gate electrode 24G which are gate-patterned are formed. Form.

4- (4) The wafer is set in an oxidation furnace, thermal oxidation is performed at a temperature of 800 ° C. for a time of 20 minutes, and a thick film is formed on the side surface of the first polycrystalline Si gate electrode 24G. An insulating film 24S made of SiO ₂ having a thickness of 10 [nm] is formed.

4- (5) By applying the ion implantation method, the ion acceleration energy is, for example, 1 keV and the dose is, for example, 4 × 10 ^14.
As [cm ⁻² ], BF ₂ ions are implanted using the SiN surface protective layer 27G and the field insulating layer 22 as a mask to form the low impurity concentration source region 30S and the low impurity concentration drain region 30D having the LDD structure.

FIG. 5 5- (1) The thickness is, for example, 50 [n] by applying the CVD method.
m], an insulating layer made of SiN is formed. In addition, Si
N may be replaced by SiO ₂ .

5- (2) RI using CF ₄ + CHF ₃ + Ar as an etching gas
By applying the method E, the insulating layer formed in the step 5- (1) is anisotropically etched to form the side wall 31G covering the side surface of the gate.

5- (3) By applying the ion implantation method, the ion acceleration energy is, for example, 5 keV and the dose is, for example, 2 × 10 ¹⁵
[Cm ^-2 ], the SiN surface protective layer 27G and the side
By implanting boron ions using the wall 31G and the field insulating layer 22 as a mask, the high impurity concentration source region 32S and the high impurity concentration drain region 32D having the LDD structure are formed.
To form

5- (4) The temperature is set to, for example, 1000 by applying the RTA method.
A heat treatment is performed in which [° C.] and [time] are, for example, 10 [seconds].

5- (5) Thereafter, by applying a normal technique, formation of an interlayer insulating layer and the like, formation of electrodes and wiring, and the like are performed to complete the process.

In the present invention, without being limited to the above-described embodiment, many other modifications can be realized.

For example, TiN used as an etching stop layer material can be replaced with WN, WSiN, MoN, TaN, and CN used as a silicide layer material.
oSi can be replaced by TiSi ₂ , PtSi, NiSi, and furthermore, Si used as a surface protective layer material
N can be replaced by SiO ₂ .

[0066]

According to the method of manufacturing a semiconductor device according to the present invention, a gate insulating film is formed in an active region of a Si semiconductor substrate, a first polycrystalline Si layer is formed, and a first polycrystalline Si layer is formed.
Impurities were introduced into the layer, at least a heat-resistant metal layer, a second polycrystalline Si layer, and a surface protective layer were laminated, and the surface protective film and the second polycrystalline Si layer were etched to form a gate pattern. Forming a surface protective film and a second polycrystalline Si gate electrode, forming a silicide layer on the side wall of the second polycrystalline Si gate electrode, etching the heat resistant metal layer and the first polycrystalline Si layer; To form a gate pattern of the heat-resistant metal layer and form a first polycrystalline Si gate electrode.

By adopting the above configuration, the gate can be reduced in resistance to a practically sufficient degree. Further, when each of the stacked layers is formed into a gate pattern, the gate insulating film is etched. No problem occurs even if the Si semiconductor substrate is damaged by penetrating through the gate electrode, so that there is no problem even if the distance between the gate and the source / drain is reduced to achieve high integration. It is suitable for manufacturing a circuit device.

[Brief description of the drawings]

FIG. 1 is a cutaway side view showing a main part of a semiconductor device in a process step for explaining an embodiment of the present invention;

FIG. 2 is a fragmentary side view showing a semiconductor device at a key point in a process for describing an embodiment of the present invention;

FIG. 3 is a fragmentary sectional side view showing a semiconductor device in a process key point for describing an embodiment of the present invention;

FIG. 4 is a fragmentary side elevational view showing a semiconductor device at a key step in the process for describing the embodiment of the present invention;

FIG. 5 is a fragmentary side view showing a semiconductor device in a process step for explaining the embodiment of the present invention;

FIG. 6 is a fragmentary side view showing a semiconductor device for explaining a conventional technique;

FIG. 7 is a fragmentary side view showing a semiconductor device for explaining a conventional technique;

FIG. 8 is a fragmentary side view showing a semiconductor device at a key point in a process for explaining a problem in producing a double structure gate.

[Explanation of symbols]

Reference Signs List 21 Si semiconductor substrate 22 Field insulating layer 23 Gate insulating film 24 Polycrystalline Si layer 24 G First polycrystalline Si gate electrode 24 Insulating film made of SiO ₂ 25 TiN etching stop layer 25 G Gate-patterned TiN etching stop layer 26 Impurity-containing polycrystalline Si layer 26G Second polycrystalline Si gate electrode 27 SiN surface protective layer 27G Gate-patterned SiN surface protective layer 28 Co layer 28G CoSi layer 29 TiN layer 30S Low impurity concentration source region of LDD structure 30D Low impurity concentration drain region of LDD structure 31G Side wall 32S High impurity concentration source region of LDD structure 32D High impurity concentration drain region of LDD structure 33 Side wall

 ──────────────────────────────────────────────────続 き Continued on front page F term (reference) 5F040 DA01 DA11 DC01 EA08 EA09 EC02 EC03 EC07 EC12 EF02 EF11 EK05 FA05 FA07 FA17 FA18 FA19 FB02 FC00 FC02 FC10 FC19 FC21 5F048 AA01 AB01 AB03 AC01 BA01 BB01 BB05 BB08 BB09 BB13 DA20 DA21 DA25 DA27

Claims (2)

[Claims] A step of forming a gate insulating film in an active region of a Si semiconductor substrate on which an element isolation insulating layer is formed; and a step of forming a first polycrystalline Si layer on the gate insulating film. Next, a step of introducing impurities into the first polycrystalline Si layer, and then, at least a heat-resistant metal layer, a second polycrystalline Si layer, and a surface protection layer are sequentially formed on the first polycrystalline Si layer. A step of etching the surface protective film and the second polycrystalline Si layer to form a gate-patterned surface protective film and a second polycrystalline Si gate electrode; Forming a silicide layer on the side wall of the crystalline Si gate electrode; and etching the refractory metal layer and the first polycrystalline Si layer to form a gate pattern of the refractory metal layer and perform the first Polycrystalline Si gate The method of manufacturing a semiconductor device characterized by comprising contains a step of forming a pole. 2. A process for forming a silicide layer on a side wall of a second polycrystalline Si gate electrode, comprising: removing a natural oxide film from a side wall of the second polycrystalline Si gate electrode; Forming a silicide layer by reacting the transition metal with Si; and then removing the unreacted transition metal layer. 2. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of performing a heat treatment for changing the resistance.