JP2000294601A - Mounting body for semiconductor device and mounting method therefor - Google Patents
Mounting body for semiconductor device and mounting method thereforInfo
- Publication number
- JP2000294601A JP2000294601A JP11102296A JP10229699A JP2000294601A JP 2000294601 A JP2000294601 A JP 2000294601A JP 11102296 A JP11102296 A JP 11102296A JP 10229699 A JP10229699 A JP 10229699A JP 2000294601 A JP2000294601 A JP 2000294601A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- filler
- circuit board
- resin composition
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29199—Material of the matrix
- H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00013—Fully indexed content
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
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- H01L2924/01005—Boron [B]
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- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H01L2924/01082—Lead [Pb]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/0665—Epoxy resin
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、主として高周波で
動作する半導体装置の実装体と、この半導体装置の実装
方法とに関する。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device package mainly operating at a high frequency and a method of mounting the semiconductor device.
【０００２】[0002]
【従来の技術】コンピュータの高速化に伴っては半導体
装置の高速動作が必要であり、半導体装置の実装体、い
わゆる半導体パッケージでは信号を高速伝送する必要が
あるため、近年においては、半導体パッケージの信号配
線を伝送線路として設計することが行われている。そし
て、このような設計では、セラミックや樹脂のような誘
電体材料を用いて作製された回路基板の信号配線が等価
的に特性インピーダンスを有する伝送線路として表され
ることになり、伝送線路ではインピーダンスのミスマッ
チが存在する地点で信号の反射が生じ、反射ノイズが発
生するため、信号配線の特性インピーダンスを制御する
必要があることになる。なお、信号配線の特性インピー
ダンスは構造的な寸法で決定されることになり、単純に
いえば、信号配線の幅や厚み、層間絶縁厚み、絶縁層の
誘電率などに依存している。2. Description of the Related Art With the speeding up of computers, high-speed operation of semiconductor devices is required. In a semiconductor device package, a so-called semiconductor package, it is necessary to transmit signals at high speed. 2. Description of the Related Art Signal wiring is designed as a transmission line. In such a design, signal wiring of a circuit board made of a dielectric material such as ceramic or resin is equivalently represented as a transmission line having characteristic impedance, and the transmission line has an impedance of impedance. Signal reflection occurs at the point where the mismatch exists, and reflection noise occurs, so that it is necessary to control the characteristic impedance of the signal wiring. It should be noted that the characteristic impedance of the signal wiring is determined by the structural dimensions, and simply depends on the width and thickness of the signal wiring, the thickness of the interlayer insulation, the dielectric constant of the insulating layer, and the like.
【０００３】しかしながら、半導体パッケージにおける
信号配線の数は入出力端子の増加によって飛躍的に増加
しており、信号配線を高密度配置する必要がある都合上
からおのずと信号配線の間隔を狭めなければならないの
が実情であり、現実的には、配線の間隔を狭めながら特
性インピーダンスを制御することが必要となる。そこ
で、特開平９−２４６４２５号公報で開示された構成、
つまり、回路基板上に形成されて隣接しあう信号配線間
に溝を設けた構成が採用される。すなわち、この構成に
おいては、図４で示すように、回路基板２１の所定位置
ごとに設けた台座２２間を溝２３とし、各台座２２上に
信号配線であるインナーリード２４を形成したものであ
り、比誘電率の小さい空気がインナーリード２４同士の
間に存在しているため、インナーリード２４の特性イン
ピーダンスを５０Ωに保ったままで配線間隔を狭めるこ
とが可能となっている。However, the number of signal wirings in a semiconductor package has increased dramatically due to an increase in the number of input / output terminals, and the interval between the signal wirings must be reduced due to the necessity of arranging the signal wirings at a high density. In reality, it is necessary to control the characteristic impedance while reducing the distance between the wirings. Therefore, the configuration disclosed in Japanese Patent Application Laid-Open No. 9-246425,
That is, a configuration in which a groove is provided between adjacent signal wirings formed on a circuit board is employed. That is, in this configuration, as shown in FIG. 4, a groove 23 is formed between the pedestals 22 provided at predetermined positions of the circuit board 21, and an inner lead 24 as a signal wiring is formed on each pedestal 22. Since air having a small relative permittivity exists between the inner leads 24, it is possible to narrow the wiring interval while maintaining the characteristic impedance of the inner leads 24 at 50Ω.
【０００４】[0004]
【発明が解決しようとする課題】ところで、半導体装置
の実装体である半導体パッケージの小型化と接続端子数
の増加とに伴っては接続端子同士の間隔が狭くなること
が避けられないため、最近では、半導体装置を回路基板
の入出力端子へと直接的に実装することによって実装面
積を小さくし、その効率化を図ることが考えられてい
る。そして、半導体装置をフェイスダウンで回路基板上
に実装した半導体装置の実装体であるとすれば、半導体
装置と回路基板との電気的接続が一括的に実行可能とな
り、実装面積を小さくし得ることとなるが、このような
構成を採用する場合には、半導体装置の電極パッドピッ
チを回路基板の接続端子ピッチと同様に微細化しておく
必要があることになる。However, as the size of the semiconductor package, which is the mounting body of the semiconductor device, and the number of connection terminals increase, it is inevitable that the distance between the connection terminals becomes narrower. Then, it is considered that the mounting area is reduced by directly mounting the semiconductor device on the input / output terminal of the circuit board, and the efficiency is improved. If the semiconductor device is a semiconductor device mounted face down on a circuit board, electrical connection between the semiconductor device and the circuit board can be performed collectively, and the mounting area can be reduced. However, when such a configuration is employed, it is necessary to make the electrode pad pitch of the semiconductor device finer in the same manner as the connection terminal pitch of the circuit board.
【０００５】すなわち、従来の形態にかかる半導体パッ
ケージでは図５のような構成が採用されており、このよ
うな構成を実現する際の実装方法としては、半導体装置
１１のパッドといわれる端子電極１２上にワイヤボンデ
ィング法またはめっき法による突起電極１３を形成して
おいたうえ、突起電極１３と回路基板１４の信号配線で
ある接続端子１５とを導電性接着剤（図示省略）でもっ
て互いに接続することによって半導体装置１１を回路基
板１４上に実装することが行われる。そして、この際、
具体的には、突起電極１１の接続面上に導電性接着剤を
転写しておき、突起電極１１と接続端子１５とを位置合
わせした後、導電性接着剤を硬化させたうえで突起電極
１１と接続端子１５とを接続することが実行されてい
る。なお、図５では、符号１６が導電性接着剤による接
続部分を示している。That is, the configuration shown in FIG. 5 is adopted in the semiconductor package according to the conventional form, and a mounting method for realizing such a configuration is to mount on the terminal electrode 12 called a pad of the semiconductor device 11. The bump electrodes 13 are formed by wire bonding or plating, and the bump electrodes 13 and the connection terminals 15 serving as signal wires of the circuit board 14 are connected to each other with a conductive adhesive (not shown). Thereby, the semiconductor device 11 is mounted on the circuit board 14. And at this time,
Specifically, after the conductive adhesive is transferred onto the connection surface of the bump electrode 11, the bump electrode 11 is aligned with the connection terminal 15, and the conductive adhesive is cured before the bump electrode 11 is hardened. And the connection terminal 15 are executed. In FIG. 5, reference numeral 16 indicates a connection portion using a conductive adhesive.
【０００６】さらに、引き続き、半導体装置１１及び回
路基板１４間の間隙を封止して導電性接着剤による接続
部分１６を補強する必要上、液状の樹脂組成物１７を充
填したうえで硬化させることが実行される。そして、こ
の際における樹脂組成物１７は樹脂１８及びフィラー１
９を含有したものであり、フィラー１９は均一状態とな
って分散している。なお、樹脂組成物１７の有する比誘
電率は、樹脂１８及びフィラー１９の成分比と各々の比
誘電率とに基づいたうえで一意的に決定されることにな
っており、フィラー１９の比誘電率が樹脂１８の比誘電
率よりも大きい場合には、フィラー１９の成分比が上昇
するのに従って樹脂組成物１７の有する比誘電率が大き
くなる。Further, since it is necessary to seal the gap between the semiconductor device 11 and the circuit board 14 to reinforce the connection portion 16 with a conductive adhesive, the liquid resin composition 17 is filled and cured. Is executed. In this case, the resin composition 17 includes the resin 18 and the filler 1.
9, and the filler 19 is dispersed in a uniform state. The relative dielectric constant of the resin composition 17 is uniquely determined based on the component ratio of the resin 18 and the filler 19 and the relative dielectric constant of each of them. When the ratio is higher than the relative dielectric constant of the resin 18, the relative dielectric constant of the resin composition 17 increases as the component ratio of the filler 19 increases.
【０００７】しかしながら、従来のような半導体装置の
実装体であり、かつ、実装方法である限りは、回路基板
１４に形成されて隣接しあう接続端子１５同士の間隔が
極めて狭くなっているため、これら接続端子１５同士間
の寄生成分、つまり、配線間容量が大きくなる結果とし
てクロストークノイズが増大するという不都合が生じる
ことになっていた。そして、半導体装置１１及び回路基
板１４間に介装された樹脂組成物１７の比誘電率を調整
することによってクロストークノイズの低減を図ること
も考えられているが、フィラー１９が均一状態で分散し
ている樹脂組成物１７の比誘電率を全体的として調整す
ることを行ってもクロストークノイズの十分な低減を実
現することはできていないのが実状である。However, as long as the conventional semiconductor device is mounted and the mounting method is used, the interval between adjacent connection terminals 15 formed on the circuit board 14 is extremely small. The parasitic component between these connection terminals 15, that is, a problem that the crosstalk noise increases as a result of an increase in the capacitance between the wirings is caused. It is also considered that the relative dielectric constant of the resin composition 17 interposed between the semiconductor device 11 and the circuit board 14 is adjusted to reduce crosstalk noise, but the filler 19 is dispersed in a uniform state. Even if the relative permittivity of the resin composition 17 is adjusted as a whole, the crosstalk noise cannot be sufficiently reduced.
【０００８】本発明は、このような不都合に鑑みて創案
されたものであって、クロストークノイズの十分な低減
を図ることが可能な構成とされた半導体装置の実装体
と、半導体装置の実装方法とを提供することを目的とし
ている。SUMMARY OF THE INVENTION The present invention has been made in view of the above-described inconveniences, and has a semiconductor device mounting structure and a semiconductor device mounting structure capable of sufficiently reducing crosstalk noise. The method is intended to provide.
【０００９】[0009]
【課題を解決するための手段】本発明の請求項１にかか
る半導体装置の実装体は、半導体装置をフェースダウン
で回路基板上に実装し、比誘電率の異なる２種の物質を
含有した封止物質でもって半導体装置及び回路基板間の
間隙を封止してなるものであり、半導体装置及び回路基
板間の間隙を封止した封止物質の回路基板側には、比誘
電率のより小さな物質を位置させていることを特徴とす
る。According to a first aspect of the present invention, there is provided a package for a semiconductor device, wherein the semiconductor device is mounted face down on a circuit board, and a package containing two kinds of substances having different dielectric constants is contained. A sealing material that seals the gap between the semiconductor device and the circuit board with a sealing material. The sealing material that seals the gap between the semiconductor device and the circuit board has a smaller relative dielectric constant on the circuit board side. It is characterized in that a substance is located.
【００１０】本発明の請求項２にかかる半導体装置の実
装体は、半導体装置をフェースダウンで回路基板上に実
装し、樹脂及びフィラーを含有した樹脂組成物で半導体
装置及び回路基板間の間隙を封止してなるものであっ
て、樹脂組成物に含有されたフィラーは樹脂よりも小さ
な比誘電率を有しており、半導体装置及び回路基板間の
間隙を封止した樹脂組成物中の回路基板側に位置してい
ることを特徴とする。この構成であれば、樹脂組成物全
体のうちでも回路基板近傍における比誘電率が半導体装
置近傍における比誘電率よりも実質的に小さくなってい
るため、フィラーが均一分散している場合に比べると、
回路基板の実装面からの影響が少なくなる結果としてク
ロストークノイズが低減するという利点が確保される。According to a second aspect of the present invention, a semiconductor device is mounted on a circuit board face down, and a gap between the semiconductor device and the circuit board is filled with a resin composition containing a resin and a filler. A circuit in the resin composition, wherein the filler contained in the resin composition has a relative permittivity smaller than that of the resin, and seals a gap between the semiconductor device and the circuit board. It is characterized by being located on the substrate side. With this configuration, the relative permittivity in the vicinity of the circuit board is substantially smaller than the relative permittivity in the vicinity of the semiconductor device even in the entire resin composition, so that compared to the case where the filler is uniformly dispersed. ,
The advantage that the influence from the mounting surface of the circuit board is reduced as a result, the crosstalk noise is reduced is secured.
【００１１】本発明の請求項３にかかる半導体装置の実
装体は請求項２に記載したものであり、樹脂組成物に含
有されたフィラーは樹脂よりも大きな密度を有している
ことを特徴とする。本発明の請求項４にかかる半導体装
置の実装体は請求項２または請求項３に記載したもので
あり、フィラーはテフロンからなることを特徴としてい
る。本発明の請求項５にかかる半導体装置の実装体は請
求項２ないし請求項４のいずれかに記載したものであ
り、フィラーは中空状であることを特徴とする。According to a third aspect of the present invention, there is provided a semiconductor device package according to the second aspect, wherein the filler contained in the resin composition has a higher density than the resin. I do. A semiconductor device package according to a fourth aspect of the present invention is the semiconductor device according to the second or third aspect, wherein the filler is made of Teflon. A semiconductor device package according to a fifth aspect of the present invention is the semiconductor device according to any one of the second to fourth aspects, wherein the filler is hollow.
【００１２】本発明の請求項６にかかる半導体装置の実
装体は、半導体装置をフェースダウンで回路基板上に実
装し、樹脂及びフィラーを含有した樹脂組成物で半導体
装置及び回路基板間の間隙を封止してなるものであっ
て、樹脂組成物に含有されたフィラーは樹脂よりも大き
な比誘電率を有しており、半導体装置及び回路基板間の
間隙を封止した樹脂組成物中の半導体装置側に位置して
いることを特徴とする。この構成であれば、樹脂組成物
全体のうちでも半導体装置近傍における比誘電率が回路
基板近傍における比誘電率よりも実質的に大きくなって
いるため、フィラーが均一分散している場合に比べる
と、回路基板の実装面からの影響が少なくなる結果とし
てクロストークノイズが低減するという利点が確保され
る。According to a sixth aspect of the present invention, there is provided a semiconductor device package comprising a semiconductor device mounted face-down on a circuit board, and a gap between the semiconductor device and the circuit board formed of a resin composition containing a resin and a filler. A filler contained in the resin composition, wherein the filler contained in the resin composition has a higher relative permittivity than the resin, and the semiconductor in the resin composition sealing the gap between the semiconductor device and the circuit board. It is characterized by being located on the device side. With this configuration, the relative permittivity in the vicinity of the semiconductor device is substantially higher than the relative permittivity in the vicinity of the circuit board in the entire resin composition, so that compared to the case where the filler is uniformly dispersed. In addition, the effect of reducing the influence from the mounting surface of the circuit board is reduced, so that the advantage that the crosstalk noise is reduced is secured.
【００１３】本発明の請求項７にかかる半導体装置の実
装体は請求項６に記載したものであり、樹脂組成物に含
有されたフィラーは樹脂よりも小さな密度を有している
ことを特徴とする。本発明の請求項８にかかる半導体装
置の実装体は請求項６または請求項７に記載したもので
あり、フィラーはシリカからなることを特徴とする。According to a seventh aspect of the present invention, there is provided a semiconductor device package according to the sixth aspect, wherein the filler contained in the resin composition has a smaller density than the resin. I do. An eighth aspect of the present invention is a semiconductor device package according to the sixth or seventh aspect, wherein the filler is made of silica.
【００１４】本発明の請求項９にかかる半導体装置の実
装方法は、半導体装置をフェースダウンで回路基板上に
実装する工程と、樹脂及び樹脂よりも比誘電率の小さい
フィラーを含有して未硬化状態にある樹脂組成物を半導
体装置及び回路基板間の間隙に充填する工程と、フィラ
ーが樹脂組成物中の回路基板側に位置する状態としたう
えで樹脂組成物を硬化させる工程とを含んでいることを
特徴とする。この方法であれば、請求項１にかかる構成
とされた半導体装置の実装体を容易に作製し得るという
利点が確保される。According to a ninth aspect of the present invention, there is provided a method of mounting a semiconductor device, comprising the steps of mounting the semiconductor device face down on a circuit board, and including a resin and a filler having a relative permittivity smaller than that of the resin. Filling the gap between the semiconductor device and the circuit board with the resin composition in a state, and curing the resin composition after the filler is positioned on the circuit board side in the resin composition. It is characterized by being. According to this method, the advantage that the package of the semiconductor device having the structure according to claim 1 can be easily manufactured is secured.
【００１５】本発明の請求項１０にかかる半導体装置の
実装方法は、半導体装置をフェースダウンで回路基板上
に実装する工程と、樹脂及び樹脂よりも比誘電率の大き
いフィラーを含有して未硬化状態にある樹脂組成物を半
導体装置及び回路基板間の間隙に充填する工程と、フィ
ラーが樹脂組成物中の半導体装置側に位置する状態とし
たうえで樹脂組成物を硬化させる工程とを含んでいるこ
とを特徴とする。この方法であれば、請求項２にかかる
構成とされた半導体装置の実装体を容易に作製し得ると
いう利点が確保される。According to a tenth aspect of the present invention, there is provided a method of mounting a semiconductor device, comprising: mounting the semiconductor device face down on a circuit board; Filling the gap between the semiconductor device and the circuit board with the resin composition in a state, and curing the resin composition after the filler is in a state positioned on the semiconductor device side of the resin composition. It is characterized by being. According to this method, the advantage that the package of the semiconductor device having the configuration according to claim 2 can be easily manufactured is secured.
【００１６】本発明の請求項１１にかかる半導体装置の
実装方法は請求項９または請求項１０に記載したもので
あり、樹脂組成物中の回路基板側または半導体装置側に
フィラーを位置させるに際しては、樹脂組成物に含有さ
れた樹脂とフィラーとの比重差を利用することを特徴と
している。本発明の請求項１２にかかる半導体装置の実
装方法は請求項９または請求項１０に記載したものであ
り、樹脂組成物中の回路基板側または半導体装置側にフ
ィラーを位置させるに際しては、樹脂組成物に含有され
た樹脂の粘度が高温下で急激に下がる性質を利用するこ
とを特徴としている。本発明の請求項１３にかかる半導
体装置の実装方法は請求項９または請求項１０に記載し
たものであり、樹脂組成物中の回路基板側または半導体
装置側にフィラーを位置させるに際しては、樹脂組成物
に含有されたフィラーを予め磁性体が内蔵されたものと
しておき、磁石によってフィラーが引き付けられる性質
を利用することを特徴としている。The method for mounting a semiconductor device according to claim 11 of the present invention is the method according to claim 9 or claim 10, wherein the filler is located on the circuit board side or the semiconductor device side in the resin composition. It is characterized by utilizing the difference in specific gravity between the resin and the filler contained in the resin composition. According to a twelfth aspect of the present invention, there is provided a method for mounting a semiconductor device according to the ninth or tenth aspect, wherein a resin composition is used when positioning a filler on a circuit board side or a semiconductor device side in a resin composition. It is characterized by utilizing the property that the viscosity of the resin contained in the material drops rapidly at high temperatures. A semiconductor device mounting method according to a thirteenth aspect of the present invention is the method according to the ninth or tenth aspect, wherein the filler is located on the circuit board side or the semiconductor device side in the resin composition. It is characterized in that a filler contained in an object is previously provided with a built-in magnetic material, and the property that the filler is attracted by a magnet is used.
【００１７】ところで、本発明よりも先行する特開平９
−２６６２２９号公報においては、半導体装置及び回路
基板、また、封止用の樹脂組成物それぞれの熱膨張係数
の相違に基づいて発生する熱応力の悪影響を回避すべ
く、樹脂組成物に含有された無機フィラーを熱膨張係数
の小さい部材側に位置させるようにして樹脂組成物を硬
化させることが既に提案されている。しかしながら、こ
の先行技術は、あくまでも無機フィラーの有する熱膨張
係数が樹脂よりも小さいことに着目してなされたもので
あるに過ぎず、このような技術を採用したとしてもクロ
ストークノイズを低減し得るか否かは全く不確定である
ため、先行技術及び本発明それぞれの基本的な技術思想
が互いに異なっていることは明らかである。By the way, Japanese Patent Application Laid-Open No.
In JP-266229A, the semiconductor device and the circuit board were contained in the resin composition in order to avoid the adverse effect of thermal stress generated based on the difference in the coefficient of thermal expansion of each of the sealing resin compositions. It has already been proposed to cure the resin composition so that the inorganic filler is positioned on the side of the member having a small coefficient of thermal expansion. However, this prior art is merely based on the fact that the thermal expansion coefficient of the inorganic filler is smaller than that of the resin, and crosstalk noise can be reduced even if such a technology is adopted. Since it is uncertain whether this is the case or not, it is clear that the basic technical ideas of the prior art and the present invention are different from each other.
【００１８】[0018]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１９】（実施の形態１）図１は実施の形態１にか
かる半導体装置の実装体を示す断面図であり、図２は実
施の形態１にかかる半導体装置の実装体を作製する際の
実装方法を示す工程断面図である。なお、半導体装置の
実装体における全体構成は従来の形態と基本的に異なら
ないので、図１及び図２において図５と互いに同一とな
る部品、部材には同一符号を付し、詳しい説明は省略す
る。(Embodiment 1) FIG. 1 is a cross-sectional view showing a mounted body of a semiconductor device according to Embodiment 1, and FIG. 2 is a mounting diagram for manufacturing a mounted body of the semiconductor device according to Embodiment 1. It is a process sectional view showing a method. Since the overall configuration of the semiconductor device package is basically the same as that of the conventional example, parts and members in FIGS. 1 and 2 which are the same as those in FIG. 5 are denoted by the same reference numerals, and detailed description is omitted. I do.
【００２０】本実施の形態１にかかる半導体装置の実装
体は、図１で示すように、半導体装置１１をフェースダ
ウンで回路基板１４上に実装しており、かつ、比誘電率
が３．３〜４のエポキシ樹脂である樹脂１と、比誘電率
が２．１以下のテフロンからなるフィラー２、つまり、
樹脂１よりも小さな比誘電率を有するフィラー２とを含
有した樹脂組成物３でもって半導体装置１１及び回路基
板１４間の間隙を封止してなる構成となっている。そし
て、この構成においては、樹脂組成物３に含有されたフ
ィラー２が、半導体装置１１及び回路基板１４間を封止
してなる樹脂組成物３内の回路基板１４側に集中したう
えで位置している。なお、樹脂組成物３に含有された樹
脂１がエポキシ樹脂であり、フィラー２がテフロンであ
る必然性があるわけではなく、フィラー２の有する比誘
電率の方が樹脂１の比誘電率よりも小さくなる組み合わ
せであれば、樹脂１及びフィラー２の材質が特定されな
いことは勿論である。As shown in FIG. 1, in the mounted body of the semiconductor device according to the first embodiment, the semiconductor device 11 is mounted face down on the circuit board 14 and the relative dielectric constant is 3.3. And a filler 2 made of Teflon having a relative dielectric constant of 2.1 or less, that is,
The gap between the semiconductor device 11 and the circuit board 14 is sealed with a resin composition 3 containing a filler 2 having a relative dielectric constant smaller than that of the resin 1. In this configuration, the filler 2 contained in the resin composition 3 is located after being concentrated on the circuit board 14 side in the resin composition 3 which seals the space between the semiconductor device 11 and the circuit board 14. ing. The resin 1 contained in the resin composition 3 is an epoxy resin, and the filler 2 does not necessarily have to be Teflon. The relative permittivity of the filler 2 is smaller than the relative permittivity of the resin 1. In the case of a certain combination, it goes without saying that the materials of the resin 1 and the filler 2 are not specified.
【００２１】すなわち、この際におけるフィラー２は、
樹脂組成物３が未硬化状態であるうちに回路基板１４側
へと集められた後、樹脂組成物３が硬化させられたのに
伴ってそのまま回路基板１４側に位置していることにな
る。そして、樹脂１よりも小さな比誘電率を有するフィ
ラー２が回路基板１４側に位置しているため、フィラー
２が均一分散している場合に比べると、回路基板１４上
に形成された信号配線である接続端子１５同士の間隔が
極めて狭くても隣接する接続端子１５間の寄生成分、つ
まり、配線間容量が大きくなり難くなり、その結果とし
てクロストークノイズは抑制される。なお、ここでのフ
ィラー２は、樹脂１よりも小さな比誘電率を有すると共
に、樹脂１よりも大きな密度を有していることが好まし
く、密度が２〜２．２のテフロンであれば、密度が１．
７〜２のエポキシ樹脂よりも密度が大きいこととなる。
また、フィラー２が中空状、例えば、中空の球形状とさ
れたものであってよく、内部に空気が封入されている場
合には比誘電率をさらに小さくすることが可能となる。That is, the filler 2 at this time is:
After being collected on the circuit board 14 side while the resin composition 3 is in an uncured state, it is located on the circuit board 14 side as the resin composition 3 is cured. Since the filler 2 having a relative permittivity smaller than that of the resin 1 is located on the circuit board 14 side, the signal wiring formed on the circuit board 14 is smaller than the case where the filler 2 is uniformly dispersed. Even if the distance between certain connection terminals 15 is extremely small, the parasitic component between adjacent connection terminals 15, that is, the capacitance between wirings is unlikely to increase, and as a result, crosstalk noise is suppressed. In addition, the filler 2 here has a relative dielectric constant smaller than that of the resin 1 and preferably has a higher density than that of the resin 1. Is 1.
This means that the density is higher than that of the epoxy resins 7 to 2.
In addition, the filler 2 may be hollow, for example, a hollow sphere, and when air is sealed therein, the relative dielectric constant can be further reduced.
【００２２】つぎに、実施の形態１にかかる半導体装置
の実装体を作製する際に採用される方法、つまり、半導
体装置の実装方法を図２に基づいて説明する。図１で示
した半導体装置の実装体を作製するに際しては、半導体
装置１１の端子電極１２上にワイヤボンディング法また
はめっき法による突起電極１３、いわゆるバンプを形成
し、かつ、半導体装置１１の突起電極１３と回路基板１
４、例えば、ガラスエホキシ基板である回路基板１４の
信号配線である接続端子１５とを導電性接着剤（図示省
略）で接続することにより、図２（ａ）で示すように、
半導体装置１１をフェースダウンで回路基板１４上に実
装することが行われる。その後、半導体装置１１及び回
路基板１４間の間隙を封止して接続部分１６を補強する
必要上、図２（ｂ）で示すように、未硬化状態で液状の
樹脂組成物３を半導体装置１１及び回路基板１４間の間
隙に充填したうえ、充填された樹脂組成物３を１５０℃
程度の温度で加熱することによって硬化させることが実
行される。Next, a method adopted when manufacturing the semiconductor device package according to the first embodiment, that is, a semiconductor device mounting method will be described with reference to FIG. In manufacturing the package of the semiconductor device shown in FIG. 1, a projection electrode 13, a so-called bump, is formed on the terminal electrode 12 of the semiconductor device 11 by a wire bonding method or a plating method, and the projection electrode of the semiconductor device 11 is formed. 13 and circuit board 1
4. For example, by connecting a connection terminal 15 which is a signal wiring of a circuit board 14 which is a glass ethoxy substrate with a conductive adhesive (not shown), as shown in FIG.
The semiconductor device 11 is mounted face down on the circuit board 14. After that, since it is necessary to seal the gap between the semiconductor device 11 and the circuit board 14 to reinforce the connection portion 16, as shown in FIG. 2B, the uncured liquid resin composition 3 is applied to the semiconductor device 11. And the gap between the circuit boards 14 is filled, and the filled resin composition 3 is heated to 150 ° C.
Curing is performed by heating at a moderate temperature.
【００２３】すなわち、未硬化状態である樹脂組成物３
に含有されたフィラー２は樹脂１中において均一分散し
ているが、フィラー２の有する比誘電率の方が樹脂１の
比誘電率よりも小さく、また、フィラー２の密度の方が
樹脂１の密度よりも大きいため、半導体装置１１と回路
基板１４との間隙に対して充填された樹脂組成物３中の
フィラー２は樹脂１との比重差に基づいて回路基板１４
側へと沈降することになり、フィラー２が回路基板１４
側へと沈降したままの状態下で樹脂組成物３は硬化され
ることになる。したがって、このままの状態下で樹脂組
成物３を硬化させると、図１で示した半導体装置の実装
体、つまり、樹脂１よりも小さな比誘電率を有するフィ
ラー２が樹脂組成物３中の回路基板１４側に位置してい
るためにクロストークノイズが抑制された半導体装置の
実装体が得られる。That is, the resin composition 3 in an uncured state
Is dispersed uniformly in the resin 1, but the relative dielectric constant of the filler 2 is smaller than that of the resin 1, and the density of the filler 2 is smaller than that of the resin 1. Since the density is higher than the density, the filler 2 in the resin composition 3 filled in the gap between the semiconductor device 11 and the circuit board 14
The filler 2 is settled to the side of the circuit board 14.
The resin composition 3 is cured while being settled to the side. Therefore, when the resin composition 3 is cured in this state, the mounted body of the semiconductor device shown in FIG. 1, that is, the filler 2 having a relative dielectric constant smaller than that of the resin 1 becomes the circuit board in the resin composition 3. Since it is located on the 14 side, a semiconductor device mounting body in which crosstalk noise is suppressed can be obtained.
【００２４】（実施の形態２）図３は実施の形態２にか
かる半導体装置の実装体を示す断面図であるが、その全
体構成は実施の形態１と基本的に異ならないので、図３
において図１と互いに同一となる部品、部材には同一符
号を付し、詳しい説明は省略する。また、実施の形態２
にかかる半導体装置の実装方法も図２で示した実施の形
態１と基本的には相違していないので、ここでは図２を
参照しながら実装方法を説明する。(Embodiment 2) FIG. 3 is a cross-sectional view showing a mounted body of a semiconductor device according to Embodiment 2, but since the overall configuration is basically not different from that of Embodiment 1, FIG.
In FIG. 1, the same components and members as those in FIG. 1 are denoted by the same reference numerals, and detailed description will be omitted. Embodiment 2
2 is basically the same as that of the first embodiment shown in FIG. 2, and the mounting method will be described here with reference to FIG.
【００２５】本実施の形態２にかかる半導体装置の実装
体は、図３で示すように、半導体装置１１をフェースダ
ウンで回路基板１４上に実装しており、かつ、比誘電率
が３．３〜４のエポキシ樹脂である樹脂１と、比誘電率
が４〜４．６のシリカからなるフィラー２、つまり、樹
脂１よりも大きな比誘電率を有するフィラー２とを含有
した樹脂組成物３でもって半導体装置１１及び回路基板
１４間の間隙を封止してなる構成となっている。そし
て、この際における実装体は、樹脂組成物３に含有され
たフィラー２が、半導体装置１１及び回路基板１４間を
封止してなる樹脂組成物３内の半導体装置１１側に集中
して位置した構成となっている。なお、ここでの樹脂組
成物３に含有された樹脂１がエポキシ樹脂であり、フィ
ラー２がシリカである必然性はなく、フィラー２の有す
る比誘電率の方が樹脂１の比誘電率よりも大きい組み合
わせであれば、樹脂１及びフィラー２の材質が特定され
ないことになる。As shown in FIG. 3, the mounted body of the semiconductor device according to the second embodiment has the semiconductor device 11 mounted face down on the circuit board 14 and has a relative dielectric constant of 3.3. A resin composition 3 containing a resin 1 which is an epoxy resin of No. 4 to 4 and a filler 2 made of silica having a relative dielectric constant of 4 to 4.6, that is, a filler 2 having a relative dielectric constant larger than that of the resin 1. Thus, the gap between the semiconductor device 11 and the circuit board 14 is sealed. In this case, the mounting body is located such that the filler 2 contained in the resin composition 3 is concentrated on the semiconductor device 11 side in the resin composition 3 which seals the space between the semiconductor device 11 and the circuit board 14. The configuration is as follows. Here, the resin 1 contained in the resin composition 3 is an epoxy resin, and the filler 2 does not necessarily have to be silica, and the relative permittivity of the filler 2 is higher than the relative permittivity of the resin 1. If it is a combination, the materials of the resin 1 and the filler 2 are not specified.
【００２６】すなわち、この際におけるフィラー２は、
樹脂組成物３が未硬化状態であるうちに半導体装置１１
側へと集められ、かつ、これらのフィラー２が半導体装
置１１側に位置した状態のままで樹脂組成物３が硬化さ
せられることになっている。そして、このような構成で
ある際には、樹脂１よりも大きな比誘電率を有するフィ
ラー２が半導体装置１１側に位置している結果としてフ
ィラー２よりも小さな比誘電率を有する樹脂１が回路基
板１４側に位置していることになり、フィラー２が均一
分散している場合に比べると、回路基板１４上に形成さ
れた信号配線である接続端子１５同士の間隔が極めて狭
くても隣接しあう接続端子１５間の寄生成分、つまり、
配線間容量が大きくはなり難くなる結果、クロストーク
ノイズは抑制されることになる。なお、ここでのフィラ
ー２は、樹脂１よりも大きな比誘電率を有すると共に、
樹脂１よりも小さな密度を有していることが好ましく、
密度が２．２〜２．６のシリカであれば、密度が１．７
〜２のエポキシ樹脂よりも密度が小さいこととなる。That is, the filler 2 at this time is:
While the resin composition 3 is in an uncured state, the semiconductor device 11
The resin composition 3 is to be cured while the filler 2 is collected on the side and the filler 2 is located on the semiconductor device 11 side. In such a configuration, the filler 2 having a relative dielectric constant larger than that of the resin 1 is located on the semiconductor device 11 side. As compared with the case where the fillers 2 are uniformly dispersed, the connection terminals 15 which are signal wirings formed on the circuit board 14 are adjacent to each other even if the interval between the connection terminals 15 is extremely small. The parasitic component between the corresponding connection terminals 15, that is,
As a result, it becomes difficult to increase the capacitance between wirings, so that crosstalk noise is suppressed. Here, the filler 2 has a higher relative dielectric constant than the resin 1, and
It is preferable to have a density smaller than that of the resin 1,
If the silica has a density of 2.2 to 2.6, the density is 1.7.
The density is smaller than that of the epoxy resins No. 2 to No. 2.
【００２７】つぎに、実施の形態１と同じ図２を参照し
ながら、実施の形態２にかかる半導体装置の実装体を作
製する際に採用される方法、つまり、半導体装置の実装
方法を説明する。すなわち、図３で示した半導体装置の
実装体を作製する際には、半導体装置１１の端子電極１
２上にワイヤボンディング法またはめっき法による突起
電極１３を形成し、かつ、半導体装置１１の突起電極１
３と回路基板１４の信号配線である接続端子１５とを導
電性接着剤（図示省略）でもって接続することにより、
図２（ａ）で示すように、半導体装置１１をフェースダ
ウンで回路基板１４上に実装することが行われる。その
後、半導体装置１１及び回路基板１４間の間隙を封止し
て接続部分１６を補強する必要上、図２（ｂ）で示すよ
うに、未硬化状態で液状の樹脂組成物３を半導体装置１
１及び回路基板１４間の間隙に充填したうえ、充填され
た樹脂組成物３を１５０℃程度の温度で加熱することに
よって硬化させることが実行される。Next, with reference to FIG. 2, which is the same as the first embodiment, a method adopted when manufacturing a semiconductor device mounted body according to the second embodiment, that is, a semiconductor device mounting method will be described. . That is, when manufacturing the package of the semiconductor device shown in FIG.
2, a protruding electrode 13 is formed by a wire bonding method or a plating method, and the protruding electrode 1 of the semiconductor device 11 is formed.
3 and a connection terminal 15 which is a signal wiring of the circuit board 14 by using a conductive adhesive (not shown),
As shown in FIG. 2A, the semiconductor device 11 is mounted face down on the circuit board 14. Then, since it is necessary to seal the gap between the semiconductor device 11 and the circuit board 14 to reinforce the connection portion 16, the uncured liquid resin composition 3 is applied to the semiconductor device 1 as shown in FIG.
After filling the gap between the substrate 1 and the circuit board 14, the filled resin composition 3 is cured by heating at a temperature of about 150 ° C.
【００２８】そして、この際にあっては、未硬化状態で
ある樹脂組成物３に含有されているフィラー２が樹脂１
中において均一分散しているにも拘わらず、フィラー２
の有する比誘電率の方が樹脂１よりも大きく、しかも、
フィラー２の密度の方が樹脂１の密度よりも小さいた
め、半導体装置１１と回路基板１４との間隙に対して充
填された樹脂組成物３中のフィラー２は樹脂１との比重
差に基づいて半導体装置１１側へと沈降することが起こ
る。そこで、フィラー２が半導体装置１１側へと沈降し
たままで樹脂組成物３を硬化させると、図３で示したよ
うに、樹脂１よりも大きな比誘電率を有するフィラー２
が樹脂組成物３中の半導体装置１１側に位置し、かつ、
フィラー２よりも比誘電率の小さな樹脂１が回路基板１
４側に位置した構成を有しており、その結果としてクロ
ストークノイズの抑制された半導体装置の実装体が得ら
れる。At this time, the filler 2 contained in the uncured resin composition 3 is mixed with the resin 1.
Filler 2 despite being uniformly dispersed in
Has a higher relative permittivity than the resin 1, and
Since the density of the filler 2 is smaller than the density of the resin 1, the filler 2 in the resin composition 3 filled in the gap between the semiconductor device 11 and the circuit board 14 is based on the specific gravity difference from the resin 1. Settling to the semiconductor device 11 side occurs. Then, when the resin composition 3 is cured while the filler 2 is settled to the semiconductor device 11 side, as shown in FIG.
Are located on the semiconductor device 11 side in the resin composition 3, and
Resin 1 having a lower relative dielectric constant than filler 2
It has a configuration located on the fourth side, and as a result, a semiconductor device mounted body with suppressed crosstalk noise can be obtained.
【００２９】ところで、以上説明した実施の形態１及び
実施の形態２にかかる半導体装置の実装方法にあって
は、樹脂組成物３中の回路基板１４側または半導体装置
１１側にフィラー２を位置させるに際し、樹脂組成物３
に含有された樹脂１とフィラー２との比重差を利用して
いるが、このような実装方法に限定されないことは勿論
である。すなわち、未硬化状態にある樹脂組成物３に含
有された樹脂１が、例えば、エポキシ樹脂のように、温
度が高くなるに連れて粘度が下がると同時に密度が下が
る性質を有する場合には、この性質を利用したうえで樹
脂１とフィラー２とを分離させることも可能であり、ま
た、図示省略しているが、樹脂組成物３に含有されたフ
ィラー２を予め磁性体が内蔵されたもの、例えば、金属
粉末の周囲をテフロンでコーティングしてなるものとし
ておき、磁石によってフィラー２が引き付けられる性質
を利用して樹脂組成物３中の回路基板１４側または半導
体装置１１側に位置させることも可能である。In the method of mounting the semiconductor device according to the first and second embodiments described above, the filler 2 is located on the circuit board 14 side or the semiconductor device 11 side in the resin composition 3. At the time, the resin composition 3
Although the difference in specific gravity between the resin 1 and the filler 2 contained in is used, it is a matter of course that the present invention is not limited to such a mounting method. That is, when the resin 1 contained in the resin composition 3 in an uncured state has a property that the viscosity decreases as the temperature increases and the density decreases at the same time as an epoxy resin, for example. It is also possible to separate the resin 1 and the filler 2 on the basis of the properties, and although not shown, the filler 2 contained in the resin composition 3 is pre-installed with a magnetic material, For example, the metal powder may be coated with Teflon around the periphery, and may be located on the circuit board 14 side or the semiconductor device 11 side in the resin composition 3 by utilizing the property that the filler 2 is attracted by the magnet. It is.
【００３０】[0030]
【発明の効果】以上説明したように、本発明にかかる半
導体装置の実装体によれば、半導体装置及び回路基板間
の間隙を封止する樹脂組成物のうちでも回路基板側に比
誘電率の小さなフィラーが位置し、または、半導体装置
側に比誘電率の大きなフィラーが位置しているので、回
路基板近傍の比誘電率が小さくなり、回路基板の実装面
からの影響が少なくなる結果としてクロストークノイズ
を抑制できるという効果が得られる。そして、本発明に
かかる半導体装置の実装方法によれば、上記構成とされ
た半導体装置の実装体を容易に作製し得ることになる。As described above, according to the semiconductor device package of the present invention, the relative permittivity of the resin composition sealing the gap between the semiconductor device and the circuit board is closer to the circuit board side. Since a small filler is located or a filler having a large relative permittivity is located on the semiconductor device side, the relative permittivity near the circuit board is reduced, and the influence from the mounting surface of the circuit board is reduced. The effect that the talk noise can be suppressed is obtained. According to the method of mounting a semiconductor device according to the present invention, a mounted body of the semiconductor device having the above configuration can be easily manufactured.
【図１】実施の形態１にかかる半導体装置の実装体を示
す断面図である。FIG. 1 is a cross-sectional view illustrating a mounted body of a semiconductor device according to a first embodiment;
【図２】実施の形態１にかかる半導体装置の実装体を作
製する際の実装方法を示す工程断面図である。FIG. 2 is a process cross-sectional view illustrating a mounting method when manufacturing the mounted body of the semiconductor device according to the first embodiment;
【図３】実施の形態２にかかる半導体装置の実装体を示
す断面図である。FIG. 3 is a sectional view showing a mounted body of the semiconductor device according to the second exemplary embodiment;
【図４】従来の形態にかかる回路基板を示す断面図であ
る。FIG. 4 is a cross-sectional view showing a circuit board according to a conventional mode.
【図５】従来の形態にかかる半導体装置の実装体を示す
断面図である。FIG. 5 is a cross-sectional view showing a package of a semiconductor device according to a conventional mode.
１ 樹脂 ２ フィラー ３ 樹脂組成物 １１ 半導体装置 １４ 回路基板 DESCRIPTION OF SYMBOLS 1 Resin 2 Filler 3 Resin composition 11 Semiconductor device 14 Circuit board
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０５Ｋ 1/18 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H05K 1/18
Claims (13)
上に実装し、比誘電率の異なる２種の物質を含有した封
止物質でもって半導体装置及び回路基板間の間隙を封止
してなる半導体装置の実装体であって、 半導体装置及び回路基板間の間隙を封止した封止物質の
回路基板側には、比誘電率のより小さな物質を位置させ
ていることを特徴とする半導体装置の実装体。1. A semiconductor in which a semiconductor device is mounted face-down on a circuit board and a gap between the semiconductor device and the circuit board is sealed with a sealing material containing two substances having different relative dielectric constants. A semiconductor device, wherein a substance having a smaller relative dielectric constant is located on a circuit board side of a sealing material that seals a gap between the semiconductor device and the circuit board. Implementation body.
上に実装し、樹脂及びフィラーを含有した樹脂組成物で
半導体装置及び回路基板間の間隙を封止してなる半導体
装置の実装体であって、 樹脂組成物に含有されたフィラーは樹脂よりも小さな比
誘電率を有しており、半導体装置及び回路基板間の間隙
を封止した樹脂組成物中の回路基板側に位置しているこ
とを特徴とする半導体装置の実装体。2. A semiconductor device package comprising: mounting a semiconductor device face down on a circuit board; and sealing a gap between the semiconductor device and the circuit board with a resin composition containing a resin and a filler. The filler contained in the resin composition has a relative permittivity smaller than that of the resin, and is located on the circuit board side in the resin composition that seals the gap between the semiconductor device and the circuit board. A packaged semiconductor device characterized by the following.
であって、 樹脂組成物に含有されたフィラーは、樹脂よりも大きな
密度を有していることを特徴とする半導体装置の実装
体。3. The package of the semiconductor device according to claim 2, wherein the filler contained in the resin composition has a higher density than the resin. .
体装置の実装体であって、 フィラーは、テフロン（登録商標）からなることを特徴
とする半導体装置の実装体。4. The package of the semiconductor device according to claim 2, wherein the filler is made of Teflon (registered trademark).
載した半導体装置の実装体であって、 フィラーは、中空状であることを特徴とする半導体装置
の実装体。5. The package of the semiconductor device according to claim 2, wherein the filler is hollow.
上に実装し、樹脂及びフィラーを含有した樹脂組成物で
半導体装置及び回路基板間の間隙を封止してなる半導体
装置の実装体であって、 樹脂組成物に含有されたフィラーは樹脂よりも大きな比
誘電率を有しており、半導体装置及び回路基板間の間隙
を封止した樹脂組成物中の半導体装置側に位置している
ことを特徴とする半導体装置の実装体。6. A semiconductor device package comprising a semiconductor device mounted face-down on a circuit board and a gap between the semiconductor device and the circuit board sealed with a resin composition containing a resin and a filler. The filler contained in the resin composition has a higher dielectric constant than the resin, and is located on the semiconductor device side in the resin composition that seals the gap between the semiconductor device and the circuit board. A packaged semiconductor device characterized by the following.
であって、 樹脂組成物に含有されたフィラーは、樹脂よりも小さな
密度を有していることを特徴とする半導体装置の実装
体。7. The package of the semiconductor device according to claim 6, wherein the filler contained in the resin composition has a density lower than that of the resin. .
体装置の実装体であって、 フィラーは、シリカからなることを特徴とする半導体装
置の実装体。8. The package of the semiconductor device according to claim 6, wherein the filler is made of silica.
上に実装する工程と、樹脂及び樹脂よりも比誘電率の小
さいフィラーを含有して未硬化状態にある樹脂組成物を
半導体装置及び回路基板間の間隙に充填する工程と、フ
ィラーが樹脂組成物中の回路基板側に位置する状態とし
たうえで樹脂組成物を硬化させる工程とを含んでいるこ
とを特徴とする半導体装置の実装方法。9. A step of mounting a semiconductor device on a circuit board face-down, and a step of applying a resin and an uncured resin composition containing a filler having a relative permittivity smaller than that of the resin between the semiconductor device and the circuit board. And a step of curing the resin composition after the filler is positioned on the circuit board side in the resin composition.
上に実装する工程と、樹脂及び樹脂よりも比誘電率の大
きいフィラーを含有して未硬化状態にある樹脂組成物を
半導体装置及び回路基板間の間隙に充填する工程と、フ
ィラーが樹脂組成物中の半導体装置側に位置する状態と
したうえで樹脂組成物を硬化させる工程とを含んでいる
ことを特徴とする半導体装置の実装方法。10. A step of mounting a semiconductor device face down on a circuit board, and a step of applying a resin and an uncured resin composition containing a filler having a relative dielectric constant larger than that of the resin between the semiconductor device and the circuit board. And a step of curing the resin composition after the filler is positioned on the side of the semiconductor device in the resin composition.
導体装置の実装方法であって、 樹脂組成物中の回路基板側または半導体装置側にフィラ
ーを位置させるに際しては、樹脂組成物に含有された樹
脂とフィラーとの比重差を利用することを特徴とする半
導体装置の実装方法。11. The method for mounting a semiconductor device according to claim 9, wherein when the filler is located on the circuit board side or the semiconductor device side in the resin composition, the filler is contained in the resin composition. A method of mounting a semiconductor device, wherein a difference in specific gravity between a resin and a filler is used.
導体装置の実装方法であって、 樹脂組成物中の回路基板側または半導体装置側にフィラ
ーを位置させるに際しては、樹脂組成物に含有された樹
脂の粘度が高温下で急激に下がる性質を利用することを
特徴とする半導体装置の実装方法。12. The method for mounting a semiconductor device according to claim 9 or claim 10, wherein when the filler is located on the circuit board side or the semiconductor device side in the resin composition, the filler is contained in the resin composition. A method for mounting a semiconductor device, wherein the method utilizes a property that the viscosity of a resin is rapidly lowered at a high temperature.
導体装置の実装方法であって、 樹脂組成物中の回路基板側または半導体装置側にフィラ
ーを位置させるに際しては、樹脂組成物に含有されたフ
ィラーを予め磁性体が内蔵されたものとしておき、磁石
によってフィラーが引き付けられる性質を利用すること
を特徴とする半導体装置の実装方法。13. The method for mounting a semiconductor device according to claim 9, wherein when the filler is located on the circuit board side or the semiconductor device side in the resin composition, the filler is contained in the resin composition. A method of mounting a semiconductor device, characterized in that a magnetic material is built in the filler in advance, and the property that the filler is attracted by a magnet is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10229699A JP4097054B2 (en) | 1999-04-09 | 1999-04-09 | Semiconductor device mounting body and semiconductor device mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10229699A JP4097054B2 (en) | 1999-04-09 | 1999-04-09 | Semiconductor device mounting body and semiconductor device mounting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000294601A true JP2000294601A (en) | 2000-10-20 |
| JP4097054B2 JP4097054B2 (en) | 2008-06-04 |
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ID=14323665
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10229699A Expired - Fee Related JP4097054B2 (en) | 1999-04-09 | 1999-04-09 | Semiconductor device mounting body and semiconductor device mounting method |
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| Country | Link |
|---|---|
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2005027223A1 (en) * | 2003-09-09 | 2007-11-08 | 三洋電機株式会社 | Semiconductor module including circuit element and insulating film, manufacturing method thereof and application thereof |
| JP2011077167A (en) * | 2009-09-29 | 2011-04-14 | Toshiba Corp | Mounting method for electronic component |
| JP2011091461A (en) * | 2011-02-10 | 2011-05-06 | Toshiba Corp | Apparatus and magnetic force application device |
| US8035212B2 (en) | 2009-03-25 | 2011-10-11 | Kabushiki Kaisha Toshiba | Semiconductor chip mounting body, method of manufacturing semiconductor chip mounting body and electronic device |
-
1999
- 1999-04-09 JP JP10229699A patent/JP4097054B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPWO2005027223A1 (en) * | 2003-09-09 | 2007-11-08 | 三洋電機株式会社 | Semiconductor module including circuit element and insulating film, manufacturing method thereof and application thereof |
| JP4688679B2 (en) * | 2003-09-09 | 2011-05-25 | 三洋電機株式会社 | Semiconductor module |
| US8304289B2 (en) | 2003-09-09 | 2012-11-06 | Sanyo Electric Co., Ltd. | Semiconductor module including circuit component and dielectric film, manufacturing method thereof, and application thereof |
| US8035212B2 (en) | 2009-03-25 | 2011-10-11 | Kabushiki Kaisha Toshiba | Semiconductor chip mounting body, method of manufacturing semiconductor chip mounting body and electronic device |
| JP2011077167A (en) * | 2009-09-29 | 2011-04-14 | Toshiba Corp | Mounting method for electronic component |
| CN102036496A (en) * | 2009-09-29 | 2011-04-27 | 株式会社东芝 | Installation method and device of an electronic component |
| JP2011091461A (en) * | 2011-02-10 | 2011-05-06 | Toshiba Corp | Apparatus and magnetic force application device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4097054B2 (en) | 2008-06-04 |
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