JP2000277927A - Wiring board, manufacture thereof, and electric apparatus comprising the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress substrate distortion caused by heat in a bonding process for electric parts, when an electric part to be provided on a wiring board is provided on the wiring board, by allowing the joint between the electric part and wiring board to comprise a region where statistically defect is easy to occur. SOLUTION: A broke line region A corresponds to a place, and its vicinity, where the outside corner of a semiconductor chip which is mounted on the wiring board is positioned, and the arrangement factor of a wiring pattern on the wiring board surface within the broken line region A comprising a region where a defect is easy to occur is set lower than the other part. With a wiring pattern where a redundant pattern is added to the wiring board, a redundant pattern B is arranged over the entire substrate so that the gap of wiring pattern is buried without shorting them. Or, a redundant pattern C is so arranged in the broken line region A that the gap of wiring pattern is buried to such extent as no shorting occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board, particularly a multi-layer printed wiring board, which has been subjected to a process for suppressing the distortion of the board caused by heat applied in a bonding step of an electric component, and a wiring board having the same. It relates to a manufacturing method. The present invention also relates to an electric device manufactured using such a wiring board, particularly to an electric device that is small enough to be portable.

[0002]

2. Description of the Related Art A conductor pattern of a wiring board on which electronic components are mounted is designed by a designer based on a product shape or an electric circuit design, and a copper-clad laminate is subjected to a subtractive method according to the pattern. (Subtrac
According to the active process, unnecessary portions of the copper foil are dissolved and removed with a chemical to obtain only necessary conductor patterns.

[0003] In order to manufacture a circuit board by mounting electronic components on the wiring board on which the predetermined conductor pattern is formed, soldering of the components is performed. In the case of mounting a chip component widely used in an electronic device, this soldering operation usually uses reflow soldering.

In the reflow soldering, as shown in FIG. 6, a circuit board 14 on which electronic components 13 are mounted on a wiring board 1 mounted on conveyor belts 12a and 12b is conveyed in a reflow furnace 10. Done by First, cream solder is applied to the pads of the wiring board 1, and then the terminal portions 15 of the electronic components 13 such as chip components are accurately positioned and mounted on the pads of the conductive layer of the printed wiring board 1. Then, while maintaining this state, the solder paste is passed through a reflow oven 10 such as an infrared oven or a hot blast oven to perform appropriate heating to melt the cream solder, complete the soldering, and fix the electronic component 13 at a predetermined position.

Since the temperature in the reflow furnace 10 becomes high, the insulating material constituting the wiring board 1 is softened, hardened, expanded or contracted, and the wiring board 1 is warped. The reflow furnace 10 can be removed from the reflow furnace 10 even at room temperature.
The deformation due to the warpage generated in the wiring board remains on the wiring board 1.
As a bonding method not using a reflow furnace, electric parts are chucked with a tool, and this tool is used for 150 to 18
There is also a method in which the electric component is heated to about 0 ° C., and the electric component is pressed against and fixed to the anisotropic conductive film disposed on the substrate.

[0006]

The circuit board manufactured by these processes is already warped in a state of a wiring board on which electronic parts and the like constituting the circuit board are not yet mounted, and the electronic parts are mounted. After soldering in a reflow furnace to perform the warping, the warpage further increases.

The warpage of the wiring board causes a defective solder connection between the mounted semiconductor lead and the wiring. When a solder connection failure occurs, the repair of the failure is a manual operation, so that a large number of man-hours are required. Further, in some cases, an accident occurs in which the wiring board warped in the mounting line falls from the mounting apparatus and the mounting line stops.

[0008] Circuit boards tend to be thinner and thinner due to demands for lighter products, and a printed circuit board having a lower board pressure tends to increase in the course of mounting electronic components. As a result, the occurrence rate of defects of the printed circuit board due to the warpage increases. For this reason, the warpage amount allowed by the automatic assembling apparatus when mounting the electronic components in the subsequent process may occur, and the mounting accuracy of the electronic components may not be obtained.

In order to prevent warpage in the reflow process,
In some cases, a warp prevention jig as shown in FIG. 7 is used. This jig is provided with warp preventing jigs 3a and 3b on both ends of the printed wiring board 1 in the direction of travel in the reflow furnace, or a warp preventing bar (not shown) is attached to the printed wiring board 1 itself. ing.

[0010] When a jig is used, it is difficult to automatically mount the jig, and a mounting worker is required. In addition, in terms of cost, the production cost of the prevention jig is disadvantageously increased. Also in the case where a warpage prevention bar is attached, the number of steps increases, which is not preferable. Also, the jig cannot suppress local deformation occurring on the substrate surface.

Further, even if no warpage occurs, the substrate is left in a high-temperature atmosphere during the reflow process, so that the entire substrate expands and shrinks after the reflow process. Defects considered to be due to this have also been confirmed.

In the method of performing bonding by chucking a bonding tool, the whole substrate does not warp, but local deformation may occur. The present invention has been made based on these circumstances, and it is an object of the present invention to provide a wiring board that can obtain a circuit board free from bonding failure even under the influence of heat in a reflow furnace or the like. . Another object of the present invention is to provide an electric device using a substrate in which bonding defects due to such thermal deformation are reduced.

[0013]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and has a conductive layer having at least a portion of a conductive member whose laying area is increased by a redundant pattern; A wiring board comprising: the conductive layer; and an insulating layer alternately laminated, wherein the part is configured such that, when the redundant pattern is not formed, an electric component to be provided on the wiring board is the wiring board. When provided on the wiring board, the wiring board is characterized by including a region where the electrical component and the wiring board are likely to be statistically defective in bonding.

A wiring board comprising a conductive layer having at least a portion of a conductive member whose laying area is increased by a redundant pattern, and an insulating layer alternately stacked with the conductive layer. Is a wiring board characterized by including a region where a portion corresponding to a corner of the outer shape of the electric component is located when the electric component is provided on the wiring board.

A wiring board comprising a conductive layer having at least a portion of a conductive member whose laying area is increased by a redundant pattern, and an insulating layer alternately stacked with the conductive layer. Is a wiring board characterized by including a region where a portion corresponding to a corner of the outer shape of the semiconductor device is located when the semiconductor device is provided on the wiring board.

At this time, it is preferable that the variation in the amount of the conductive member in the thickness direction of the conductive layer with respect to the center of the wiring substrate in the thickness direction is within a predetermined range. Further, the ratio of the area formed by the conductive member to the area formed by the plate surface is the ratio of the conductive member disposed, N is the number of conductive member layers, and the Z axis is an axis parallel to the plate thickness direction and having the origin at the center of the plate. and when,

[0017]

(Equation 3) Is preferably within a predetermined range where warpage is unlikely to occur.

It is preferable that the areas of the conductive layers located symmetrically in the thickness direction are equal. Further, it is preferable that the conductive member has a conductive layer having an area reduction hole. Also,
It is preferable to have a conductive layer having an area increasing pattern made of a conductive member.

The conductive member is preferably made of copper or a copper alloy. The present invention also provides a method for manufacturing a wiring board, comprising a laminating step of alternately laminating conductive layers and insulating layers each having at least a part of a conductive member whose laying area is increased by a redundant pattern. When the part is not formed with the redundant pattern,
A wiring board, wherein when an electric component to be provided on the wiring board is provided on the wiring board, a region where a failure is statistically likely to occur in joining between the electric component and the wiring board; It is a manufacturing method of.

A method for manufacturing a wiring board, comprising: a laminating step of alternately laminating conductive layers having at least a portion of a conductive member whose laying area is increased by a redundant pattern and insulating layers. Is a method for manufacturing a wiring board, wherein the part is a region where a part corresponding to a corner of an outer shape of the electric component is located when the electric component is provided on the wiring board.

The present invention also provides a method for manufacturing a wiring board, comprising: a laminating step of alternately laminating a conductive layer having at least a portion of a conductive member whose laying area is increased by a redundant pattern and an insulating layer. Is a method for manufacturing a wiring board, wherein the part is a region where a part corresponding to a corner of an outer shape of the semiconductor device is located when the semiconductor device is provided on the wiring board.

In this case, the conductive layer may include a step of laminating a conductive layer in which the variation in the amount of the conductive member in the thickness direction with respect to the center of the wiring substrate in the thickness direction is within a predetermined range. preferable.

The ratio of the area formed by the conductive member to the area formed by the plate surface is defined as the ratio of the conductive member provided, N is the number of conductive member layers, the Z axis is parallel to the plate thickness direction, and the center of the plate is defined as the origin. When the axis is

[0024]

(Equation 4) It is preferable to include a step of arranging a conductive layer in which the value is within a predetermined range in which warpage hardly occurs.

It is preferable to provide a conductive layer having an area equal to that of another conductive layer located symmetrically in the thickness direction. Further, it is preferable to dispose a conductive layer having an area reduction hole in the conductive member.

It is preferable to provide a conductive layer having an area increasing pattern made of a conductive member. Preferably, the conductive member is copper or a copper alloy. According to another aspect of the present invention, there is provided an electrical apparatus including: a circuit board including the wiring board as described above; and a housing that houses the circuit board.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS As a wiring board, there is not only a printed wiring board having both front and back surfaces of an insulating layer, but also a printed wiring board having a conductor pattern formed on an inner surface. Such a multilayer printed wiring board having a plurality of conductive layers is formed by a four-layer plate (a conductive pattern is formed by superposing four conductive patterns on a conductive layer) by an electronic computer or the like in accordance with miniaturization and high-density mounting of electronic devices. Thing), 6-layer board,
An eight-layer plate or more (for example, a 44-layer plate) has been put to practical use. Such poor bonding between the wiring board and the electric element is caused by thermal expansion of the board. It is considered that the bonding portion is peeled off when the substrate is warped or locally deformed due to thermal expansion. However,
Even if warpage occurs, bonding failure may not occur due to warpage but may occur due to the effect of stress caused by local deformation of the substrate. Therefore, two factors are always present. It does not have to be eliminated at the same time.

<Regarding "Warping" (Overall Deformation of Board)> Each of the conductive layers of the multilayer printed wiring board has a predetermined electric power in consideration of the installation space restriction due to the product shape, the heat radiation efficiency of the mounted components, and the like. The conductive pattern is designed based on the circuit. Usually, in these designs, the electric circuit design and the product shape design are prioritized, so that the printed wiring board is designed to prevent warpage after mounting the specified electronic components and assuming warpage after passing through a reflow furnace. Has not been done. For this reason, the pattern of each conductive layer of a normal multilayer printed wiring board does not consider the mutual relationship with respect to the warpage, and as a result, promotes the warpage of the entire multilayer printed wiring board.

The warpage of the printed wiring board caused by the reflow furnace is caused by a difference in thermal expansion coefficient due to a difference in material between the insulating layer and the conductive layer forming the printed wiring board, and the difference in expansion coefficient is different between the front and back of the board. This is caused by the stress generated. This factor is particularly remarkable in substrates for small electronic devices such as mobile phones that have been reduced in size and weight.

Therefore, in the case of a multilayer printed wiring board,
By performing a process of balancing the conductive layers having a symmetrical positional relationship with respect to the center layer, the stresses generated from the respective layers are cancelled, and the warpage can be prevented. The balance between the conductive layers can be obtained by optimizing the area of copper with respect to the substrate and its arrangement.

As a method of preventing warpage, a method of increasing the laying area of the wiring pattern of the conductive layer to increase the rigidity may be adopted. However, it is necessary to lay the copper material all over theoretically unnecessary portions. Is generated, resulting in waste of material. Further, the weight of the substrate increases, which is not preferable particularly as a substrate incorporated in a portable electric device. Therefore, it is preferable to arrange an appropriate amount of the copper material of the conductive layer by adjusting the balance of each layer.

As a method of balancing, there is a method of making the laying area of the copper material for each layer uniform so that warpage does not occur. However, this method becomes more difficult as a multilayer structure is formed. Therefore, the balance processing is performed by the following method.

FIG. 1 is a model for explaining the adjustment principle of the present invention, and is a cross-sectional view showing the mechanical relationship of a warped printed wiring board. In this model, the printed wiring board 1 includes four conductive layers made of copper, and the first to fourth conductive layers L1, L2, L3, and L4 are stacked with the insulating layer 2 interposed therebetween.

Now, when the printed circuit board 1 (hereinafter referred to as the board) warps in FIG. 1 with the board end curving downward, the bending moment can be expressed by equation (1). In addition,
The bending moment is a value per unit length in the Y-axis direction. The thermal stress is an X-direction component of the thermal stress.

[0035]

(Equation 5)

However, the Z axis is a reference axis (virtual axis) LC which is parallel to the normal line of the substrate and whose origin is the center in the thickness direction of the substrate. In general, the rigidity of the conductive layers L1 to L4 is sufficiently larger than the rigidity of the insulating layer 2, and therefore, if N is the number of conductive layers, the bending moment can be expressed by the equation (2).

[0037]

(Equation 6)

If the ratio of the area of the portion where the copper is disposed to the area of the surface formed by the substrate is defined as the residual copper ratio,
The elastic coefficient and linear expansion coefficient of the conductive layer are given by equations (3) and (4), and [Z coordinate of the center of the i-th copper foil layer] is given by equation (5).
-1) and (5-2).

[0039]

(Equation 7)

[0040]

(Equation 8) <When i = 1>

[0041]

(Equation 9) <When i = 2 to N>

[0042]

(Equation 10) Equations (3) and (4) are substituted into equation (2) representing the bending moment and rearranged into equation (6).

[0043]

[Equation 11]

In the equation (6), the expression is enclosed by [].
Is defined as [variation in the amount of copper in the thickness direction]. Therefore, [variation in the amount of copper in the thickness direction] can be expressed by equation (7).

[0045]

(Equation 12)

Equation (6) sandwiched by [] in equation (6),
That is, since the terms other than the expression (7) are physical quantities that cannot be set to 0, the amount of the copper material of the specific conductive layer is adjusted so that the expression (7) can be brought close to 0. The amount of copper material is determined. Actually, this term does not need to be 0, and is 0 to the extent that a defect due to warpage does not occur.
I just need to get closer to.

The discussion so far has been made on the case where the conductive member of the conductive layer is copper. However, [copper] is used as the [conductive member], [copper foil layer] is used as the [conductive layer], and [residual copper ratio] is used. ] Can be read as [arrangement ratio of conductive member], the same description can be made even when another conductive material is used.

<Regarding "Local Deformation" (Partial Deformation of Substrate)> By setting the balance of the thermal expansion coefficients so as to approach a predetermined reference, the warpage of the substrate is reduced. However, since the substrate as a whole expands uniformly, no warpage has occurred, and thermal expansion itself still occurs, so local deformation caused by a temperature change after mounting the element is performed. As a result, a position shift may occur between a terminal of the element and a terminal portion to be bonded on the wiring board, which causes a bonding failure. Therefore, for bonding with a terminal that cannot secure sufficient bonding strength or bonding at a terminal on a portion of the substrate that has a restricting action in a composite direction with respect to expansion and contraction, On the other hand, it is necessary to provide a means for reducing the deformation by slowing the expansion and contraction of the substrate, at least in a portion where defects are likely to occur. Although it may be provided over the entire surface of the substrate, it is possible to reduce the required amount of material by arranging it only at a site where it works effectively.

Consider the properties between the materials used for the circuit board. The wiring board includes an insulating layer made of an insulating material such as FR4 and a conductive layer made of a good conductor such as Cu. An electric element is connected to this wiring board. Table 1 shows the physical property values of each material in the case of BGA bare chip connection via ACF.

[0050]

[Table 1] According to Table 1, the relationship in terms of Young's modulus and transverse elastic modulus is as follows.

[0051]

(Equation 13)

However, as compared with FR4 and ACF, the Young's modulus of Si and Cu has a larger difference as the order is different. Compared to Si
Although the linear expansion coefficient of Cu is one order of magnitude higher, when considered in view of the mechanical properties as well, the difficulty of deformation of Si and Cu as a whole is about the same. On the other hand, conventionally, peeling failure between the wiring material and the insulating layer has hardly occurred.

From the above, it is appropriate to take measures to slow down the expansion and contraction of the substrate at or near the site where the bonding failure occurs.
In areas where bonding defects are likely to occur statistically, set the density or thickness of the wiring pattern of the conductive layer in this area higher than in other areas, or use redundant patterns unrelated to the conductive function of the circuit. A method such as adding to this area or its vicinity is effective. Examples of the region where a bonding failure is statistically likely to occur include a terminal portion near a corner of a bare chip to be BGA-bonded. In this portion, stress due to deformation or distortion acts greatly, and an open defect is likely to occur. The above description can be similarly applied to a mounting not using the ACF, although there is a difference in bonding strength.

<Specific Embodiment> A specific embodiment of the present invention will be described with reference to the drawings. The wiring patterns of the wiring board shown in FIG. 2 to FIG. 5 indicate portions including areas where defects are likely to occur on the surface of the wiring board. FIG. 2 shows a conventional wiring pattern, and the bonding failure is remarkable in a broken line region in the figure. The area inside the broken line area A corresponds to the position where the corner of the outer shape X of the semiconductor chip mounted on the wiring board is located and in the vicinity thereof. Lower than that.

FIG. 3 is a view showing a wiring board having a wiring pattern obtained by adding a redundant pattern to the wiring board shown in FIG. 2, and the redundant pattern B is formed over the entire area of the wiring board so as to fill gaps between the wiring patterns so as not to short-circuit each other. It has been arranged.

FIG. 4 is a view showing a wiring board having a wiring pattern obtained by adding a redundant pattern to the wiring board shown in FIG. 2. The redundant pattern is enclosed in a broken line region so as to fill the gap between the wiring patterns without short-circuiting. C is provided.

FIG. 5 is a view showing a wiring board in which a wiring pattern is added to the wiring board of FIG. 2. In FIG. 5, another different wiring pattern is filled so as not to short-circuit a gap between the wiring patterns. The pattern is reconfigured so that D is provided.

In FIGS. 3 to 5, the redundant pattern is made of the same material as the wiring pattern, that is, made of copper material, and a conductive member is provided between the insulating material of the wiring board and the electric component in a region where defects easily occur. Is provided. As a result, occurrence of bonding failure between the electric component and the wiring board is reduced.

In the above example, the wiring pattern has been described in which the wiring is drawn out from the area corresponding to the vicinity of the corner of the electric component. However, from the viewpoint of closing the gap between the wirings as much as possible, It is preferable that a wiring pattern is not provided in a region corresponding to the vicinity where a failure is likely to occur, and that this region is covered with a redundant pattern. At this time, the electric wiring may be provided not in the vicinity of the corner of the outer shape of the electric component but in the area on the wiring board corresponding to the position of the side connecting the corners of the electric component. It will be preferable.

<Application to Electric Apparatus> As described above, a wiring board in which the residual copper ratio of a conductive layer is adjusted so that it does not warp due to heat, or whose local deformation is reduced, is a semiconductor integrated circuit or a semiconductor. A memory board and other various electrical components are soldered in a reflow furnace or connected by ACF to form a highly reliable circuit board. The circuit board includes a display device that displays the internal state of the electronic circuit, a display device such as an LED, an input component such as a microphone, various sensors, or a keypad for inputting electronic information to the circuit board. For devices that handle sound, such as speakers, for devices that handle heat, heating devices such as heating wires and microwave generators, and for devices that handle power, output devices such as rotating machines and linear motors are installed. It is housed in a housing that is integrally held, and all types of electrical devices are configured.

In the conventional wiring board design concept, when the wiring board is warped, the board is bent by pressing both ends of the board with heavy objects as shown in FIG. 7 in order to increase the rigidity of the entire board. However, when electrical equipment was manufactured using a circuit board manufactured by such a process, the wiring board warped after being incorporated into the product due to the heat generated by the electrical equipment itself, Local deformation may occur, and such a problem is particularly caused by miniaturization /
In portable information terminal devices such as mobile phones, portable computers, and electronic organizers that are becoming lighter / higher-density packages, the problem cannot be ignored. The wiring board of the present invention focuses on the difference in the degree of expansion between the conductive layers caused by the difference in the residual copper ratio, and balances the degree of expansion between the conductive layers so that warpage does not occur, and focuses on local deformation. Since this deformation is reduced, the generation of stress applied to the joint is essentially suppressed,
In portable information terminal devices that are becoming smaller and lighter, the wiring board of the present invention can be used without taking special heat measures, and electrical equipment using this wiring board is unlikely to cause failure due to heat. Becomes

[0062]

As described above, according to the present invention, in order to reduce the variation in the amount of copper in the thickness direction of the conductive layer of the wiring board, the residual copper ratio of the conductive layer and the thickness of the conductive layer and the insulating layer are reduced. As a result, the bending moment due to the thermal deformation can be reduced to prevent the wiring board from warping, thereby making it difficult to warp. By applying the present invention to a small-sized electric device in which it is difficult to take measures against heat, it is not necessary to use other heat measures parts, so that it is possible to contribute to simplification of the apparatus while maintaining reliability.

[Brief description of the drawings]

FIG. 1 is a plan view showing a state in which a substrate is transferred by a transfer belt of a reflow furnace.

FIG. 2 is a schematic view showing a region where a conventional wiring board is likely to be defective and its vicinity.

FIG. 3 is a schematic view showing an embodiment in which the present invention is applied to a conventional wiring board.

FIG. 4 is a schematic diagram showing an embodiment in which the present invention is applied to a conventional wiring board.

FIG. 5 is a schematic view showing an embodiment in which the present invention is applied to a conventional wiring board.

FIG. 6 is a schematic explanatory view showing an outline of a process using a reflow furnace.

FIG. 7 is a schematic view showing an example in which a warp prevention jig is used for a substrate.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Wiring board, 2 ... Insulating layer, L1-L6 ... Conductive layer, 5a
... area reduction hole, 6 ... area increase pattern, 10 ... reflow furnace, 110 ... wiring board.

Claims (19)

[Claims] 1. A wiring board, comprising: a conductive layer having at least a part of a conductive member whose laying area is increased by a redundant pattern; and an insulating layer alternately laminated with the conductive layer. When the redundant pattern is not formed, when an electrical component to be provided on the wiring board is provided on the wiring board, statistically defective bonding between the electrical component and the wiring board is performed. A wiring board comprising a region which is likely to occur. 2. A wiring board, comprising: a conductive layer having at least a portion of a conductive member whose laying area is increased by a redundant pattern; and an insulating layer alternately stacked with the conductive layer. A wiring board characterized by including a region where a portion corresponding to a corner of an outer shape of the electric component is located when the electric component is provided on the wiring board. 3. A wiring board, comprising: a conductive layer having at least a portion of a conductive member whose laying area is increased by a redundant pattern; and an insulating layer alternately laminated with the conductive layer. The present invention provides a wiring board characterized by including a region where a portion corresponding to a corner of an outer shape of the semiconductor device is located when the semiconductor device is provided on the wiring board. 4. A method for manufacturing a wiring board, comprising: a laminating step of alternately laminating conductive layers having at least a portion of a conductive member whose laying area is increased by a redundant pattern and insulating layers. When the part is not formed with the redundant pattern, when an electric component to be provided on the wiring board is provided on the wiring board, the electric component is statistically bonded to the wiring board. A method for manufacturing a wiring board, wherein the method is a region in which a defect is likely to occur in a circuit. 5. A method for manufacturing a wiring board, comprising: a laminating step of alternately laminating conductive layers and insulating layers each having at least a portion of a conductive member whose laying area is increased by a redundant pattern. The method of manufacturing a wiring board according to claim 1, wherein the part is a region where a part corresponding to a corner of an outer shape of the electric component is located when the electric component is provided on the wiring board. 6. A method for manufacturing a wiring board, comprising: a laminating step of alternately laminating conductive layers having at least a portion of a conductive member whose laying area is increased by a redundant pattern and insulating layers. Wherein the portion is a region where a portion corresponding to a corner of the outer shape of the semiconductor device is located when the semiconductor device is provided on the wiring substrate. 7. The wiring board according to claim 1, wherein the conductive layer has a predetermined range of variation in the amount of conductive members in the thickness direction with respect to the center of the wiring board in the thickness direction. A wiring board characterized by being inside. 8. A method for manufacturing a wiring board according to claim 4, wherein the conductive layer has a predetermined variation in the amount of conductive members in the thickness direction with respect to the center of the wiring board in the thickness direction. A method for manufacturing a wiring board, comprising a step of laminating a conductive layer within a range. 9. The ratio of the area formed by the conductive member to the area formed by the plate surface is defined as the ratio of the conductive member disposed, N is the number of conductive member layers, the Z axis is parallel to the plate thickness direction, and the center of the plate is defined as the origin. When the axis is to be 4. The wiring board according to claim 1, wherein the value of the wiring board is within a predetermined range in which warpage is unlikely to occur. 10. The ratio of the area formed by the conductive member to the area formed by the plate surface is defined as the ratio of the conductive member, N is the number of conductive member layers, the Z axis is parallel to the plate thickness direction, and the center of the plate is defined as the origin. When the axis is to be 7. The method for manufacturing a wiring board according to claim 4, further comprising the step of arranging a conductive layer whose value is within a predetermined range in which warpage hardly occurs. 11. The wiring board according to claim 1, wherein the conductive layers located symmetrically in the thickness direction have the same area. 12. The method for manufacturing a wiring board according to claim 4, wherein a conductive layer having an area equal to that of another conductive layer located symmetrically in the thickness direction is provided. 13. The wiring board according to claim 7, wherein the conductive member has a conductive layer having an area reducing hole. 14. A conductive layer having an area increasing pattern made of a conductive member.
The wiring board as described. 15. The method for manufacturing a wiring board according to claim 8, wherein a conductive layer having an area reduction hole is provided in the conductive member. 16. The method for manufacturing a wiring board according to claim 8, wherein a conductive layer having an area increasing pattern made of a conductive member is provided. 17. The wiring board according to claim 1, wherein the conductive member is copper or a copper alloy. 18. The method according to claim 4, wherein the conductive member is copper or a copper alloy. 19. An electric device comprising: a circuit board comprising the wiring board according to claim 1, and a housing for accommodating the circuit board.