JP2000269538A - Waveguide type light receiving element and manufacture of the same - Google Patents
Waveguide type light receiving element and manufacture of the sameInfo
- Publication number
- JP2000269538A JP2000269538A JP11068946A JP6894699A JP2000269538A JP 2000269538 A JP2000269538 A JP 2000269538A JP 11068946 A JP11068946 A JP 11068946A JP 6894699 A JP6894699 A JP 6894699A JP 2000269538 A JP2000269538 A JP 2000269538A
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- light receiving
- region
- receiving element
- waveguide type
- type light
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Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、受光素子領域の前
段に光減衰領域をモノリシックに集積してなり、上記受
光素子領域と光減衰領域との光結合効率を高めた高感度
な導波路型受光素子とその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-sensitivity waveguide type in which a light-attenuating region is monolithically integrated before a light-receiving element region to enhance the optical coupling efficiency between the light-receiving element region and the light-attenuating region. The present invention relates to a light receiving element and a method for manufacturing the same.
【0002】[0002]
【関連する背景技術】近時、光を媒体とした高速・大容
量の光情報通信が注目されている。このような光情報通
信において重要な役割を担う光学素子の1つに半導体受
光素子、例えば導波路型の受光領域の前段に光減衰領域
をモノリシックに集積した導波路型受光素子がある。2. Related Art Recently, high-speed, large-capacity optical information communication using light as a medium has been receiving attention. One of the optical elements that play an important role in such optical information communication is a semiconductor light receiving element, for example, a waveguide type light receiving element in which a light attenuation area is monolithically integrated in front of a waveguide type light receiving area.
【0003】この種の導波路型受光素子は、例えば図3
にその製造工程を模式的に示すように、基板上に受光領
域と光減衰領域とをモノリシックに形成すると共に、こ
れらの受光領域と光減衰領域とを電気的に分離する素子
分離領域を形成した素子構造を有する。即ち、この種の
導波路型受光素子は、先ず図3(a)に示すようにn-In
P基板1上に有機金属気相成長(MOCVD)法を用い
る等して受光素子をなすn-InPクラッド層2、i-Ga
InAs光吸収層3、p-InPクラッド層4、そしてp-
GaInAsコンタクト層5を順に成長させる。次いで図
3(b)に示すようにSiNx膜6aをマスクとして受光素
子形成領域を除く領域を前記i-GaInAs光吸収層3ま
で選択エッチングし、その露出領域に図3(c)に示すよ
うに光減衰領域をなすi-GaInAsP光減衰層7、p-
InPクラッド層9、そしてp-GaInAsコンタクト層
9を順に再成長させる。A waveguide type light receiving element of this type is, for example, shown in FIG.
As schematically shown in the manufacturing process, a light receiving region and a light attenuation region were formed monolithically on a substrate, and an element isolation region for electrically separating the light receiving region and the light attenuation region was formed. It has an element structure. That is, this type of waveguide type light receiving element first has n-In, as shown in FIG.
An n-InP clad layer 2 forming a light receiving element on a P substrate 1 by using a metal organic chemical vapor deposition (MOCVD) method or the like, i-Ga
InAs light absorbing layer 3, p-InP cladding layer 4, and p-
The GaInAs contact layer 5 is grown in order. Next, as shown in FIG. 3B, using the SiNx film 6a as a mask, the region excluding the light receiving element forming region is selectively etched to the i-GaInAs light absorption layer 3, and the exposed region is formed as shown in FIG. I-GaInAsP light attenuating layer 7 forming a light attenuating region, p-
The InP cladding layer 9 and the p-GaInAs contact layer 9 are sequentially grown again.
【0004】しかる後、前記SiNx膜6bからなる別の
マスクを用いて図3(d)に示すように前記InP基板1
が露出するまで選択エッチングして素子分離用開口部A
を形成すると共に、前記受光素子領域および光減衰領域
をそれぞれリッジ導波路構造に形成する。そして前記受
光素子領域および光減衰領域をそれぞれ逆バイアスした
際に生じる無効電流を抑制するべく、上記素子分離用開
口部にFeドープの半絶縁性InP(Fe-InPと略す)
分離層10を埋め込み再成長させることで10GΩ以上
の分離抵抗を実現し、その後、所定のプロセスを経て電
極形成して前述した光減衰領域を前段に備えた導波路型
受光素子が製造される。Thereafter, using another mask made of the SiNx film 6b, as shown in FIG.
Selective etching until element is exposed
And the light receiving element region and the light attenuation region are each formed in a ridge waveguide structure. Then, in order to suppress a reactive current generated when the light receiving element region and the light attenuation region are reversely biased, a Fe-doped semi-insulating InP (abbreviated as Fe-InP) is formed in the element isolation opening.
By embedding and regrowing the separation layer 10, a separation resistance of 10 GΩ or more is realized, and thereafter, electrodes are formed through a predetermined process to manufacture the above-described waveguide type light receiving element having the above-described light attenuation region at the preceding stage.
【0005】[0005]
【発明が解決しようとする課題】ところで上述した如く
素子分離用開口部Aをウェットエッチングにより選択的
に形成する場合、そのエッチングか深さ方向のみならず
横方向にも進むので、その開口幅(分離幅)を高精度に
制御することが困難である。しかも特定の面方位が形成
されるので、Fe-InP分離層10を完全に埋め込み再
成長させることが困難である。この為、素子分離領域に
おける光の散乱損失や回折損失が大きく、受光素子とし
ての受光感度が制限されることが否めない。As described above, when the element isolation opening A is selectively formed by wet etching, the etching proceeds not only in the depth direction but also in the lateral direction. It is difficult to control the separation width with high accuracy. In addition, since a specific plane orientation is formed, it is difficult to completely bury and regrow the Fe-InP separation layer 10. For this reason, light scattering loss and diffraction loss in the element isolation region are large, and it cannot be denied that light receiving sensitivity as a light receiving element is limited.
【0006】ちなみに前記受光素子領域と光減衰領域と
の間の結合効率は、例えば図4に示すように上記素子分
離用開口部Aの分離幅zに大きく依存している。具体的
には前記光吸収層3の厚みdPDを0.1μmとした受光
素子にあっては、素子分離領域を設けない場合(分離幅
zが[0])に比較して、上記分離幅zを30μmとし
た場合、その結合効率が[0.84]から[0.24]へ
と大幅に低下し、素子分離領域がその最小受光感度に大
きな制約を与えている。Incidentally, the coupling efficiency between the light receiving element region and the light attenuation region largely depends on the separation width z of the element separating opening A as shown in FIG. Specifically, in the light receiving element in which the thickness dPD of the light absorbing layer 3 is 0.1 μm, the above-described separation width is smaller than when the element isolation region is not provided (the separation width z is [0]). When z is 30 μm, the coupling efficiency is greatly reduced from [0.84] to [0.24], and the element isolation region greatly restricts the minimum light receiving sensitivity.
【0007】これに対して前記素子分離領域をドライエ
ッチングにより形成することが考えられる。しかしなが
らドライエッチングにより分離幅zが4μm以下の素子
分離用開口部Aを形成したとしても、その狭い開口部A
にFe-InP分離層10を埋め込み再成長させることが
極めて困難である。本発明はこのような事情を考慮して
なされたもので、その目的は、受光素子領域の前段に光
減衰領域をモノリシックに集積した導波路型受光素子で
あって、上記受光素子領域と光減衰領域との結合効率を
十分に高め、その最小受光感度を大きくした導波路型受
光素子とその製造方法を提供することにある。On the other hand, it is conceivable to form the element isolation region by dry etching. However, even if the element separation opening A having a separation width z of 4 μm or less is formed by dry etching, the narrow opening A
It is extremely difficult to bury the Fe-InP separation layer 10 in the first layer and to re-grow it. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a waveguide type light receiving element in which an optical attenuation area is monolithically integrated in a stage preceding a light receiving element area. It is an object of the present invention to provide a waveguide type light receiving element having a sufficiently high coupling efficiency with a region and an increased minimum light receiving sensitivity, and a method of manufacturing the same.
【0008】[0008]
【課題を解決するための手段】上述した目的を達成する
べく本発明に係る導波路型受光素子は、受光素子領域の
前段に光減衰領域をモノリシックに集積したものであっ
て、特に上記受光素子領域と前記光減衰領域との間に、
多層導波路構造をなして該受光素子領域と光減衰領域と
を光学的に結合する電気的素子分離領域を設けたことを
特徴としている。In order to achieve the above-mentioned object, a waveguide type light receiving device according to the present invention comprises a light attenuating region monolithically integrated before a light receiving device region. Between the region and the light attenuation region,
It is characterized in that an electrical element isolation region for optically coupling the light receiving element region and the optical attenuation region is provided in a multilayer waveguide structure.
【0009】即ち、本発明に係る導波路型受光素子は、
受光素子領域と光減衰領域との間に形成する電気的素子
分離領域自体を、該受光素子領域と光減衰領域とを光学
的に結合する多層導波路構造として実現することで該電
気的素子分離領域における光の散乱損失や回折損失を押
さえ、受光素子領域と光減衰領域との間の光結合効率を
高めることで、その最小受光感度を高めたことを特徴と
している。That is, the waveguide type light receiving element according to the present invention comprises:
The electrical element isolation region itself formed between the light receiving element region and the light attenuation region is realized as a multilayer waveguide structure that optically couples the light reception element region and the light attenuation region to achieve the electrical element isolation. It is characterized in that the minimum light receiving sensitivity is increased by suppressing light scattering loss and diffraction loss in the region and increasing the optical coupling efficiency between the light receiving element region and the light attenuation region.
【0010】また本発明に係る導波路型受光素子の製造
方法は、基板上に多層導波路構造をなす電気的素子分離
層を成長させた後、該電気的素子分離層を部分的にエッ
チング除去して前記基板を露出させて、該基板上に前記
電気的素子分離層に光学的に結合させた導波路型の受光
素子領域および導波路型の光減衰領域を前記電気的素子
分離層を挟んでそれぞれ成長させることを特徴としてい
る。In the method of manufacturing a waveguide type light receiving device according to the present invention, after an electrical isolation layer having a multilayer waveguide structure is grown on a substrate, the electrical isolation layer is partially removed by etching. Exposing the substrate, and sandwiching the electrical element isolation layer with a waveguide type light receiving element region and a waveguide type optical attenuation region optically coupled to the electrical element isolation layer on the substrate. It is characterized in that each is grown.
【0011】つまり基板上に先ず多層導波路構造をなす
電気的素子分離層を成長させた後、この電気的素子分離
層を挟んで導波路型の受光素子領域および導波路型の光
減衰領域をそれぞれモノリシックに成長させて導波路型
受光素子を製造することを特徴としている。That is, after an electrical element isolation layer having a multilayer waveguide structure is first grown on a substrate, a waveguide type light receiving element region and a waveguide type optical attenuation region are sandwiched by the electrical element isolation layer. It is characterized in that a waveguide type light receiving element is manufactured by growing each monolithically.
【0012】[0012]
【発明の実施の形態】以下、図面を参照して本発明の一
実施形態に係る導波路型受光素子とその製造方法につい
て説明する。図1は導波路型受光素子の製造方法をその
製造工程の手順に従って分解して示すもので、図2はこ
の製造手順に従って製造される導波路型受光素子の概略
的な素子構造を示している。図2に示すようにこの発明
に係る導波路型受光素子は、n-InP基板11上に形成
した導波路型の受光素子領域PDの前段に光減衰領域A
TTをモノリシックに集積すると共に、更に上記受光素
子領域PDと光減衰領域ATTとの間に多層導波路構造
をなす電気的素子分離領域WGを成長させ、この多層導
波路構造をなす素子分離領域WGを介して前記受光素子
領域PDと光減衰領域ATTとを光学的に結合させた素
子構造を有する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A waveguide type light receiving device according to an embodiment of the present invention and a method for manufacturing the same will be described below with reference to the drawings. FIG. 1 is an exploded view of a method of manufacturing a waveguide type light receiving element according to the procedure of the manufacturing process, and FIG. 2 shows a schematic element structure of the waveguide type light receiving element manufactured according to this manufacturing procedure. . As shown in FIG. 2, the waveguide type light receiving element according to the present invention has a light attenuation region A before the waveguide type light receiving element region PD formed on the n-InP substrate 11.
In addition to monolithically integrating the TT, an electrical element isolation region WG having a multilayer waveguide structure is grown between the light receiving element region PD and the optical attenuation region ATT, and the element isolation region WG having the multilayer waveguide structure is grown. Has an element structure in which the light receiving element region PD and the light attenuation region ATT are optically coupled to each other.
【0013】このような素子構造をなす導波路型受光素
子とその製造方法について説明すると、先ずn-InP基
板11を準備し、例えばMOCVD法により図1(a)に
示すように上記n-InP基板11上に多層導波路型の素
子分離層12を成長させる。この多層導波路構造をなす
素子分離層12は、例えばn-InP基板11上に順次成
長させたFeドープの半絶縁性InPクラッド層12a、
Feドープの半絶縁性GaInAsP光減衰層12b、そし
てFeドープの半絶縁性InPクラッド層12cからな
る。A waveguide type light receiving element having such an element structure and a method of manufacturing the same will be described. First, an n-InP substrate 11 is prepared, and the n-InP substrate 11 is formed by MOCVD, for example, as shown in FIG. A multi-layer waveguide type element isolation layer 12 is grown on a substrate 11. The element isolation layer 12 having the multilayer waveguide structure includes, for example, an Fe-doped semi-insulating InP clad layer 12a sequentially grown on the n-InP substrate 11,
It comprises a semi-insulating GaInAsP light attenuating layer 12b doped with Fe and a semi-insulating InP cladding layer 12c doped with Fe.
【0014】次いで図1(b)に示すように上記素子分離
層12上に形成したSiNx膜13aをマスクとして前記
素子分離層12を選択的にドライエッチングし、これに
よって露出させた前記n-InP基板11上に図1(c)に
示すように導波路型受光素子PDをなすn-InPクラッ
ド層14、i-GaInAs光吸収層15、p-InPクラッ
ド層16、そしてp-GaInAsコンタクト層17からな
る多層膜を順に再成長させる。しかる後、その全面に成
膜したSiNx膜13bを前記素子分離層12の幅zが、
例えば4μmとなるようにフォトリソグラフィによりパ
ターニングし、図1(d)に示すように前記素子分離層1
2を選択的にドライエッチングする。Next, as shown in FIG. 1B, the element isolation layer 12 is selectively dry-etched using the SiNx film 13a formed on the element isolation layer 12 as a mask, and the n-InP As shown in FIG. 1 (c), an n-InP cladding layer 14, an i-GaInAs light absorbing layer 15, a p-InP cladding layer 16, and a p-GaInAs contact layer 17 forming a waveguide type light receiving element PD on a substrate 11 as shown in FIG. Are sequentially regrown. After that, the SiNx film 13b formed on the entire surface of the element isolation layer 12 is set to have a width z of
For example, patterning is performed by photolithography so as to have a thickness of, for example, 4 μm, and as shown in FIG.
2 is selectively dry-etched.
【0015】次いで上記エッチングにより露出した前記
n-InP基板11上に、図1(d)に示すように導波路型
の光減衰領域ATTをなすn-InPクラッド層18、i
-GaInAsP光減衰層19、p-InPクラッド層20、
そしてp-GaInAsコンタクト層21を順に再成長させ
る。その後、所定のプロセスを経て、図2に示すように
その上面にp電極22,また基板11の裏面にn電極2
3をそれぞれ蒸着形成して導波路型受光素子が製作され
る。Next, on the n-InP substrate 11 exposed by the etching, as shown in FIG. 1D, n-InP cladding layers 18 and i forming a waveguide type optical attenuation region ATT are formed.
-GaInAsP light attenuation layer 19, p-InP cladding layer 20,
Then, the p-GaInAs contact layer 21 is regrown in order. Thereafter, through a predetermined process, a p-electrode 22 is formed on the upper surface and an n-electrode 2 is formed on the back surface of the substrate 11 as shown in FIG.
3 are formed by vapor deposition to manufacture a waveguide type light receiving element.
【0016】かくしてこのようにして製作される導波路
型受光素子によれば、受光素子領域PDと光減衰領域A
TTとが多層導波路構造をなす素子分離層12を介して
光学的に結合され、且つ電気的に分離された素子構造と
なる。しかも先にn-InP基板11上に成長させた素子
分離層12をエッチングし、該素子分離層12を挟んで
受光素子領域PDと光減衰領域ATTとをそれぞれ成長
させた素子構造をなすので、該受光素子領域PDと光減
衰領域ATTとの分離幅zを狭くする場合であっても、
その狭い領域に上記素子分離層12を確実に位置付ける
ことが可能である。更には素子分離層12自体が導波路
構造をなすので、素子分離層12における光の散乱損失
や回折損失を十分に小さく抑えることができ、前記受光
素子領域PDと光減衰領域ATTとの結合効率を略
[1]に高めることができる。この結果、最小受光感度
を0.8A/W以上とする高感度な導波路型受光素子を
実現することが可能となる。しかも非常に簡単に、安価
に高感度な導波路型受光素子を製造することができる。
また最低受光感度を高め得る分、そのダイナミックレン
ジを広くし、低歪み動作化を図ることが可能となる等の
効果が奏せられる。According to the waveguide type light receiving element thus manufactured, the light receiving element region PD and the light attenuation region A
TT and TT are optically coupled via an element isolation layer 12 having a multilayer waveguide structure, and an element structure electrically isolated. In addition, since the element isolation layer 12 previously grown on the n-InP substrate 11 is etched and the light receiving element area PD and the light attenuation area ATT are grown with the element isolation layer 12 interposed therebetween, an element structure is formed. Even when the separation width z between the light receiving element region PD and the light attenuation region ATT is reduced,
The element isolation layer 12 can be reliably positioned in the narrow area. Further, since the element isolation layer 12 itself forms a waveguide structure, light scattering loss and diffraction loss in the element isolation layer 12 can be sufficiently suppressed, and the coupling efficiency between the light receiving element region PD and the light attenuation region ATT can be improved. Can be increased to approximately [1]. As a result, it is possible to realize a highly sensitive waveguide type light receiving element having a minimum light receiving sensitivity of 0.8 A / W or more. Moreover, a highly sensitive waveguide type light receiving element can be manufactured very easily and inexpensively.
In addition, since the minimum light receiving sensitivity can be increased, the dynamic range can be widened, and effects such as low distortion operation can be achieved.
【0017】尚、本発明は上述した実施形態に限定され
るものではない。例えば素子分離層12による受光素子
領域PDと光減衰領域ATTとの分離幅zを更に広く設
定しても、該素子分離層12自体が導波路をなすので実
用上、感度低下等の問題を招くことはない。またドライ
エッチングのみならず、ウェットエッチングにより前記
素子分離層12をエッチングするようにしても良い。ま
たそのエッチングマスクとしてSiNx膜以外の絶縁膜
を用いることも勿論可能である。また実施形態において
は素子分離層12のコア層を光減衰層としたが、受光素
子領域PDと同一のGaInAs層からなる光吸収層とす
ることも可能である。The present invention is not limited to the above embodiment. For example, even if the separation width z between the light receiving element region PD and the light attenuating region ATT by the element isolation layer 12 is set to be wider, the element isolation layer 12 itself forms a waveguide, which causes problems such as a decrease in sensitivity in practical use. Never. Further, the element isolation layer 12 may be etched not only by dry etching but also by wet etching. Of course, an insulating film other than the SiNx film can be used as the etching mask. In the embodiment, the core layer of the element isolation layer 12 is a light attenuating layer, but may be a light absorbing layer made of the same GaInAs layer as the light receiving element region PD.
【0018】更にはここではn-InP基板11上にGa
InAsP系の受光素子を実現する例について示したが、
p-InP基板上に実施形態とは逆導電型の受光素子を実
現することも可能であり、GaAs基板やInP基板上にI
II-V族、或いはII-V族の化合物半導体からなる受光素
子を生成する場合にも同様に適用可能である。更には受
光素子領域PDおよび光減衰領域ATT上に形成する電
極を分離させ、光減衰領域ATTを変調器として機能さ
せることも可能である。その他、本発明はその要旨を逸
脱しない範囲で種々変形して実施することができる。Further, here, Ga is placed on the n-InP substrate 11.
Although an example of realizing an InAsP light receiving element has been described,
It is also possible to realize a light receiving element of the opposite conductivity type to the embodiment on a p-InP substrate,
The present invention can be similarly applied to the case of producing a light receiving element made of a II-V group or II-V compound semiconductor. Further, it is possible to separate the electrodes formed on the light receiving element region PD and the light attenuation region ATT so that the light attenuation region ATT functions as a modulator. In addition, the present invention can be variously modified and implemented without departing from the gist thereof.
【0019】[0019]
【発明の効果】以上説明したように本発明によれば、受
光素子領域と光減衰領域との結合効率を十分に高くして
素子分離領域に依存する制約を受けた最低受光感度を十
分に高くした導波路型受光素子を実現することができ
る。しかも導波路構造をなす素子分離領域を予め形成
し、該素子分離領域を挟んで受光素子領域と光減衰領域
とをそれぞれ形成すると言う簡易な手順により、高感度
で高性能な導波路型受光素子を安価に実現することがで
きる等の実用上多大なる効果が奏せられる。As described above, according to the present invention, the coupling efficiency between the light receiving element region and the light attenuating region is made sufficiently high so that the minimum light receiving sensitivity which is limited by the element isolation region is made sufficiently high. The waveguide type light receiving element described above can be realized. In addition, a waveguide-type photodetector with high sensitivity and high performance is obtained by a simple procedure of forming an element isolation region forming a waveguide structure in advance and forming a light receiving element region and an optical attenuation region with the element isolation region interposed therebetween. Can be realized inexpensively, for example, and a great effect can be obtained in practical use.
【図1】本発明の一実施形態に係る導波路型受光素子の
製造方法を、その工程手順に従って示す図。FIG. 1 is a view showing a manufacturing method of a waveguide type light receiving element according to an embodiment of the present invention in accordance with the process procedure.
【図2】本発明の一実施形態に係る導波路型受光素子の
概略的な素子構造を示す図。FIG. 2 is a diagram showing a schematic element structure of a waveguide type light receiving element according to one embodiment of the present invention.
【図3】従来の導波路型受光素子の製造方法を、その工
程手順に従って示す図。FIG. 3 is a diagram showing a conventional method for manufacturing a waveguide type light receiving element according to the process procedure.
【図4】従来の導波路型受光素子における受光素子領域
と光減衰領域との間の素子分離用開口部の分離幅zに依
存する結合効率の変化特性を示す図。FIG. 4 is a diagram showing a change characteristic of coupling efficiency depending on a separation width z of an element separating opening between a light receiving element region and a light attenuation region in a conventional waveguide type light receiving element.
11 n-InP基板 12 導波路型の素子分離領域 12a Feドープの半絶縁性InPクラッド層 12b Feドープの半絶縁性GaInAsP光減衰層 12c Feドープの半絶縁性InPクラッド層 13a,13b SiNx膜(マスク) 14 n-InPクラッド層 15 i-GaInAs光吸収層 16 p-InPクラッド層 17 p-GaInAsコンタクト層 18 n-InPクラッド層 19 i-GaInAsP光減衰層 20 p-InPクラッド層 21 p-GaInAsコンタクト層 22 p電極 23 n電極 PD 受光素子領域 ATT 光減衰領域 WG 導波路型の素子分離領域 DESCRIPTION OF SYMBOLS 11 n-InP board 12 Waveguide-type element isolation region 12a Fe-doped semi-insulating InP cladding layer 12b Fe-doped semi-insulating GaInAsP light attenuation layer 12c Fe-doped semi-insulating InP cladding layer 13a, 13b SiNx film ( Mask) 14 n-InP clad layer 15 i-GaInAs light absorbing layer 16 p-InP clad layer 17 p-GaInAs contact layer 18 n-InP clad layer 19 i-GaInAsP light attenuating layer 20 p-InP clad layer 21 p-GaInAs Contact layer 22 p-electrode 23 n-electrode PD light-receiving element area ATT light attenuation area WG waveguide-type element isolation area
───────────────────────────────────────────────────── フロントページの続き (72)発明者 山口 武治 東京都千代田区丸の内2丁目6番1号 古 河電気工業株式会社内 Fターム(参考) 5F049 MB07 NA01 NB01 PA04 PA14 QA03 QA08 QA11 RA06 SS04 SZ20 5F088 AA03 AB07 BA01 BB01 CB04 DA01 DA17 GA05 JA11 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Takeharu Yamaguchi 2-6-1 Marunouchi, Chiyoda-ku, Tokyo Furukawa Electric Co., Ltd. F-term (reference) 5F049 MB07 NA01 NB01 PA04 PA14 QA03 QA08 QA11 RA06 SS04 SZ20 5F088 AA03 AB07 BA01 BB01 CB04 DA01 DA17 GA05 JA11
Claims (2)
領域をモノリシックに集積してなり、 上記受光素子領域と前記光減衰領域との間に、多層導波
路構造をなして該受光素子領域と光減衰領域とを光学的
に結合する電気的素子分離領域を設けたことを特徴とす
る導波路型受光素子。An optical attenuation region is monolithically integrated before a waveguide type light receiving element region, and a multilayer waveguide structure is formed between the light receiving element region and the light attenuation region. A waveguide type light receiving device, comprising: an electrical element isolation region for optically coupling a region and a light attenuation region.
子分離層を成長させた後、該電気的素子分離層を部分的
にエッチング除去して前記基板を露出させて、該基板上
に前記電気的素子分離層に光学的に結合させた導波路型
の受光素子領域および導波路型の光減衰領域を前記電気
的素子分離層を挟んでそれぞれ成長させることを特徴と
する導波路型受光素子の製造方法。2. After growing an electrical isolation layer having a multilayer waveguide structure on a substrate, the electrical isolation layer is partially etched away to expose the substrate, and the substrate is exposed on the substrate. A waveguide type light receiving device, wherein a waveguide type light receiving element region optically coupled to the electrical element isolation layer and a waveguide type light attenuation region are grown with the electrical element isolation layer interposed therebetween. Device manufacturing method.
Priority Applications (1)
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---|---|---|---|
JP11068946A JP2000269538A (en) | 1999-03-15 | 1999-03-15 | Waveguide type light receiving element and manufacture of the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11068946A JP2000269538A (en) | 1999-03-15 | 1999-03-15 | Waveguide type light receiving element and manufacture of the same |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2000269538A true JP2000269538A (en) | 2000-09-29 |
Family
ID=13388350
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011037686A1 (en) * | 2009-09-25 | 2011-03-31 | Intel Corporation | Optical modulator utilizing wafer bonding technology |
JP2013110207A (en) * | 2011-11-18 | 2013-06-06 | Fujitsu Ltd | Semiconductor optical integrated element and manufacturing method of the same |
-
1999
- 1999-03-15 JP JP11068946A patent/JP2000269538A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011037686A1 (en) * | 2009-09-25 | 2011-03-31 | Intel Corporation | Optical modulator utilizing wafer bonding technology |
US8450186B2 (en) | 2009-09-25 | 2013-05-28 | Intel Corporation | Optical modulator utilizing wafer bonding technology |
JP2013110207A (en) * | 2011-11-18 | 2013-06-06 | Fujitsu Ltd | Semiconductor optical integrated element and manufacturing method of the same |
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