JP2000269508A - Manufacture for thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a difference in respective threshold voltages between (n) channel thin film transistors and (p) channel thin film transistors by a method wherein, at a step of forming an active layer of the thin film transistors, a defective level is formed in a polycrystal semiconductor film constituting the active layer. SOLUTION: When an active layer of thin film transistors is formed, impurities at a lower concentration are doped to the active layer of the thin film transistors, and simultaneously, elements or ions hindering a crystallization are implanted, and a polycrystal silicon thin film 13 having a defective level is formed. Then, when these thin film transistors are functioned as an (n) channel and (p) channel transistor, they have a predetermined threshold voltage in response to the number of defective levels, respectively. Accordingly, it is possible to control the respective threshold voltages of (n) channel thin film transistors and (p) channel thin film transistors to be appropriate values by one time impurity doping.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a thin film transistor, and more particularly to a method for manufacturing a thin film transistor used for a driving circuit of a liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, a thin film transistor as a pixel switching circuit arranged in a display area for displaying an image and a thin film transistor as a drive circuit arranged in a peripheral area around the display area are integrally formed on an insulating substrate. Liquid crystal display devices have attracted attention. In such a liquid crystal display device, as a thin film transistor constituting a driving circuit, an n-channel thin film transistor and a p-channel thin film transistor are usually formed on the same substrate and used as a complementary circuit.

[0003] Such a thin film transistor is, for example,
An amorphous silicon thin film having a predetermined thickness is deposited on an insulating substrate, for example, a glass substrate by, for example, a CVD method. Then, a dehydrogenation process for removing hydrogen contained in the amorphous silicon thin film is performed by annealing. Subsequently, low-concentration impurities, for example, boron are implanted into the entire surface of the amorphous silicon thin film.

Then, the entire surface of the amorphous silicon thin film is irradiated with, for example, an excimer laser to melt the amorphous silicon.
Recrystallize to form a polycrystalline silicon thin film.

Then, the polycrystalline silicon thin film is patterned into a predetermined shape by, for example, photolithography to form an active layer of the thin film transistor. After this, n
The active layer in the region where the channel thin film transistor or the p-channel thin film transistor is to be formed is covered with a resist, and a low concentration impurity is implanted again using the resist as a mask.

In a thin film transistor formed using such an active layer, a low-concentration impurity is implanted twice.

That is, when an n-channel thin film transistor and a p-channel thin film transistor are formed on the same substrate to form a complementary circuit, the threshold voltage of each thin film transistor is considered from the viewpoint of operating speed and power consumption. Adjustment is important. When using a polycrystalline semiconductor thin film such as a polycrystalline silicon thin film as a thin film transistor active layer, that is, a non-single-crystal semiconductor thin film,
Poor rise of sub-threshold area.

Therefore, in order for the circuit to operate normally, it is required that the threshold voltages of the n-channel thin film transistor and the p-channel thin film transistor have a certain difference or more. The required difference in threshold voltage between the n-channel thin film transistor and the p-channel thin film transistor is required to be about 3 V. When a thin film transistor using a polycrystalline semiconductor thin film as an active layer is formed, a difference in threshold voltage between an n-channel thin film transistor and a p-channel thin film transistor becomes about 1 V, and there is a possibility that a normal operation may not be performed as a complementary circuit. is there.

For this reason, when an n-channel thin film transistor and a p-channel thin film transistor are formed on the same substrate, conventionally, a low-concentration impurity is implanted into a semiconductor thin film which is to be an active layer in two steps, and an n-channel thin film transistor is formed. Control the threshold voltage by making a difference in the impurity concentration of the active layer in the n-channel thin film transistor and the p-channel thin film transistor so that the difference in threshold voltage between the thin film transistor and the p-channel thin film transistor becomes about a required value. are doing.

[0010]

As described above, when an n-channel thin-film transistor and a p-channel thin-film transistor are formed on the same substrate, the n-channel thin-film transistor is required to operate normally as a complementary circuit. It is required that there be a certain degree of difference between the threshold voltage and the threshold voltage of the p-channel thin film transistor. For this reason, the threshold voltage is controlled by injecting a low-concentration impurity into the semiconductor thin film forming the active layer of each thin-film transistor twice, and making the impurity concentration of the active layer different.

However, since the impurity is implanted in two steps, there is a problem that the manufacturing steps become long and the manufacturing cost is high.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has as its object to provide an inexpensive manufacturing cost and n
An object of the present invention is to provide a method for manufacturing a thin film transistor in which a channel thin film transistor and a p-channel thin film transistor can be formed over the same substrate.

[0013]

According to a first aspect of the present invention, there is provided a method of manufacturing a thin film transistor, comprising: an n-channel thin film transistor having a polycrystalline semiconductor thin film as an active layer; In a method of manufacturing a thin film transistor in which a thin film transistor is formed on the same substrate, a step of forming an active layer by patterning an impurity-containing polycrystalline semiconductor thin film formed on the substrate and forming an active layer on the active layer via an insulating film Patterning the formed metal film to form a gate electrode; and implanting impurities using the gate electrode as a mask to form source and drain regions containing p-type or n-type impurities on both sides of the active layer, respectively. And forming the active layer includes forming a defect level in the active layer. And wherein the Rukoto.

According to the method of manufacturing a thin film transistor of the present invention, in the step of forming the active layer of the thin film transistor, a defect level is formed in the polycrystalline semiconductor thin film forming the active layer. That is, when an impurity or a low concentration impurity is implanted into the active layer of the thin film transistor, a defect level is formed in the active layer by simultaneously implanting an element or ion that inhibits crystallization.

By using the active layer having such a defect level as an active layer of an n-channel thin film transistor and a p-channel thin film transistor, respectively,
The difference in threshold voltage between the n-channel thin film transistor and the p-channel thin film transistor increases.

Therefore, by one impurity implantation, n
The threshold voltage of each of the channel thin film transistor and the p-channel thin film transistor can be controlled to an appropriate value.

Thus, in the method for manufacturing a thin film transistor in which the n-channel thin film transistor and the p-channel thin film transistor are formed on the same substrate, the number of steps can be reduced, and the manufacturing cost can be reduced. Therefore, it is possible to provide a method for manufacturing a thin film transistor at a low manufacturing cost.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a thin film transistor according to the present invention will be described below with reference to the drawings. According to the method for manufacturing a thin film transistor of the present invention, an n-channel thin film transistor and a p-channel thin film transistor are formed over the same substrate, and a complementary circuit is formed by the thin film transistors. Such a complementary circuit is used, for example, as a drive circuit arranged in a peripheral area of an array substrate constituting an active matrix liquid crystal display device.

FIG. 1 schematically shows an example of a liquid crystal display panel of a liquid crystal display device using an n-channel thin film transistor and a p-channel thin film transistor formed on the same substrate as a driving circuit.

FIG. 2 schematically shows a circuit configuration of the active matrix type liquid crystal display device.

As shown in FIGS. 1 and 2, the liquid crystal display panel 10 includes an array substrate 100 as a first substrate, an opposing substrate 200 as a second substrate opposed to the array substrate 100, and an array substrate. 100 and a liquid crystal composition 300 disposed between the opposing substrate 200. In such a liquid crystal display panel 10, a display area 102 for displaying an image includes an array substrate 100 and a counter substrate 20.
The peripheral area 104 formed in a region surrounded by the seal material 106 for bonding the “0” and having various wiring patterns drawn out from the display area 102 is formed in a region outside the seal material 106.

The display area 102 of the array substrate 100 is
As shown in FIG. 2, mxn pixel electrodes 151 arranged in a matrix on a transparent insulating substrate, for example, a glass substrate having a thickness of 0.7 mm, are formed along the row direction of the pixel electrodes 151. M scanning lines Y1 to Ym, n signal lines X1 to Xn formed along the column direction of these pixel electrodes 151, and scanning lines Y1 to Ym and signal lines corresponding to mxn pixel electrodes 151. Mxn thin film transistors or TFTs 121 arranged as switching elements near intersections of X1 to Xn, and scanning lines Y1 to Ym
, A scanning line driving circuit 18 for driving the signal lines X1 to X
and a signal line driving circuit 19 for driving n.

The scanning lines Y and the signal lines X are formed of a low-resistance material such as aluminum or a molybdenum-tungsten alloy. The pixel electrode 151 is made of a transparent conductive material, for example, indium-tin-oxide or I
It is formed by TO.

The TFT 121 is constituted by, for example, a top gate type polycrystalline silicon thin film transistor having a portion protruding from the scanning line as a gate electrode and a polycrystalline silicon thin film as an active layer. The source region of the semiconductor layer is in contact with a source electrode electrically connected to the pixel electrode 151, and the drain region of the semiconductor layer is in contact with a drain electrode forming a part of a signal line.

The surface of the pixel electrode 151 is
And is covered with an alignment film for aligning the liquid crystal composition 300 interposed between them.

Each of the thin TFTs 121 has a corresponding one of the signal lines X1 to Xn driven by the signal line driving circuit 19 when the corresponding scanning line is driven by the scanning line driving circuit 18 to select the pixel electrode 151 in the corresponding row. It is used as a switching element for applying a potential to the pixel electrodes 151 in the corresponding rows.

The scanning line driving circuit 18 supplies a scanning voltage to the scanning lines Y1 to Ym sequentially in a horizontal scanning cycle, and the signal line driving circuit 19 supplies a pixel signal voltage to the signal lines X1 to Xn in each horizontal scanning cycle. I do.

In the liquid crystal display panel 10, as shown in FIG. 1, the signal lines X are connected to the array substrate 100 in order to reduce the external dimensions of the liquid crystal display device, particularly the frame size.
The X-TAB 401-is drawn out only to the first end 100X side of the peripheral area 104X of the X-control circuit board 421 including the signal line driving circuit 19 for supplying video data to the signal lines on the first end 100X side. 1, 401-2, 401
-3, 401-4.

Further, the scanning line Y is also drawn out only to the second side 100Y orthogonal to the first side 100X in the peripheral area 104X of the array substrate, and this second side 100Y
Scan line driving circuit 18 that supplies scan pulses to scan lines on the side
Y-TAB 411-
1, 411-2.

The driving circuits such as the X control circuit board 421 and the Y control circuit board 431 are constituted by complementary circuits composed of an n-channel thin film transistor and a P-channel thin film transistor. These thin film transistors are top gate thin film transistors using a polycrystalline semiconductor thin film such as a polycrystalline silicon thin film, that is, a non-single-crystal semiconductor thin film as an active layer.

The display area 10 of the array substrate 100
2 and non-pixel portions in the peripheral area 104 (X, Y),
That is, spacers for forming a gap of about 5 μm between the array substrate 100 and the counter substrate 200 are arranged on the wiring patterns such as the signal lines 103 and the scanning lines 111, the TFT 121, the pixel electrode 151, the peripheral frame portion, and the like. Accordingly, a gap between the array substrate 100 and the counter substrate 200 is set.

The display area 102 of the opposing substrate 200 is formed of a transparent insulating substrate, for example, a color filter disposed on a glass substrate having a thickness of 0.7 mm, and a transparent conductive material for forming a potential difference between the pixel electrode 151 and the pixel. A counter electrode 204 formed of a conductive member, for example, indium-tin-oxide, that is, ITO, and an alignment film for aligning the liquid crystal composition 300 interposed between the array member 100 and the counter electrode 204.

The counter electrode 204 includes a plurality of pixel electrodes 151
Are set to the reference potential. An electrode transfer material, that is, a silver paste as a transfer, disposed around the substrate is provided to supply a voltage from the array substrate 100 to the counter substrate 200, and the counter electrode 204 is connected to the counter electrode drive connected via the transfer. Driven by the circuit 20.

A liquid crystal capacitor CL is formed by the liquid crystal layer 300 sandwiched between the pixel electrode 151 and the counter electrode 204. The array substrate 100 includes a pair of electrodes for forming an auxiliary capacitance CS in parallel with the liquid crystal capacitance CL. That is, the storage capacitor CS is formed by a potential difference formed between the storage capacitor electrode 61 having the same potential as the pixel electrode 151 and the storage capacitor line 52 set to a predetermined potential.

On the front and back surfaces of the liquid crystal display panel 10, that is, on the outer surfaces of the glass substrates 101 and 201, a polarizing plate whose deflection surface is selected according to the display mode of the liquid crystal display device, the twist angle of the liquid crystal composition, and the like is provided. They are provided as needed.

Next, a first manufacturing method of an n-channel thin film transistor and a p-channel thin film transistor used as a driving circuit of the liquid crystal display device will be described.

Such a thin film transistor is formed by the steps shown in FIGS.

That is, as shown in FIG. 3A, an amorphous silicon thin film 1 is formed as an amorphous semiconductor thin film on an insulating substrate, for example, a glass substrate 11 by a plasma CVD method.
2 is deposited to a thickness of 50 nm. At this time, for example, silane (SiH ₄ ) is mainly used as a source gas.
Then, the glass substrate 11 on which the amorphous silicon thin film 12 has been formed is annealed in an annealing furnace at a temperature of 500 ° C. for 1 hour to remove hydrogen contained in the amorphous silicon thin film 12. Perform elementary processing.

Subsequently, the deposited amorphous silicon thin film 12
Is implanted at a dose of 9.5 × 10 ¹¹ / cm ² into the entire surface of the substrate by ion doping. As a raw material gas at this time, borohydride (B
Using a mixed gas obtained by mixing about 10% nitrogen (N ₂ ) gas in a gas such as ₂ H ₆ ), nitrogen is simultaneously implanted into the entire surface of the amorphous silicon thin film 12 with boron. Nitrogen mixed with the source gas acts as an element that inhibits crystallization of amorphous silicon.

Subsequently, as shown in FIG. 3B, for example, excimer laser light is applied to the entire surface of the amorphous silicon thin film 12 into which boron as an impurity and nitrogen as an element for inhibiting crystallization are implanted. Irradiation melts the amorphous silicon and recrystallizes it. At this time, the element that inhibits crystallization inhibits crystallization of amorphous silicon and forms a defect level. Thus, a polycrystalline silicon thin film 13 having a defect level is formed.

Subsequently, as shown in FIG. 3C, the polycrystalline silicon thin film 13 is formed by, for example, photolithography.
Is patterned into a predetermined shape to form active layers 13a and 13b of the thin film transistor. Subsequently, the active layer 1
On 3a and 13b, a gate insulating film 15 is formed to a thickness of 100 nm.
It is formed with a film thickness of. Then, a metal film 16 having a thickness of 300 nm is formed on the gate insulating film 15 by sputtering.
To form Then, the metal film 16 is patterned by photolithography to form a gate electrode 16a of one of the thin film transistors.

Subsequently, using the gate electrode 16a and the remaining metal film 16 as a mask, a non-mass separation type ion implantation apparatus is used to deposit p-type or n-type impurities at a high concentration on both sides of the active layer 13a. Implantation is performed to form a source region 17as and a drain region 17ad.

Subsequently, as shown in FIG. 3D, the remaining metal film 16 is patterned by photolithography to form a gate electrode 16b of the other thin film transistor.
To form Then, the resist 14 covers the entire region where one of the thin film transistors is formed in which the source region 17as and the drain region 17ad are formed on both sides of the active layer 13a and the gate electrode 16b of the other thin film transistor. Then, using the resist 14 as a mask, a non-mass separation type ion implantation apparatus is used to implant a conductive impurity at a high concentration into both sides of the active layer 13b in the opposite direction to the step described with reference to FIG. Then, a source region 17bs and a drain region 17bd are formed. After the resist 14 is removed, annealing is performed at 600 ° C. for 1 hour to form the source regions 17as and 17bs and the drain regions 17ad and 17b.
Activate the high-concentration impurities implanted in d.

Subsequently, as shown in FIG. 3E, an interlayer insulating film 18 having a thickness of 600 nm is formed on the gate electrodes 16a and 16b. Then, this interlayer insulating film 18
Then, a contact hole is formed in the gate insulating film 15.
Then, the source region 17 is formed through the contact hole.
as and 17bs and drain regions 17ad and 17b
d and the source electrodes 19as and 1
9bs and drain electrodes 19ad and 19bd are formed.

The thin film transistors 20a and 20b formed by the above-described steps are shown in FIG.
In the steps described in (d) and (d), an n-channel thin film transistor and a p-channel thin film transistor can be formed by appropriately selecting the impurities to be implanted. When formed as an n-channel thin film transistor, for example, phosphorus hydride (PH ₃ ) is used as an impurity to be injected into the active layer. When formed as a p-channel thin film transistor, as an impurity, for example, borohydride (PH) is used. B ₂ H ₆ ).

In this embodiment, FIG.
In the step, the impurities are, for example, mainly hydrogen
Phosphorus chloride (PH_Three), The acceleration voltage is 70 kV, and 1 ×
10 ¹⁵/ Cm^TwoIs implanted at a dose of. This allows
The thin film transistor 20a is an n-channel thin film transistor.
Function as a star. Further, the step shown in FIG.
For example, impurities may be primarily hydrogenated borane
Elementary (B_TwoH₆), The acceleration voltage is 70 kV, and 2 × 10
¹⁵/ Cm^TwoIs implanted at a dose of. This enables the thin film
The transistor 20b is a p-channel thin film transistor
Function as

The threshold voltage of the n-channel type thin film transistor manufactured by the above manufacturing method is +
1.6 V, and the threshold voltage of the p-channel thin film transistor was -1.5 V.

On the other hand, when boron is implanted into the active layer formed of the semiconductor thin film and no defect level is formed without adding nitrogen, the threshold voltage of the n-channel thin film transistor becomes , + 0.1V, and the threshold voltage of the p-channel type thin film transistor is -1.1V
Met. When nitrogen was not added, the amount of boron implanted in each of the n-channel thin film transistor and the p-channel thin film transistor was changed to cause a difference in the impurity concentration in the semiconductor thin film, and the threshold value of each thin film transistor was changed. Although the voltage can be controlled, the difference between the threshold voltages of the respective thin film transistors is about 1.0 to 1.5 V, and the circuit cannot operate normally as a complementary circuit.

On the other hand, according to the thin film transistor manufactured by the above-described manufacturing method, when boron is injected into the active layer formed by the semiconductor thin film, it is simultaneously injected to form a defect level in the active layer. By adjusting the amount of nitrogen added, the difference between the threshold voltage of the n-channel thin film transistor and the threshold voltage of the p-channel thin film transistor changes.

That is, by adjusting the amount of boron and the amount of nitrogen to be injected into the active layer, the amorphous semiconductor thin film forming the active layer is crystallized to form a polycrystalline semiconductor thin film. A predetermined number of defect levels are formed in the polycrystalline semiconductor thin film. By adjusting the number of defect levels formed in the polycrystalline semiconductor thin film, a thin film transistor using the polycrystalline semiconductor thin film as an active layer can function as an n-channel type and a p-channel type. Each has a predetermined threshold voltage according to the number.

Therefore, by adjusting the amount of boron and the amount of nitrogen to be implanted into the active layer, the threshold of each of these thin film transistors is adjusted according to the number of defect levels formed in the polycrystalline semiconductor thin film. The value voltage can be controlled to a desired value, and the difference between the threshold voltages of these thin film transistors can be adjusted to an appropriate value.

As described above, when forming the active layer of the thin-film transistor, the active layer of the thin-film transistor is simultaneously implanted with low-concentration impurities and at the same time, by implanting elements or ions that inhibit crystallization. Defect levels are formed. Therefore, the threshold voltage of each of the n-channel thin film transistor and the p-channel thin film transistor can be controlled to an appropriate value by one impurity implantation.

Thus, in the method of manufacturing a thin film transistor in which the n-channel thin film transistor and the p-channel thin film transistor are formed on the same substrate, the number of steps for causing a difference in the concentration of impurities implanted in each active layer is eliminated. It is possible to reduce the manufacturing cost. Therefore, it is possible to provide a method for manufacturing a thin film transistor at a low manufacturing cost.

In this embodiment, nitrogen is added as an element that inhibits the crystallization of amorphous silicon. However, other elements may be added. It is possible to form a defect level.

Also, in this embodiment, FIG.
After forming the amorphous silicon thin film by the steps shown in (2), impurities and elements that inhibit crystallization were implanted into this amorphous silicon thin film, but when forming the amorphous silicon thin film, By using a mixed gas mainly composed of silane gas, borane gas, and nitrogen gas as a source gas, it is possible to form an amorphous silicon thin film containing an impurity and an element inhibiting crystallization in one step. .

Therefore, it is possible to omit the step of implanting impurities and elements that inhibit crystallization, and it is possible to reduce the number of steps. Therefore, a thin film transistor can be manufactured at a low manufacturing cost.

Next, a second method for manufacturing an n-channel thin film transistor and a p-channel thin film transistor used as a driving circuit of the liquid crystal display device will be described.

Such a thin film transistor is formed by the steps shown in FIGS.

That is, as shown in FIG. 4A, an amorphous silicon thin film 3 is formed as an amorphous semiconductor thin film on an insulating substrate, for example, a glass substrate 31 by a plasma CVD method.
2 is deposited to a thickness of 50 nm. At this time, for example, silane (SiH ₄ ) is mainly used as a source gas.
Then, the glass substrate 31 on which the amorphous silicon thin film 32 is formed is annealed in an annealing furnace at a temperature of 500 ° C. for 1 hour to remove hydrogen contained in the amorphous silicon thin film 32. Perform elementary processing.

Subsequently, as shown in FIG. 4B, the entire surface of the amorphous silicon thin film 32 is irradiated with, for example, excimer laser light to melt and recrystallize the amorphous silicon.
A polycrystalline silicon thin film 33 is formed.

Subsequently, low-concentration impurities, mainly boron, are implanted into the entire surface of the polycrystalline silicon thin film 33 at a dose of 9.5 × 10 ¹¹ / cm ² by ion doping. As a raw material gas at this time, borohydride (B
The ₂ H ₆₎ gas and argon (Ar) gas, such as 1: 1 using a mixed gas mixture at a ratio, the polycrystalline silicon thin film 3
Argon is simultaneously implanted with boron over the entire surface of No. 3. Argon mixed with the source gas serves as an element that breaks bonds of polycrystalline silicon and causes crystal breakage. Thus, a polycrystalline silicon thin film 33 having a defect level is formed.

Subsequently, as shown in FIG. 4C, the polycrystalline silicon thin film 33 is formed by photolithography, for example.
Is patterned into a predetermined shape to form active layers 33a and 33b of the thin film transistor. Subsequently, the active layer 3
On 3a and 33b, a gate insulating film 35 is formed to a thickness of 100 nm.
It is formed with a film thickness of. Then, a metal film 36 having a thickness of 300 nm is formed on the gate insulating film 35 by sputtering.
To form Then, the metal film 36 is patterned by photolithography to form a gate electrode 36a of one of the thin film transistors.

Subsequently, using the gate electrode 36a and the remaining metal film 36 as a mask, a p-type or n-type impurity is highly concentrated on both sides of the active layer 33a by using a non-mass separation type ion implantation apparatus. Implantation is performed to form a source region 37as and a drain region 37ad.

Subsequently, as shown in FIG. 4D, the remaining metal film 36 is patterned by photolithography to form a gate electrode 36b of the other thin film transistor.
To form Then, the entire region where one thin film transistor is formed in which the source region 37as and the drain region 37ad are formed on both sides of the active layer 33a and the gate electrode 36b of the other thin film transistor are covered with the resist. Then, using this resist 34 as a mask, a conductive impurity opposite to the step described in FIG. 4C is implanted into both sides of the active layer 33b at a high concentration by using a non-mass separation type ion implantation apparatus. Then, a source region 37bs and a drain region 37bd are formed. Then, after the resist 34 is removed, annealing is performed at a temperature of 600 ° C. for 1 hour, so that the source regions 37as and 37bs and the drain regions 37ad and
Activate high-concentration impurities implanted into 37bd.

Subsequently, as shown in FIG. 4E, an interlayer insulating film 38 having a thickness of 600 nm is formed on the gate electrodes 36a and 36b. Then, the interlayer insulating film 38
Then, a contact hole is formed in the gate insulating film 35.
Then, the source region 37 is formed through the contact hole.
as and 37bs and drain regions 37ad and 37b
d, the source electrodes 39as and 3
9bs and drain electrodes 39ad and 39bd are formed.

The thin film transistors 40a and 40b formed by the above-described steps are shown in FIG.
In the steps described in (d) and (d), an n-channel thin film transistor and a p-channel thin film transistor can be formed by appropriately selecting the impurities to be implanted.

The threshold voltage of the n-channel type thin film transistor manufactured by the above-described manufacturing method is +
1.5V, and the threshold voltage of the p-channel thin film transistor was -1.5V.

On the other hand, when boron is implanted into the active layer formed of the semiconductor thin film and no defect level is formed without adding argon, the threshold voltage of the n-channel thin film transistor becomes , 0 V, and the threshold voltage of the p-channel thin film transistor was −1.0 V. When argon was not added, by changing the amount of boron implanted in each of the n-channel thin film transistor and the p-channel thin film transistor, a difference was caused in the impurity concentration in the semiconductor thin film, and the threshold voltage of each thin film transistor was changed. Although the voltage can be controlled, the difference between the threshold voltages of the respective thin film transistors is about 1.0 to 1.5 V, and the circuit cannot operate normally as a complementary circuit.

On the other hand, according to the thin film transistor manufactured by the above-described manufacturing method, when boron is injected into the active layer formed by the semiconductor thin film, it is simultaneously injected to form a defect level in the active layer. By adjusting the addition amount of argon, the difference between the threshold voltage of the n-channel thin film transistor and the threshold voltage of the p-channel thin film transistor changes.

That is, by adjusting the addition amount of boron and the addition amount of argon to be injected into the active layer, the polycrystalline semiconductor thin film forming the active layer is crystal-destructed, and the polycrystalline semiconductor thin film has a predetermined number of defects. A level is formed. By adjusting the number of defect levels formed in the polycrystalline semiconductor thin film, a thin film transistor using the polycrystalline semiconductor thin film as an active layer can function as an n-channel type and a p-channel type. Each has a predetermined threshold voltage according to the number.

Therefore, by adjusting the amount of boron and the amount of argon to be implanted into the active layer, the threshold of each of these thin film transistors is adjusted according to the number of defect levels formed in the polycrystalline semiconductor thin film. The value voltage can be controlled to a desired value, and the difference between the threshold voltages of these thin film transistors can be adjusted to an appropriate value.

As described above, when the active layer of the thin film transistor is formed, a low concentration impurity is implanted into the polycrystalline semiconductor thin film forming the active layer of the thin film transistor, and at the same time, an element or ion that causes crystal destruction is added. By the implantation, a defect level is formed in the active layer.
Therefore, the threshold voltage of each of the n-channel thin film transistor and the p-channel thin film transistor can be controlled to an appropriate value by one impurity implantation.

Thus, in the method of manufacturing a thin film transistor in which an n-channel thin film transistor and a p-channel thin film transistor are formed on the same substrate, the number of steps for causing a difference in the concentration of impurities implanted in each active layer is eliminated. It is possible to reduce the manufacturing cost. Therefore, it is possible to provide a method for manufacturing a thin film transistor at a low manufacturing cost.

In this embodiment, argon is added as an element causing crystal destruction of polycrystalline silicon.
Any other element that does not generate carriers in the polycrystalline thin film may be used, for example, an inert gas such as nitrogen gas or krypton (Kr) gas, or the same silicon as the element forming the semiconductor thin film. It is also possible to add silanes that generate elements.

[0075]

As described above, according to the present invention, there is provided a method of manufacturing a thin film transistor in which an n-channel thin film transistor and a p-channel thin film transistor can be formed on the same substrate at a low manufacturing cost. Can be.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing the configuration and appearance of a liquid crystal panel of a liquid crystal display device using a complementary circuit manufactured by a method for manufacturing a thin film transistor according to the present invention as a drive circuit.

FIG. 2 is a diagram schematically showing a configuration of a liquid crystal panel shown in FIG.

FIGS. 3A to 3E are views for explaining a method of manufacturing a thin film transistor according to the present invention.

FIGS. 4A to 4E are views for explaining another method for manufacturing a thin film transistor according to the present invention.

[Explanation of symbols]

Reference Signs List 10 liquid crystal panel 11, 31 glass substrate 12, 32 amorphous silicon thin film 13, 33 polycrystalline silicon thin film 15, 35 gate insulating film 16, 36 metal film 16 (a, b), 36 (a) , B) gate electrode 17 (as, bs), 37 (as, bs) source region 17 (ad, bd), 37 (ad, bd) drain region 18 interlayer insulating film 19 (as, bs) 39 (as, bs) ... source electrode 19 (ad, bd), 39 (ad, bd) ... drain electrode 20 (a, b), 40 (a, b) ... thin film transistor

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification FI FI theme coat ゛ (Reference) H01L 29/78 627G F-term (Reference) 2H092 JA25 JA29 JA38 JA42 JA47 KA04 KA07 MA08 MA13 MA17 MA27 MA30 MA35 MA37 MA41 NA25 NA27 5F045 AA08 AB03 AB04 AC01 AC19 AF07 BB08 BB16 CA15 DA57 HA12 HA15 HA16 HA18 5F052 AA02 BB07 DA02 DB03 EA15 FA05 JA01 JA04 JA10 5F110 AA08 AA16 BB01 BB02 BB04 CC02 DD02 EE02 EE13 GG03 GG03 GG02 HL03 HL06 NN04 NN72 NN73 PP03 PP33 PP35 QQ11

Claims (6)

[Claims] 1. A method for manufacturing a thin film transistor in which an n-channel thin film transistor and a p-channel thin film transistor having a polycrystalline semiconductor thin film as an active layer are formed on the same substrate, wherein the polycrystalline semiconductor thin film containing impurities formed on the substrate is Patterning to form an active layer; patterning a metal film formed on the active layer via an insulating film to form a gate electrode; implanting impurities using the gate electrode as a mask to activate the gate electrode; Forming a source region and a drain region each containing p-type or n-type impurities on both sides of the layer, wherein forming the active layer includes forming a defect level in the active layer. A method for manufacturing a thin film transistor, comprising: 2. The step of forming the active layer includes: forming an amorphous semiconductor thin film on a substrate; and implanting an impurity and an element that inhibits crystallization into the amorphous semiconductor thin film. 2. The method according to claim 1, further comprising the steps of: polycrystallizing the amorphous semiconductor thin film to form a polycrystalline semiconductor thin film including a defect level. 3. The step of forming the active layer comprises: forming a non-crystalline semiconductor film on a substrate by using a mixed gas obtained by mixing an impurity and an element inhibiting crystallization as a raw material gas for forming an amorphous semiconductor thin film; 2. The method according to claim 1, further comprising: forming a crystalline semiconductor thin film; and polycrystallizing the amorphous semiconductor thin film to form a polycrystalline semiconductor thin film including a defect level. A method for manufacturing a thin film transistor. 4. The method according to claim 2, wherein the element that inhibits crystallization is oxygen or nitrogen. 5. The step of forming the active layer includes: forming an amorphous semiconductor thin film on a substrate; polycrystallizing the amorphous semiconductor thin film to form a polycrystalline semiconductor thin film; 2. The method of manufacturing a thin film transistor according to claim 1, further comprising: implanting ions forming impurities and defect levels into the polycrystalline semiconductor thin film to destroy the crystal. 6. The method according to claim 5, wherein the ions forming the defect levels are inert gas ions or ions of the same element as the active layer.