JP2000266821A - Inspection system for iic bus circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an inspection system for an IIC bus circuit, by which the voltage control characteristic of a slave circuit can be inspected in an extremely short time. SOLUTION: In an inspection apparatus 21, two each of data for inspection, which are outputted to a slave circuit 2 are increased sequentially from '01H'. When the data reach an upper-limit value of 'FFH', the data are outputted in such a way that two each are decreased sequentially from 'FFH'. After the transmission of the data for inspection is completed by a bus interface part 22 for inspection, the level of a clock signal is maintained at a low level so as to be stopped. The ratio of its stop time is changed. The output waveform of a low-pass filter 24 is made to be nearly sinusoidal. Then, the inspection apparatus 21 measures the amplitude distorsion of the output waveform. Whether a D/A conversion level according to control data is obtained in the slave circuit 2 or not is inspected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a master circuit,
An IIC bus comprising a slave circuit that receives control data transmitted via an IC bus and performs a predetermined control operation based on the control data, and an inspection device that inspects voltage control characteristics of the slave circuit. The present invention relates to a circuit inspection system.

[0002]

2. Description of the Related Art FIG. 9 shows a conventional configuration example in which an inspection system for an IIC bus circuit is applied to an IC for a television. The master circuit 1 is mainly configured by a microcomputer or the like, and is different from the slave circuit 2 by an IIC (Inter IC).
It is connected via a bus 3. The IIC bus 3 includes a clock line 3a and a data line 3b, and is configured to transmit an address and data serially in synchronization with a clock signal.

The slave circuit 2 has an IIC bus interface (DAC controller) 4. That I
The IC bus interface 4 determines whether or not the addresses (slave address and subaddress) transmitted via the IIC bus 3 match the addresses assigned to itself, and if they match, subsequently transmits. The acquired data is fetched and output to the D / A converter 5.

The slave circuit 2 is a part (functional block) of the whole configured as an IC. For example, an amplifier 7 amplifies an audio signal supplied from the outside to an input terminal 6 and outputs the amplified signal via an output terminal 8. It is configured to output to the outside. The slave address is assigned to the IC, and the sub-address is assigned to the slave circuit 2.

The voltage signal that has been D / A converted by the D / A converter 5 is further converted to a current signal by a V / I converter 9 and given to the amplifier 7 to control the amplification factor of the amplifier 7. ing. The voltage signal output from the D / A converter 5 is also supplied to an output terminal 10 for inspection.

On the other hand, the inspection device 11 is used for inspecting whether or not the voltage control characteristic of the slave circuit 2 performed via the IIC bus 3 is normal, for example, in a manufacturing process. , An IIC bus interface (master) 13 and a voltage measuring device 14. The inspection control unit 12 outputs inspection data to the slave circuit 2 via the IIC bus interface 13 and the IIC bus 3. Further, the voltage measuring device 14 measures the level of the voltage signal output from the output terminal 10 of the slave circuit 2 and outputs the measurement result to the inspection control unit 12.

Next, the slave circuit 2 by the inspection device 11
Will be described with reference to FIG. For example, when the bit width of the parallel data is 8 bits, the inspection apparatus 11 changes the output data to the slave circuit 2 from “00H” to “01H” → “02H” → “03”.
Then, the level of the voltage signal that has been D / A converted by the D / A converter 5 increases by one step.

[0008] The inspection control section 12 measures the level of the voltage signal D / A-converted by the D / A converter 5 every time each data is output by the voltmeter 14, and according to the increase of the data. Check whether the voltage signal level has increased. When the above is performed up to the maximum value "FFH" of the data, the inspection ends (see FIG. 10B). In this way, it is checked that no bit missing or short circuit occurs in the output data bus of the D / A converter 5 and that the amplification factor of the amplifier 7 can be reliably controlled according to the control data.

[0009]

In such an inspection system, a voltage is measured every time data is incremented (in the case of 8 bits, 256 voltages including "00H" are included).
Times), the larger the data bit width, the longer the inspection time is required. The above inspection is performed for each functional block of the IC (that is, for each sub address).
Each time (each slave address) needs to be performed, so that the total time required for inspection becomes enormous. In addition, even when the bit width is 8 bits, the increase in the voltage level with respect to the increase of 1 bit is only a few mV lower, and the voltage measuring device 14 is required to have a relatively high accuracy.
There was such a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an inspection system for an IIC bus circuit capable of performing a voltage control characteristic inspection of a slave circuit in an extremely short time.

[0011]

According to a first aspect of the present invention, there is provided an inspection system for an IIC bus circuit.
A D / A converter for receiving control data transmitted from the master circuit via the IIC bus and performing D / A conversion, and an output terminal for outputting a voltage signal output from the D / A converter to the outside; A slave circuit in which a predetermined control operation is performed based on the control data; and a test circuit that transmits test data to the slave circuit via the IIC bus, based on a voltage signal obtained from an output terminal of the slave circuit. A testing device for testing a voltage control characteristic of a circuit, wherein the testing device outputs a testing clock signal to the IIC bus when transmitting the testing data; and A low-pass filter for filtering a signal; and an inspection unit for inspecting a voltage control characteristic based on an output signal waveform of the low-pass filter. And wherein the are.

With this configuration, the test clock signal output means outputs a test clock signal different from the clock signal used for normal data transmission to the IIC bus when transmitting the test data. This makes it possible to make the signal waveform output from the low-pass filter of the slave circuit a waveform suitable for inspection. Then, the inspection means inspects the voltage control characteristic based on the output signal waveform,
The measurement can be completed in an extremely short time as compared with the conventional method of measuring the voltage signal level for each data bit.

In this case, the inspection apparatus outputs the inspection data so as to sequentially increase the inspection data from a predetermined value and, when the data reaches the upper limit, sequentially reduce the data. The test clock signal output means stops the output of the clock signal each time the test data is transmitted, and changes the stop time so that the output signal waveform of the low-pass filter is substantially sinusoidal. It is preferable that the inspection means be configured to detect distortion of the output signal waveform and inspect voltage control characteristics based on the distortion.

According to this configuration, when the inspection apparatus sequentially increases the inspection data from a predetermined value and then outputs the data to decrease sequentially, the output signal waveform of the low-pass filter as a change trajectory of the inspection data becomes If the output time is substantially constant, the waveform becomes triangular. In addition, when the test clock signal output unit stops outputting the clock signal each time each test data is transmitted and changes the stop time, the triangular wave-like change trajectory is deformed on the time axis. Can be done. Therefore, by appropriately adjusting the stop time, the output signal waveform of the low-pass filter can be made substantially sinusoidal.

The inspection means measures, for example, the amplitude distortion rate of the substantially sinusoidal output signal waveform, and if the distortion rate is equal to or less than a predetermined value, determines that the voltage control characteristic is good, thereby performing the inspection. It can be done easily.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described with reference to the accompanying drawings.
One embodiment applied to C will be described with reference to FIGS. The same parts as those in FIG. 9 are denoted by the same reference numerals, and description thereof will be omitted. Only different parts will be described below.
In FIG. 1 showing the electrical configuration, in the present embodiment, the inspection device 11 is replaced with an inspection device 21, and the inspection device 21 is an inspection bus interface unit (inspection device) configured by a DSP (Digital Signal Processor). Clock signal output means, hereinafter referred to as a test bus I / F)
22.

The inspection bus I / F section 22 operates according to a control program as described later, and has a frequency of, for example, 100 kHz specified by the IIC bus standard.
The clock signal of Hz is controlled so as to be output intermittently on the clock line 3a of the IIC bus 3, and a clock signal for inspection is output. The output pattern of the test clock signal is determined based on a data table 22a stored in an internal memory, as described later. The test bus I / F unit 22 converts the 8-bit test data provided by the test control unit 23 into serial data and outputs the serial data on the data line 3b.

The test apparatus 21 receives an analog output signal supplied from the test output terminal 10 of the slave circuit 2 into an FFT analyzer 25 via a low-pass filter (LPF) 24. The time constant of the low-pass filter 24 is set to be sufficiently longer than the output interval of the 8-bit data serially supplied from the inspection device 21.

When the analog output signal filtered by the low-pass filter 24 is again A / D-converted, the FFT analyzer 25 performs a fast Fourier transform on the digital data to analyze the frequency of the analog output signal. The result of the frequency analysis performed by the FFT analyzer 25 is provided to the distortion rate measuring unit 26 to measure the amplitude distortion, and the measurement result is provided to the inspection control unit 23. In addition, FF
The T analyzer 25 and the distortion rate measuring unit 26 correspond to an inspection unit.

Next, the operation of the present embodiment will be described with reference to FIGS. The inspection control unit 23 outputs a predetermined value “01” as the inspection data to be output to the slave circuit 2.
From "H" to "03H", "05H", "07H",..., The data is sequentially increased by "2", and when "FDH" reaches the maximum value (upper limit value) "FFH", "FEH" , “FCH”, “FAH” and “2” at a time. From “04H” and “02H” to the minimum value “00H”
Output to return to

At this time, the test apparatus 21 starts transmission by lowering the data line from the high level to the low level while the clock signal is at the high level, and then outputs the IC including the slave circuit 2 only when the first test data is output. And the sub address of the slave circuit 2 are output. That is, for example, the slave address of the IC is set to “88”.
H "and the sub-address of the slave circuit 2 is" 00H ", Is transmitted, and at the time of outputting the subsequent inspection data, the same sub address and 1
Send 6 bits. 00H 02H 00H 04H ... Then, after transmission of the last data "00H", a series of test data is generated by raising the data line from low level to high level with the clock signal at high level. The transmission of is ended.

Here, FIG. 2 shows the output pattern of the above-described inspection data in the case of 4 bits as an example for convenience of illustration (however, the increase / decrease pattern of the data is reversed). ing). When the output interval of the inspection data is constant as shown in FIG. 2A, the output waveform of the low-pass filter 24 shown in FIG. 2B has a triangular waveform.

In the case of this embodiment, the output interval of the inspection data is not fixed as shown in FIG. 2A, and the inspection apparatus 21 outputs the output interval of each inspection data as shown in FIG. Is changed, the low-pass filter 2 shown in FIG.
4 is controlled so as to be substantially sinusoidal. This is performed by sequentially changing the time during which the inspection bus I / F unit 22 stops outputting the inspection clock signal after outputting each inspection data.

That is, each test data except the first "01H" is transmitted serially in 16 bits including the sub address to the slave circuit 2, but after completion of transmission of each test data, the level of the clock signal is kept low. If the output of the clock signal is stopped so as not to supply the next inspection data by maintaining the D / A converter 5, the D / A conversion output of the D / A converter 5 maintains the conversion output at that time. .

Therefore, by appropriately changing the level of the test data output from the test apparatus 21 and outputting a test clock signal for changing the stop time of the clock signal after each test data is output, the low-pass filter 2
4 can be arbitrarily shaped.

Here, in order to make the output waveform of the low-pass filter 24 substantially sinusoidal, the setting method of the output time ratio (including the stop time) of each test data is shown in FIG. This will be described with reference to FIG.

First, as shown in FIG. 4A, the output data sequence for inspection "1, 3, 5,..., D, F, E,.
2,0 ″, symbols a1 to a4, b5 indicating output time ratios
To b8, c9 to c12, and d13 to d16. Then, as shown in FIG. 4 (b), a unit circle having a radius of “1.000” is drawn around the origin of the xy coordinates, and six dividing lines that divide the diameter coincident in the vertical direction into eight equal parts are drawn in the horizontal direction. Then, the symbols a1 to d16 are assigned to the x, y axes and 16 intersections between each secant line and the circumference.

At this time, if an angle formed by a line segment drawn from the coordinate origin P to each code point R with respect to the x axis is θ, cos θ
Corresponds to the output time ratio of the inspection data corresponding to each code. Then, the output time ratio of the minimum value “0 (d16)” and the maximum value (upper limit value) “F (b8)” of the inspection data is set to “1.000” (significant digits are three digits after the decimal point). When both are arranged on the x-axis, the other sign is d
A1, a2, a3,...
Will be arranged.

For example, when cos θ is obtained for the code point a2 with Q as the perpendicular foot lowered from the code point R to the x-axis, cos θ = PQ θ = sin ⁻¹ (RQ / PR) = sin ⁻¹ (2 / 4) = 30 (deg), so that cos θ = cos (30 °) = 0.866.

[0030] That is, n = 1,2, ..., When ^{16, an (n = 1~4)} : cos (sin -1 (n / 4)) bn (n = 5~8): cos (sin - ¹ ((8−n) / 4)) cn (n = 9 to 12): cos (sin ⁻¹ ((n−8) / 4)) dn (n = 13 to 16): cos (sin ⁻¹ ( (16-n) / 4)), and specific numerical values are as follows. a1 = 0.968, b5 = 0.661, c9 = 0.968, d13 = 0.
661 a2 = 0.866, b6 = 0,866, c10 = 0,866, d14 = 0.
866 a3 = 0.661, b7 = 0.968, c11 = 0.661, d15 = 0.
968 a4 = 0, b8 = 1.000, c12 = 0, d16 = 1.
000 That is, as is clear from FIG.
The numerical values of the columns, bn column and dn column are respectively equal.

Next, the above example of 4-bit data will be extended to 8-bit data. In the case of 8-bit data, 256 pieces of inspection data “00H to FFH” are
It is assigned to the intersection of each circumference determined by dividing the diameter of the unit circle into 128 equal parts. Then, each of the 256 pieces of inspection data is divided into four groups of 64 in accordance with each quadrant of the xy coordinates in the same manner as in the case of 4 bits, and output time ratios corresponding to each data are a1 to a64, b65 to b65. b128, c129
Assuming that c192 and d193 to d256, an (n = 1 to 64): cos (sin- ¹ (n / 64)) bn (n = 65 to 128): cos (sin- ¹ ((128-n) / 64)) cn (n = 129 to 192): cos (sin ^-1 ((n-128) / 64)) dn (n = 193 to 256): cos (sin ^-1 ((256-n) / 64) ).

The specific numerical values are as follows: a1 = c129 = cos (sin ^-1 (1/64)) = 0.9998779 a2 = c130 = cos (sin ^-1 (2/64)) = 0.9995116 a3 = c131 = Cos (sin ^-1 (3/64)) = 0.9989007 ... a62 = c190 = cos (sin ^-1 (62/64)) = 0.2480391 ... a63 = c191 = cos (sin ^-1 (63/64) ) = 0.1760848 a64 = c192 = cos (sin ^-1 (64/64)) = 0.0000000 b65 = d193 = cos (sin ^-1 (63/64)) = 0.1760848 b66 = d194 = cos (sin ^-1 ( 62/64)) = 0.2480391 b67 = d195 = cos (sin ^-1 (61/64)) = 0.3025768 ... b126 = d254 = cos (sin ^-1 (2/64)) = 0.9995116 b127 = d255 = Cos (sin ^-1 (1/64)) = 0. 9998779... B128 = d256 = cos (sin ⁻¹ (0/64)) = 1.0000000.

Next, an actual output time is obtained based on each output time ratio. Minimum output time ratio excluding output time “0” of n = 64,192, n = 63,65,1
The output time of the inspection data corresponding to 91, 193 is minimum,
That is, the stop time is set to “0”. If the clock frequency of the IIC-bus is 100 kHz, the period is 10
μs, and it takes (8 + 8) × 10 μs = 160 μs to transmit one sub-address and test data. Therefore, each output time Tn (n = 1 to 256) is determined by calculating as follows.

T1 = T129 = (0.9998779 / 0.1760848) × 160 = 908.542 = 160 + 748.542 (μs) T2 = T130 = (0.9995116 / 0.1760848) × 160 = 908.209 = 160 + 748.209 (μs) ……… T61 = T189 = (0.3025768 / 0.1760848) × 160 = 274.937 = 160 + 114.937 (μs) T62 = T190 = (0.2480391 / 0.1760848) × 160 = 225.381 = 160 + 65.381 (μs) T63 = T191 = (0.1760848 / 0.1760848) × 160 = 160.000 = 160+ 0.000 (μs) T64 = T192 = 0.0000000 T65 = T193 = (0.1760848 / 0.1760848) × 160 = 160.000 = 160 + 0.000 (μs) T66 = T194 = (0.2480391 / 0.1760848) × 160 = 225.381 = 160 + 65.381 (μs )……… T127 = T255 = (0.9998779 / 0.1760848) × 160 = 908.542 = 160 + 748.542 (μs) T128 = T256 = (1.000000 / 0.1760848) × 160 = 908.653 = 160 + 748.653 (μs)

That is, 160 μs from the data output time Tn
Is the clock stop time. The clock stop time is set to the inspection bus I / F unit (DSP) 22.
The value divided by the system timer interrupt period is stored as STn in the control program of the inspection bus I / F unit 22 as the data table 22a, so that the inspection clock signal is output as described later.

The inspection apparatus 21 analyzes the frequency of the substantially sinusoidal output waveform from the low-pass filter 24 with the FFT analyzer 25 and obtains the amplitude level of the fundamental wave and each harmonic. Distortion rate measurement unit 2 based on
At 6, the amplitude distortion rate is measured. That is, the level of the test data is sequentially increased and decreased as shown in FIG.
For example, if the output data bus of the D / A converter 5 has a missing bit due to disconnection or the like, the output waveform of the low-pass filter 24 is distorted from a sine wave and contains a harmonic component. . Therefore, when the amplitude distortion rate measured by the distortion rate measurement unit 26 exceeds, for example, 0.5%, the inspection control unit 23 determines that there is an abnormality, and displays a message to that effect. To be notified.

Next, the operation of the inspection bus I / F section 22 will be described in detail with reference to FIGS. FIG.
5 is a flowchart showing the processing contents of the main routine in the control program of the inspection bus I / F unit 22. It should be noted that the part of the slave circuit 2 for transmitting the 8 bits of the main address first is omitted.

In FIG. 5, first, the inspection bus I /
The F unit 22 performs initial setting, and counts the clock cycle count value PRD and the clock level change point count value DTH1.
, DTH2 (see FIG. 8 (c)),
The counter N2 is set to "0". Then, the sub address of the slave circuit 2 to be inspected, which is given from the inspection control unit 23 and held in the register, is set, and the initial value “01H” of the inspection data is set (Step S).
1).

Next, when the counter N1 is set to "0" and initialized (step S2), it is determined whether or not the value of the counter N2 is "63" or "191" (step S3). If the values match, the process proceeds to step S4, which is a routine for setting and outputting one cycle of data. If the values do not match, the process proceeds to step S8. Here, the case where the value of the counter N2 is "63" or "191" means that the data output time T64 = T192.
= 0.0000000, and no data is output.

FIG. 6 is a detailed flowchart of the data setting processing routine in step S4. In FIG. 6, the inspection bus I / F unit 22 has a value of CNT which is a clock signal output counter (corresponding to the horizontal axis in FIG.
Is set to "0" (step A1), the counter N
It is determined whether 1 is equal to or less than “7” (step A).
2).

The counter N1 is a counter for outputting 8 bits of sub address and 8 bits of data, and corresponds to the output period of N1 = 0 to 7: subaddress N1 = 8 to 15: data (see FIG. 8B). ). Therefore, N
If 1 ≦ 7, the sub address bit X (X7, X6,
, X0) according to the value (1 (H), 0 (L)).
The level of DATA is set, and the level is set in an internal output buffer A (not shown) (step A3,
A5). Then, the data line 3b becomes the output buffer A
Driven by

If N1 ≦ 7 in step S3, the test bus I / F unit 22 sets the value of the counter N2 and the value of the data bit Y (Y7, Y6,..., Y0) (1,
0), the level of OUT DATA is set, and the level is set in the output buffer A (step A).
4). Here, the value of the counter N2 corresponds to 256 data, and the test data is set by increasing or decreasing the data value according to the value of the counter N2, and the data is serially output from the MSB. It is supposed to.

For example, if N2 = 0, the output data is the initial value "01H = 00000011B". If N2 = 1, the output data is "00000011B" and if N2 = 2, the output data is:
The output data is "00000101B".

FIGS. 8A and 8B show the inspection device 2
8 is a timing chart of the IIC bus when 1 outputs the sub address 01H and the data A1H, and FIG.
FIG. 4 shows an enlarged view of a high-level data waveform and a clock waveform.

Next, the inspection bus I / F unit 22 counts the system timer interrupt by the counter CNT (steps A6 and A7), and the value of the counter CNT is DTH1.
It is determined whether it is less than (Step A8). FIG.
As shown in (c), if CNT <DTH1, OUT
CLOCK (clock level) is set to low (L) (step A9), and if CNT ≧ DTH1, OUT
Set CLOCK to high (H) (step A1)
0). Then, the level of OUT CLOCK is set in an internal output buffer B (not shown) (step A).
11). Then, the clock line 3a is driven by the output buffer B. Note that output buffers A and B
Are designed to latch and hold the level once set.

Next, the inspection bus I / F unit 22 determines whether or not the value of the counter CNT is equal to DTH2 (step A12). As shown in FIG. 8C, CNT = DTH
If it is 2, OUT CLOCK is set to low (L) and set in the output buffer B (steps A13 and A1).
4) If the counter value CNT has not reached DTH2,
Move to step A6. Then, the timer interrupt is counted until the value of the counter CNT reaches PRD (steps A15 to A17). When the timer interrupt reaches PRD, "YES" is determined in step A17, and the process ends and returns.

Referring again to FIG. 5, when step S4 is completed, inspection bus I / F section 22 determines whether the value of counter N1 has reached "15" (ie, transmission of one 8-bit data has been completed). (Step S5).
If it has not reached "15", the counter N1 is incremented (step S6), and the routine goes to step S4. When the value of the counter N1 has reached "15",
The process proceeds to a stop time setting processing routine (step S7).

FIG. 7 is a detailed flowchart of the stop time setting processing routine. In FIG. 7, the test bus I / F unit 22 first sets OUT DATA to low (L) and sets it in the output buffer A (steps B1 and B2), and sets the stop time counter SCNT to “0”. (Step B3). Then, according to the value of the counter N2, the value of the stop time STn is read from the data table 22a stored in the internal memory and set (step B4). And the inspection bus I
The / F unit 22 counts the timer interrupt until the value of the counter SCNT reaches STn (Steps B5 to B
7) When STn is reached, "YES" is determined in the step B7, the process is terminated, and the process returns.

That is, as shown in FIGS. 8A and 8B, when the transmission of one cycle of data is completed, the stop time setting processing routine is executed, and during the set clock stop time, the clock signal level and The data levels are all low (L). During this stop time, the 8-bit data output immediately before is stopped in the IIC bus I / F 4 and the D / A converter 5 of the slave circuit 2.

Referring to FIG. 5, when step S7 is completed, inspection bus I / F section 22 increments the value of counter N2 (step S8),
Has reached “255” (ie, a series of 256
It is determined whether or not the transmission of the individual inspection data has been completed) (step S9).
Move to 2.

Therefore, every time the value of the counter N2 is incremented, step S4 is performed 16 times, and step S7 is performed by 1
Executed several times. Each stop time STn according to the value of the counter N2 is set at a time ratio at which the output waveform of the low-pass filter 24 of the inspection device 21 becomes a substantially sine wave as described above, and every time step S7 is executed. Is read from the data table 22a in step B4.
Then, as shown in FIG. 3A, the output time of each data changes according to the stop time.

On the other hand, in step S9, the counter N2
Is "255", the inspection bus I / F unit 2
2 executes the data transmission end sequence of steps S10 to S13. That is, OUT DATA and OUT
When CLOCK is set to high (H) (steps S10 and S11), OUT CLOCK is output to the output buffer B.
After setting the K level and raising the clock signal to the high level first (step S12), the output buffer A
Is set to the OUT DATA level and the data is raised to the high level (step S12). Then, the output of the inspection data to the slave circuit 2 ends.

In the case of inspecting the next circuit to be inspected in the same IC, the sub-address of the circuit is given from the inspection controller 23 so that the circuit shown in FIG.
The flowchart shown in FIG. Further, when another IC is to be inspected, a slave address (different main address) of the IC is given from the inspection control unit 23, and the same inspection is performed.

In the above embodiment, the counter value N2 = 6
Although the data “7FH” and “80H” corresponding to 3,191 are not output, for example, if there is an abnormality in the bits related to these data, the low-pass Since the output waveform of the filter 24 is distorted, an abnormality can be detected.

As described above, according to the present embodiment, the inspection apparatus 21 increases the inspection data output to the slave circuit 2 from the predetermined value “01H” by “2” sequentially.
When the maximum value “FFH” is reached, the output is sequentially reduced by “2”, and when the minimum value “00H” is reached, the clock signal is output by the test bus I / F unit 22 after the completion of transmission of each test data. Is maintained at a low level and stopped, and the output waveform of the low-pass filter 24 is made substantially sinusoidal by changing the ratio of the stop time. Then, the inspection device 21 measures whether or not the D / A conversion level corresponding to the control data is obtained in the slave circuit 2 by measuring the amplitude distortion of the output waveform.

That is, after outputting a series of inspection data, the inspection can be performed collectively based on the waveform drawn by the change trajectory of the inspection data. The measurement can be completed in an extremely short time as compared with the method of measuring. Further, the high-precision voltage measuring device 14 which has been conventionally required is not required.

When the test data is to be sequentially increased, the data is increased by "2" so as to take an odd value from "01H", and when the test data is to be sequentially reduced from the maximum value "FFH", "FEH" is used. "" To reduce the value by "2" so as to take an even value. Therefore, in order to inspect all the data, the same inspection data is output as compared with the case where the minimum inspection value is increased by "1" and the maximum value is reached, and then the maximum inspection value is decreased by "1". It can eliminate the data output time by half. Therefore, the inspection can be performed in a shorter time.

The test bus I / F section 22 is formed of a DSP, and a test clock signal for making the output signal waveform of the low-pass filter 24 substantially sinusoidal is generated by high-speed arithmetic processing of the DSP. Can be output,
The total output time of the test clock signal can be reduced, and therefore the time required for the test can be reduced. In addition, the stop time STn is stored in the data table 22a in advance, the data is read out, and the test clock signal having a different stop time is sequentially output, so that the arithmetic processing load on the DSP can be reduced. Furthermore, the time required for the inspection can be further reduced by shortening the output interval of the inspection data.

The present invention is not limited to the embodiment described above and shown in the drawings, and the following modifications or extensions are possible. When the inspection data is sequentially increased, the data is increased from “00H” to “02H”, “04H”,..., And when the data reaches “FFH” from “FEH”,
“FDH”, “FBH”,... May be sequentially reduced. In addition, when increasing from "00H" by "1" and sequentially decreasing from "FFH", it may be decreased by "1". The bit width of the address and data is not limited to 8 bits. The output pattern of the inspection data is not limited to the output waveform of the low-pass filter 24 having a substantially sinusoidal waveform. For example, FIG.
As shown in (2), test data may be given so that the output waveform of the low-pass filter 24 becomes a triangular wave, and the distortion factor measuring unit 26 may measure the amplitude distortion using each frequency component of the triangular wave as a fundamental wave. In addition, the measurement may be similarly performed for other arbitrary waveforms.

The 256 test data are transferred to the test bus I
The data table may be held and read out inside the / F unit 22 in the same manner as the stop time STn. Also,
An input data buffer is provided in the inspection bus I / F unit 22 so that the inspection control unit 23 transmits the inspection bus I / F before the inspection starts.
You may make it transmit to the F part 22 collectively. Also,
Similarly, for the slave address, the test bus I /
An input address buffer is provided in the F unit 22, and before the start of the inspection, the setting of the slave address and the sub address to be inspected is transmitted from the inspection control unit 23 to the inspection bus I / F unit 22 in a lump. The inspection bus I / F unit 22 may be configured to sequentially and automatically inspect all the set inspection targets. The inspection means is not limited to the one that measures the distortion rate of the output waveform of the low-pass filter. For example, the inspection means captures the output waveform as drawing data and detects a difference (deviation) from the normal output waveform drawing data. The inspection may be performed in such a manner.

Even if the test data is not necessarily output between the minimum value and the maximum value of the data value range that can be taken on the IIC bus, the predetermined value and the upper limit value are set to appropriate values, and a part of the data value range is set. Only the inspection may be performed. If the DSP has sufficient processing capacity, each clock stop time STn is stored in the data table 22a.
Instead of holding the values, the values may be calculated and calculated in real time. Further, the test clock signal output means is not limited to a DSP, but may be a CPU (microcomputer). In this case, the test control unit 23 and the test clock signal output means are integrally formed. You may. Not limited to TV control ICs, II
The present invention can be applied to any circuit using the C bus.

[0062]

Since the present invention is as described above,
The following effects are obtained. According to the IIC bus circuit test system, the test clock signal output means outputs the test clock signal different from the clock signal used for normal data transmission when transmitting the test data. By outputting the signal to the bus, the signal waveform output from the low-pass filter of the slave circuit can be made a waveform suitable for inspection. The inspection means inspects the voltage control characteristic based on the output signal waveform, thereby completing the measurement in an extremely short time as compared with the conventional method of measuring the voltage signal level for each data bit. be able to.

According to the inspection system of the IIC bus circuit according to the second aspect, the inspection apparatus outputs the inspection data so as to sequentially increase the inspection data from a predetermined value and then decrease the inspection data sequentially.
The output of the clock signal is stopped each time the inspection clock signal output unit transmits each inspection data, and the output signal waveform of the low-pass filter can be made substantially sinusoidal by appropriately changing the stop time. . Then, the inspection means measures, for example, the amplitude distortion rate of the output signal waveform,
If the distortion rate is equal to or less than a certain value, it is determined that the voltage control characteristics are good, so that the inspection can be easily performed.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an electrical configuration according to an embodiment of the present invention.

FIG. 2 shows a case where the output interval of inspection data is constant;
(A) shows the output waveform of the D / A converter, and (b) shows the output waveform of the low-pass filter.

FIG. 3 is a diagram corresponding to FIG. 2 when an output interval of inspection data is changed.

FIG. 4 is a view for explaining the principle of determining a stop time of a clock signal so as to obtain a substantially sinusoidal low-pass filter output.

FIG. 5 is a flowchart showing processing contents of a main routine of an inspection bus interface unit;

FIG. 6 is a flowchart showing the processing content of a one-cycle data setting processing routine;

FIG. 7 is a flowchart showing processing contents of a stop time setting processing routine;

8 is a timing chart in the case of outputting a sub-address and data (b) in synchronization with a clock signal (a), and FIG. 8 (c) is an enlarged view showing a part of (a) and (b).

FIG. 9 is a diagram corresponding to FIG. 1 showing a conventional technique.

FIG. 10 is a diagram showing an output pattern of conventional inspection data.

[Explanation of symbols]

2 is a slave circuit, 3 is an IIC bus, 5 is a D / A converter, 10 is an output terminal, 21 is an inspection device, 22 is an inspection bus interface unit (inspection clock signal output means, DSP), 22a is a data table, 25 is FFT
An analyzer (inspection unit) 26 indicates a distortion rate measurement unit (inspection unit).

Claims (2)

[Claims] 1. A D / A converter for receiving control data transmitted from a master circuit via an IIC bus and performing D / A conversion, and an output for outputting a voltage signal output from the D / A converter to the outside A slave circuit having a terminal and performing a predetermined control operation based on the control data; and a voltage signal transmitted from the output terminal of the slave circuit, transmitting test data to the slave circuit via the IIC bus. And a testing device for testing a voltage control characteristic of the slave circuit based on the following. The testing device outputs a testing clock signal to the IIC bus when transmitting the testing data. Means, a low-pass filter for filtering the voltage signal, and inspecting a voltage control characteristic based on an output signal waveform of the low-pass filter. Inspection system IIC bus circuit, wherein a and a 査 means. 2. An inspection apparatus sequentially increases inspection data from a predetermined value, and when the data reaches an upper limit value, outputs the data so as to sequentially decrease the data, and the inspection clock signal output means includes: The output signal waveform of the low-pass filter is configured to be substantially sinusoidal by stopping the output of the clock signal every time each test data is transmitted, and changing the stop time thereof. 2. The system for testing an IIC bus circuit according to claim 1, wherein the system is configured to detect the distortion of the ICC and inspect the voltage control characteristic based on the distortion.