JPH0385813A - Delay generator - Google Patents

Abstract

PURPOSE:To obtain a delay with high accuracy by providing a means converting an initial value set with calculation or the like in response to a required delay into a value acquiring actually the required delay. CONSTITUTION:A code converter 9 receiving a value being the division of a full scale in response to a required delay as a control signal 3 converts the setting value and outputted to a delay generating element 1 in parallel. Upon the receipt of a latch enable signal, a TTL latch 11 latches a parallel signal being a control signal 3, supplies it to an internal digital analog converter(DAC) 12, the internal DAC 12 converts the digital signal into an analog signal and it is supplied to a comparator of a timing control circuit 13 as a threshold level deciding an output timing of an input signal 2. The comparator receives the threshold level as one input and a ramp voltage of a linear ramp generator is used as the other input, and when the ramp voltage reaches the threshold level or below, the output signal 4 is outputted to the outside of the device. Thus, the required delay is obtained with high accuracy.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for changing the phase of a digital signal, for example.
The present invention relates to a delay generating device that delays the output of an input signal by a delay amount according to a value set by a control signal.

[Conventional technology]

Figure 2 shows, for example, the digital programmable IL! introduced in the 4th edition of Analog Devices' Data Book (published in May 1988). FIG. 2 is a block diagram showing the configuration of a digital programmable delay generating device using a delay element AD9500. In the figure, 1 is a digital programmable delay generating element AD9500 (hereinafter abbreviated as delay generating element), which delays input signal 2 in accordance with control signal 3 given from a controller (not shown) and outputs this as output signal 4. Output to outside the device.

An external resistor 7 is connected between the Rs terminal of the delay generating element l and the negative power supply -V, and the positive power supply +V is connected to the positive power supply terminal +V.
An external capacitor 8 is connected between the positive power supply terminal +Vs, the Cs terminal, and the positive power supply terminal +Vs.

The control signal 3 is applied to the data input terminal Do%D as an 8-bit parallel signal. The TTL latch 11 becomes a data input terminal when a launch enable signal is input. The data applied to -Dl is latched, and the latched data is applied to an internal DAC (digital to analog converter) 12. The reference current setting circuit 17 sets a reference current according to the resistance value of the external resistor 7 and supplies it to the internal DAC 12 and the timing control circuit 13.

The internal DAC 12 converts the digital signal of the set value given from the TTL latch 11 into an analog signal and supplies it to the timing control circuit 13 . The timing control circuit I3 has a linear ramp generator that lowers the ramp voltage and a comparator that compares the ramp voltage and a threshold level, and supplies an analog signal from the internal DAC 12 as the threshold level to one input of the comparator. Further, the human power signal 2 is transmitted to the timing control circuit 13 via the trigger terminal and the differential analog human power stage 14.
is input.

The timing control circuit 13 is connected to the positive power supply terminal +Vs and the C3 terminal, and outputs the input signal 2 to the operational amplifier 15 according to the comparison result of the comparator.

The non-inverting output terminal of the operational amplifier 15 is connected to the base of a transistor 16a whose emitter is connected to the output terminal Q, and the inverting output terminal is connected to the base of a transistor 16b and t6 whose emitters are connected to the output terminals Q and QR, respectively.
connected to the base of c. These transistors 16a
, 16b, and 16c form an ECL circuit, and their respective collectors are connected to the ECL common terminal.

The operation of delaying an input signal by the delay generating device configured as above will be explained.

The reference current inside the delay element 1 is set by an external resistor 7, and the time constant is set by an external capacitor 8 to obtain the full scale of the delay amount determined by the rate of fall of the lamp voltage of the linear lamp generator. decide. The required delay amount is obtained by dividing the full-scale delay amount, and y! A value for dividing the full scale according to the extension is output as a control signal 3 to the delay generating element I in parallel. When the latch enable signal is output, the TTL launch 11 latches the control @ signal 3 and provides it to the internal DAC 12. The internal DAC 12 converts the applied parallel digital signal into an analog signal and supplies it to the comparator of the timing control circuit 13 as a threshold level for determining the output timing of the human input signal 2. The comparator takes the given threshold level as one input and the lamp voltage of the linear ramp generator as the other input.

On the other hand, when the input signal 2 is input, the ramp of the linear ramp generator in the timing control circuit 13
The cycle starts and the lamp voltage falls. The comparator compares the lamp voltage with the threshold level, and when the lamp voltage reaches the threshold level or less, outputs the output signal 4 as a delayed signal of the input signal 2 to the outside of the device. .

[Problem to be solved by the invention]

The conventional digital programmable delay generation device is configured as follows, and the full-scale delay amount set by an external resistor 7 and capacitor 8 is divided, and a value is calculated according to the required delay amount. As control signal 3, delay l! Since it only has a means to supply the element l, an external resistor 7 and capacitor 8 that determine the full scale delay t=i are required.
There are problems in that high accuracy is required and the equipment cost is high.

Furthermore, even if a highly accurate product is used, individual differences in analog circuits such as the linear ramp generator that constitute the timing control circuit 13 inside the delay generating element 1 are unavoidable, and the delay as per the set value cannot be avoided. The problem was that it was difficult to obtain quantities.

The present invention has been made to solve such problems, and by providing a set value conversion means for correcting the set values, the required amount of delay can be increased regardless of individual differences in the device components. The purpose of this invention is to provide a delay generating device that can achieve high accuracy.

[Means for Solving the Problems] The delay generation device of the present invention includes means for converting an initial set value obtained by calculation etc. into a value such that the actually obtained aI extension becomes the required delay amount; It is particularly noted that the present invention is provided with means for delaying the input signal by a value set by the input signal.

[Effect]

The delay generation device of the present invention converts the set value obtained by calculation into a value that actually provides the required delay amount, and then outputs an input signal delayed based on the converted set value to the outside of the device.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 is a block diagram showing the configuration of a delay generating device according to the present invention. As in the conventional example described above, the digital programmable delay generating element AD9500 manufactured by Analog Devices, Inc. is used as the delay generating element. In addition, in the drawings, the same reference numerals indicate the same or corresponding parts as in the conventional example, and detailed explanation thereof will be omitted.

The delay generating device according to the present invention includes, for example, a programmable R
The code converter 9 is connected to a code converter 9 that converts the set value of the input control signal 3 and supplies it to the delay generating element 1, and the control signal 3 is converted through the address line of the ROM.
is input, the code is converted, and the converted data is provided as a digital parallel signal 10 to the TTL latch 11 via the data output line.

Prior to the operation of delaying an input signal by the delay generator configured as described above, a procedure for setting conversion data of a control signal in the code converter 9 will be explained.

After setting the reference current inside the delay element 1 with an external resistor 7 and setting a time constant with an external capacitor 8 to determine the full scale of the delay amount, the delay amount is corrected by test measurement.

First, the code converter 9 is set so that its input and output are equal, and the control signal 3 is set so that each bit of the code signal input to the internal DAC 12 changes.
The value of is changed and input to the code converter 9, and the amount of delay of the signal output from the device is tested and measured. As a result of test measurements, the input signal code closest to the required delay amount is collected.

When the control signal 3 set by calculation from the full-scale delay amount is input to the code converter 9, the contents of the code converter 9 are rewritten so that this set value becomes the signal code obtained as a result of the test measurement. The modification is completed.

Next, the operation of delaying an input signal will be explained.

The required delay amount is obtained by dividing the full scale delay amount, and a value for dividing the full scale according to the delay amount is given to the code converter 9 as the control signal 3.

The code converter 9 converts the setting value given by the control signal 3 and outputs it to the delay generating element 1 in parallel.

When the latch enable signal is output, the TTL chip 11 latches the parallel signal of the control signal 3 and outputs the internal DA.
Give to C12. The internal DA and CI2 convert the applied parallel digital signal into an analog signal and provide it to the comparator of the timing control circuit 3 as a threshold level for determining the output timing of the input signal 2.

The comparator takes the applied threshold level as one input and the lamp voltage of the linear ramp generator as the other input.

On the other hand, when the input signal 2 is input, the ramp of the linear ramp generator in the timing control circuit 13
The cycle begins and the lamp voltage decreases. The comparator compares the lamp voltage with the threshold level, and outputs an output signal 4 to the outside of the device when the lamp voltage reaches the threshold level or lower.

Note that this embodiment is effective when the number of switching control signals 3 is small compared to the resolution of the internal DAC 12, but if the resolution of the internal DAC is low, delay generating elements may be connected in series to It is also possible to apparently improve the resolution of the DAC.

Also, depending on the conditions, the delay amount may be set to, for example, 10 ns.

When switching to four stages of 25 ns, 30 ns, and 50 ns, the values for each of the four stages may be written and stored in the programmable ROM used as the code converter 9, and the required stage may be designated by the control signal 3. For example, in the case of four stages, two signal lines for the control signal 3 are sufficient, and the effect of reducing the burden on the controller, which is the means for outputting the control signal, can be obtained.

Further, in this embodiment, a programmable ROM is used as the code converter, but a system such as a one-chip microcomputer may also be used.

〔Effect of the invention〕

The delay generation device of the present invention eliminates the occurrence of problems caused by individual differences in devices by providing means for converting an initial value set by calculation etc. according to the required delay amount into a value that actually obtains the required delay amount. This makes it possible to exclusively correct the errors obtained, and has the excellent effect of obtaining a highly accurate delay amount.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a delay generating device according to the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional delay generating device. 1... Delay generation element 2... Input signal 3... Control signal 4... Output signal 7... External resistor 8
...External capacitor 11...TTL launch 1
2... Internal DAC 13... Tie control circuit In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A delay generating device that delays an input signal according to a set value and outputs it to the outside of the device, which includes means for converting the set value and means for delaying the input signal based on the converted value. A characteristic delay generator.