JPH02140018A - Signal level detector - Google Patents

Abstract

PURPOSE:To measure the level with high accuracy even in a minimum bit by sampling a high level and a low level of a signal to be tested individually, holding the result and using a voltage measurement means so as to measure the difference voltage. CONSTITUTION:A couple of sample-and-hold circuits 5, 6 comprise analog switches 5a, 6a and hold capacitors 5b, 6b holding a voltage level obtained via them. Positive poles of capacitors 5b, 6b are connected individually to lines l1, l2 and negative poles are connected in common. A high level output VH of a D/A converter 2 led on the line l1 is charged in the capacitor 5b, a low level output VL led to the line l2 is charged in the capacitor 6b and each level is kept. Thus, the voltage between the lines l1 and l2 is a difference voltage Vx between the outputs VH and VL and the the voltage of the LSB of the converter 2 is directly measured by measuring the voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a device for detecting the amplitude level of a signal such as the output of a digital/analog converter.

BACKGROUND OF THE INVENTION A digital-to-analog converter (hereinafter referred to as a D/A converter) is an electronic circuit that generates a current or voltage analog output proportional to a weighted digital code input. A D/A converter is an essential electronic device when, for example, computer output drives analog equipment, and whether the D/A converter is operating accurately is a very important issue regarding the operating accuracy of analog equipment. It is. Conventionally, digital data that produces a constant level of output is input to the input terminal of a D/A converter, and the output level is measured with a measuring device such as a level meter to determine whether the D/A converter is operating normally. I was testing something.

Problems to be Solved by the Invention However, in the so-called static test method as described above, since the measured values of each input data include errors, a measuring means with high precision measurement ability is required. Furthermore, if the D/A converter to be tested is, for example, 8 bits, the measuring means is 1/2' = 1/256
It must be possible to read minute level outputs corresponding to the least significant bit (LSB).

Therefore, it was necessary to prepare highly accurate measuring equipment for the test, which required high costs. Therefore, there has been a desire for a test circuit that can detect signal levels with a simple configuration.

An object of the present invention is to solve the above-mentioned technical problems and to provide a signal level detection device that has a simple configuration and can detect signal levels with high accuracy.

Means for Solving the Problems The present invention provides a plurality of sample and hold circuits that individually sample and hold high and low levels of a signal, and a difference between the high and low levels obtained from the sample and hold circuits. This is a signal level detection device characterized by including a differential voltage measuring means for measuring voltage.

Function: The signal level detection device according to the present invention samples the high level and low level of a signal to be tested individually by a sample hold circuit, and then holds the high level and low level of the signal to be tested. The differential voltage of is measured by a differential voltage measuring means.

Thereby, the level of even the least significant bit (ILSB) can be measured with high precision.

Embodiment FIG. 1 is a block diagram showing the electrical configuration of a digital/analog converter test circuit (hereinafter referred to as test circuit) 1, which is a signal level detection device according to an embodiment of the present invention, and FIG. is a time chart showing the operation. Referring to FIG. 1, a test circuit 1 sets a tarokk signal generation circuit 3 that supplies a clock signal CK and a test digital input code, and outputs a signal to a D/A converter 2 in synchronization with the clock signal CK. An input code setter 4 that supplies a digital input code, a pair of sample bold circuits 5.6 that individually sample the high level and low level of the output of the D/A converter 2, and hold the outputs; A drive circuit 7 that drives the hold circuit, and a voltmeter 8 that is a differential voltage measuring means that measures the differential voltage between the high level and low level obtained through the sample and hold circuit.
It is formed by.

The pair of sample and hold circuits 5 and 6 include analog switches 5a and 6a;
It consists of a bold capacitor 5b, 6b which holds the voltage level obtained through the hold capacitor 5a.
The positive terminals of the terminals b and 6b are individually connected to the lines tl and 12, respectively, and the negative terminals are commonly connected to the ground line 13. Further, each of the analog switches 5a and 6a described above receives an analog switch drive signal S1 derived from the drive circuit 7,
S2 controls the 0N10FF operation and its timing. Analog switch drive signal S1. S2 is
It is generated by a frequency dividing circuit (not shown) in the drive circuit 7 based on the clock signal CK.

The D/A converter 2 has, for example, an 8-bit input,
A clock signal CK of the frequency to be measured (for example, 100KH2) is applied to the clock terminal ck, and a pair of inputs capable of comparing the least significant bit (LSB) as shown in Table 1 is applied to the data input terminal d. Data D
a pair of input data Da2 .al, Dbl, or adjacent bits as shown in Table 2) that can be compared. Db2
Either one of these is applied alternately in synchronization with the clock signal CK.

Table 1 Table 2 As a result, the output terminal V of the D/A converter 2.

The input data Dal or Da2 (
The high level output VH corresponding to the input data Dbl or Db2
Low level outputs VL (generally referred to as Db) are alternately derived in synchronization with the clock signal CK.

FIG. 2(1) is a waveform showing the timing of the clock signal CK. The frequency of the clock signal CK is, for example, 1
It is 00KH2.

FIG. 2(2) is a waveform showing the timing of input data Da and Db given to the D/A converter 2. FIG. The pair of input data D is synchronized with the clock signal CK.
a and Db are alternately input to the data terminal d of the D/A converter 2 shown in FIG.

FIG. 2(3) shows the waveform of the output Vout of the D/A converter 2, which is a high-level output Vout corresponding to the pair of input data Da and Db in synchronization with the clock signal CK.
H and low level output VL are alternately derived.

FIGS. 2(4) and 2(5) show the timing of the analog switch drive signals St and S2 applied to the analog switches 5a and 6a, which are sampling means. The analog switch drive signals Sl and S2 are both alternately derived at a frequency of 1/2 of the clock signal CK, that is, twice the cycle of the clock signal CK, and the drive signal S1 drives the analog switch 5a to drive the D/A converter. 2 high level output■
The drive signal S2 drives the analog switch 6a to output a low level output VL to the line 12.

Referring again to FIG. 1, the high level output VH of the D/A converter 2 thus led out to the line 11 is:
The low level output VL charged in the capacitor 5b and led out to the line 12 is charged in the capacitor 6b, and the respective levels are maintained. Therefore line I 1
, 12 is the difference voltage Vx (-VH-VI-) between the high-level output VH and the low-level output VL.
By measuring this differential voltage Vx, the voltage of ILSB of the D/A converter 2 can be directly measured.

If the level of the differential voltage Vx is low, as shown in FIG. All you have to do is measure it with a total of 8.

By comparing the value of the differential voltage Vx obtained in this way with the predetermined specifications of the D/A converter 2, it is possible to determine whether the operation is good or bad.

In the above-described embodiment, the input of the D/A converter 2 to be tested is 8 bits, but there is no problem in using a D/A converter using just a few bits. Further, the detected signal is not limited to the output of the D/A converter 2, and the source thereof is not limited as long as it is a periodically fluctuating signal.

Effects of the Invention As described above, the signal level detection device according to the present invention samples the high level and low level of the signal to be tested individually by the sample and hold circuit, holds them, and then samples the high and low levels of the signal to be tested by the sample and hold circuit. The obtained difference voltage between the high level and the low level is measured by a difference voltage measuring means.

Thereby, the level of even the least significant bit (ILSB) can be measured with high precision, and the quality of the operation can be quickly determined.

In the present invention, since the signal level is detected by a so-called dynamic operation, it is also possible to measure the voltage of the above-mentioned ILSB when the frequency of the clock signal is changed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the electrical configuration of a test circuit 1 for a digital/analog converter according to an embodiment of the present invention, FIG. 2 is a time chart showing its operation, and FIG. 3 is a diagram showing another embodiment of the present invention. FIG. 2 is a block diagram illustrating a portion of an example. 1... Digital/analog converter test circuit, 2...
・Digital/analog converter, 3... Clock signal generator, 4... Input data setter, 5.6... Sample hold circuit, 8... Voltmeter, 9... Differential amplifier, CK...Clock signal, D...Input data, SL
, S2...Analog switch drive signal agent Patent attorney Keiichi Saikyo

Claims (1)

[Claims] A plurality of sample-and-hold circuits that individually sample and hold high and low levels of a signal, and a difference that measures the voltage difference between the high and low levels obtained from the sample-and-hold circuits. A signal level detection device comprising voltage measuring means.