JP2000261110A - Printed wiring board and semiconductor mounting structure using the same - Google Patents

Printed wiring board and semiconductor mounting structure using the same

Info

Publication number
JP2000261110A
JP2000261110A JP6469099A JP6469099A JP2000261110A JP 2000261110 A JP2000261110 A JP 2000261110A JP 6469099 A JP6469099 A JP 6469099A JP 6469099 A JP6469099 A JP 6469099A JP 2000261110 A JP2000261110 A JP 2000261110A
Authority
JP
Japan
Prior art keywords
lead
wiring board
printed wiring
electrode pads
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6469099A
Other languages
Japanese (ja)
Inventor
Kazuhiko Abe
和彦 阿部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP6469099A priority Critical patent/JP2000261110A/en
Publication of JP2000261110A publication Critical patent/JP2000261110A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To obtain a larger junction strength without making electrode pads larger by providing a plurality of electrode pads for fusing and joining the projecting electrodes and making leader lines from each electrode pad in radial directions whose origin is a predetermined deformation center. SOLUTION: Lands 602 corresponding to respective electrode pads 601 aligned and arranged at positions opposing to projecting electrodes are formed to connect the electrode pads 601 with wiring. Then, main parts 604a of leader lines 604 for electrically connecting respective electrode pads 601 with the lands 602, which parts 604a being at least near the connecting parts of the respective electrode pads 601, are drawn out inwardly from the respective electrode pads 601 along radiating directions whose origin is a predetermined deformation center O on the board. According to this construction, a part of the projecting electrode is fused towards the main part 604a of leader line when they are joined and the contact angle between the surface of the board and the projecting electrode become larger. Therefore, the junction strength of the projecting electrode against thermal stress is improved.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、プリント配線基板
およびこれを用いた半導体実装装置に係り、特に、突起
状電極を利用して他の基板と接続されるプリント配線基
板およびこれを用いた半導体実装装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board and a semiconductor mounting device using the same, and more particularly, to a printed wiring board connected to another substrate using a protruding electrode and a semiconductor using the same. It relates to a mounting device.

【0002】[0002]

【従来の技術】電子機器の高集積化に伴って様々な半導
体装置が提案されているが、その中でも、BGA(ボー
ル・グリッド・アレイ)あるいはLGA(ランド・グリ
ッド・アレイ)と称される半導体装置が注目されてい
る。
2. Description of the Related Art A variety of semiconductor devices have been proposed along with higher integration of electronic equipment. Among them, a semiconductor device called a BGA (ball grid array) or LGA (land grid array) has been proposed. The device is receiving attention.

【0003】これらの半導体装置では、インターポーザ
(あるいはチップ・キャリア)基板の表面に半導体素子
(半導体チップ)が搭載され、外部接続用電極パッドが
裏面に形成されることから、従来の半導体装置であるQ
FP(クワッド・フラット・パッケージ)と比較した場
合、そのサイズを大幅に縮小できるという利点がある。
さらに、外部接続用電極パッドのピッチも、QFPの
0.3〜0.5mmに対して1.0〜1.5mmと広く
できるため、プリント配線基板への実装が容易になると
いう利点もある。
In these semiconductor devices, a semiconductor element (semiconductor chip) is mounted on the surface of an interposer (or chip carrier) substrate, and external connection electrode pads are formed on the back surface. Q
As compared with FP (quad flat package), there is an advantage that the size can be greatly reduced.
Furthermore, since the pitch of the external connection electrode pads can be widened to 1.0 to 1.5 mm with respect to the QFP of 0.3 to 0.5 mm, there is an advantage that mounting on a printed wiring board becomes easy.

【0004】図9は、従来の一般的なBGAの構成およ
びその実装構造を示した断面図である。BGA1は、イ
ンターポーザ基板20の表面に半導体素子10を載置し
て構成される。半導体素子10とインターポーザ基板2
0とはボンディングワイヤ30により電気的に接続さ
れ、半導体素子10およびボンディングワイヤ30は、
封止樹脂としてのレジン40により、インターポーザ基
板20に対して封止、固定されている。
FIG. 9 is a sectional view showing the structure of a conventional general BGA and its mounting structure. The BGA 1 is configured by mounting the semiconductor element 10 on the surface of an interposer substrate 20. Semiconductor element 10 and interposer substrate 2
0 is electrically connected to the semiconductor element 10 and the bonding wire 30 by a bonding wire 30.
It is sealed and fixed to the interposer substrate 20 by a resin 40 as a sealing resin.

【0005】上記したBGA1が実装されるプリント配
線基板80と前記インターポーザ基板20とは、インタ
ーポーザ基板20の裏面に予め形成された突起状電極5
0を介して、電気的および機械的に接続される。前記突
起状電極50としては、融点が200℃以下のはんだ合
金が用いられる。なお、LGAの場合、インターポーザ
基板20の裏面には電極パッドが形成されるのみで、上
記した突起状電極は形成されない。
[0005] The printed wiring board 80 on which the BGA 1 is mounted and the interposer substrate 20 are formed by forming the protruding electrodes 5 formed on the back surface of the interposer substrate 20 in advance.
0 and are electrically and mechanically connected. As the projecting electrode 50, a solder alloy having a melting point of 200 ° C. or less is used. In the case of the LGA, only the electrode pads are formed on the back surface of the interposer substrate 20, and the above-mentioned protruding electrodes are not formed.

【0006】上記したBGA1を含む半導体実装装置2
では、インターポーザ基板20に高密度、高精細配線を
形成する場合、アルミナセラミックス基板が用いられ、
その熱膨張係数は6〜7ppm/℃程度である。これに
対して、プリント配線基板80として多用されるガラス
エポキシに代表される有機系基板では、熱膨張係数が1
2〜15ppm/℃程度である。
Semiconductor mounting device 2 including BGA 1 described above
In the case where a high-density, high-definition wiring is formed on the interposer substrate 20, an alumina ceramic substrate is used,
Its coefficient of thermal expansion is about 6-7 ppm / ° C. On the other hand, an organic substrate typified by glass epoxy which is frequently used as the printed wiring board 80 has a thermal expansion coefficient of 1
It is about 2 to 15 ppm / ° C.

【0007】このように、インターポーザ基板20とプ
リント配線基板80とでは熱膨張係数が大きく異なるた
め、半導体素子10が動作時に発生する熱により、両者
の熱膨張係数の差に起因して大きな熱応力が発生する。
この熱応力は、各基板20、80を接合する突起状電極
50の外周部分に集中し、最悪の場合には接合部に疲労
破壊が生じ得る。
As described above, since the thermal expansion coefficients of the interposer substrate 20 and the printed wiring board 80 are significantly different, the heat generated during operation of the semiconductor element 10 causes a large thermal stress due to the difference between the two. Occurs.
This thermal stress is concentrated on the outer peripheral portion of the protruding electrode 50 that joins the substrates 20 and 80, and in the worst case, fatigue failure may occur at the joint.

【0008】図10は、前記突起状電極50の拡大断面
図であり、溶融接合された突起状電極50は、図示した
ように太鼓状となり、熱膨張係数の差に起因して生じる
熱応力は接合界面のくびれ部分に集中し、基板80(電
極パッド801)との接合角度θが小さく(鋭角に)な
るほど集中度合いが増す。この接合角度θを大きくする
ためには、基板間の間隙を広くすれば良いが、溶融接合
された際の突起状電極50の形状は、はんだの表面張力
やBGA1の質量にも依存するため、一般的には制御困
難である。
FIG. 10 is an enlarged sectional view of the projecting electrode 50. The projecting electrode 50 fused and joined has a drum shape as shown in FIG. The concentration is concentrated on the constricted portion of the bonding interface, and the degree of concentration increases as the bonding angle θ with the substrate 80 (electrode pad 801) decreases (is sharper). In order to increase the bonding angle θ, the gap between the substrates may be widened. However, the shape of the protruding electrode 50 at the time of fusion bonding depends on the surface tension of the solder and the mass of the BGA 1. Generally, it is difficult to control.

【0009】このような問題を解決するために、特開平
7−321247号公報あるいは特開平9−27047
7号公報では、電極バッド801の形状を変形方向に長
径とすることで、熱応力発生方向に関して電極と基板と
の接触角度を大きくし、接合強度を高める技術が開示さ
れている。
In order to solve such a problem, Japanese Patent Application Laid-Open No. 7-321247 or Japanese Patent Application Laid-Open No. 9-27047 has been proposed.
Japanese Patent Application Laid-Open No. 7-74139 discloses a technique of increasing the contact angle between an electrode and a substrate in the direction of thermal stress generation by increasing the shape of an electrode pad 801 in the deformation direction to increase the bonding strength.

【0010】[0010]

【発明が解決しようとする課題】上記した従来技術で
は、電極パッドの寸法が熱応力の発生方向に沿って長く
なり、その面積も従来よりも大型化してしまうため、プ
リント配線基板60上での実装密度が低下してしまうと
いう問題があった。
In the above-mentioned prior art, the dimensions of the electrode pads become longer in the direction in which the thermal stress is generated, and the area of the electrode pads becomes larger than before. There is a problem that the mounting density is reduced.

【0011】本発明の目的は、上記した従来技術の課題
を解決し、電極パッドを大型化することなく、強い接合
強度が得られるようにしたプリント配線基板およびこれ
を用いた半導体実装装置を提供することにある。
An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a printed wiring board capable of obtaining a strong bonding strength without increasing the size of an electrode pad, and a semiconductor mounting apparatus using the same. Is to do.

【0012】[0012]

【課題を解決するための手段】上記した目的を達成する
ために、本発明は、突起状電極が溶融接合される複数の
電極パッドと、前記各電極パッドから引き出された引き
出し配線とを設け、前記各引き出し配線を、所定の変形
中心を基点とした放射方向に沿って引き出すようにした
点に特徴がある。
In order to achieve the above-mentioned object, the present invention provides a plurality of electrode pads to which a protruding electrode is fused and joined, and a lead-out wiring drawn from each of the electrode pads. It is characterized in that each of the lead-out wirings is drawn out in a radial direction from a predetermined deformation center as a base point.

【0013】上記した特徴によれば、電極パッドの形状
を大型化することなく、その引き出し配線を利用して突
起状電極と基板表面との接触角度を大きくすることがで
きる。したがって、基板面積を大型化することなく、す
なわち基板の実装密度を低下させることなく、突起状電
極の接合強度を向上させることができる。
According to the above feature, the contact angle between the protruding electrode and the surface of the substrate can be increased by using the lead-out wiring without increasing the size of the electrode pad. Therefore, the bonding strength of the protruding electrodes can be improved without increasing the substrate area, that is, without lowering the mounting density of the substrate.

【0014】[0014]

【発明の実施の形態】以下、図面を参照して本発明を説
明する。図1は、本発明の第1実施形態であるプリント
配線基板60の部分平面図であり、基板表面には、たと
えばBGAのインターポーザ基板に形成された突起状電
極と対向する位置に多数の電極パッド601が整列配置
されると共に、各電極パッド601に対応して、当該電
極パッドを基板裏面や基板内部に形成した配線(図示せ
ず)と接続するためのランド602およびビア603が
形成されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a partial plan view of a printed wiring board 60 according to a first embodiment of the present invention, and a large number of electrode pads are provided on a surface of the substrate, for example, at positions opposed to protruding electrodes formed on a BGA interposer substrate. 601 are arranged and arranged, and corresponding to each electrode pad 601, a land 602 and a via 603 for connecting the electrode pad to a wiring (not shown) formed on the back surface of the substrate or inside the substrate are formed. .

【0015】前記各電極パッド601およびランド60
2は引き出し配線604を介して電気的に接続される。
本実施形態では、各引き出し配線604のうち、少なく
とも各電極パッド601との接続部に近い主要部604
aが、基板60上の所定の変形中心Oを基点として、各
電極パッド601から放射方向に沿って内側に引き出さ
れている。
Each of the electrode pads 601 and the lands 60
2 is electrically connected via a lead wiring 604.
In the present embodiment, at least a main portion 604 of each lead-out wiring 604 which is close to a connection portion with each electrode pad 601.
a is drawn inward from each of the electrode pads 601 in the radial direction with a predetermined deformation center O on the substrate 60 as a base point.

【0016】図2(a) は、前記プリント配線基板60の
電極パッド601周辺の拡大平面図、同図(b) は、BG
A1のインターポーザ基板20を当該プリント配線基板
60の電極パッド601に前記突起状電極50を介して
接合した本発明の第2実施形態の、前記放射方向に沿っ
たX−X線での断面図であり、前記と同一の符号は同一
または同等部分を表している。
FIG. 2A is an enlarged plan view around the electrode pads 601 of the printed wiring board 60, and FIG.
FIG. 9 is a cross-sectional view of the second embodiment of the present invention in which the interposer substrate 20 of A1 is joined to the electrode pads 601 of the printed wiring board 60 via the protruding electrodes 50 along the XX line along the radiation direction. The same reference numerals as those described above represent the same or equivalent parts.

【0017】プリント配線基板60の表面には、少なく
とも電極パッド601および引き出し配線主要部604
aの前記電極パッド601との接続部近傍を避けるよう
にソルダーレジスト層605が形成されている。このソ
ルダーレジスト層605は、ソルダーレジストのパター
ン形成精度やプリント配線基板60の加工精度を考慮し
て、電極パッド601から0.05〜0.1mm程度の
クリアランスを設けてパターン形成されている。
On the surface of the printed wiring board 60, at least the electrode pads 601 and the lead wiring main portion 604
The solder resist layer 605 is formed so as to avoid the vicinity of the connection portion with the electrode pad 601 in FIG. The solder resist layer 605 is formed with a clearance of about 0.05 to 0.1 mm from the electrode pad 601 in consideration of the solder resist pattern formation accuracy and the processing accuracy of the printed wiring board 60.

【0018】このような構成のプリント配線基板60に
BGA1のインターポーザ基板20を突起状電極50に
より接合すると、図2(b) に示したように、突起状電極
50の一部が引き出し配線主要部604aへも溶け出
す。このため、基板60の表面と突起状電極50との接
触角θが大きくなり、必要に応じて接触角θを鈍角とす
ることができる。したがって、各基板20、60の熱膨
張力の差異により、プリント配線基板60がインターポ
ーザ基板20に対して図中右方向、すなわち前記放射方
向に沿って変形中心Oの方向へ熱応力を受けても、この
熱応力に対する接合強度を飛躍的に向上させることがで
きる。
When the interposer substrate 20 of the BGA 1 is joined to the printed wiring board 60 having such a configuration by the protruding electrodes 50, as shown in FIG. Also dissolves into 604a. For this reason, the contact angle θ between the surface of the substrate 60 and the protruding electrode 50 increases, and the contact angle θ can be made obtuse if necessary. Therefore, even if the printed wiring board 60 receives thermal stress in the right direction in the drawing with respect to the interposer board 20, that is, in the direction of the deformation center O along the radiation direction due to the difference in thermal expansion force between the boards 20, 60. Thus, the bonding strength against this thermal stress can be dramatically improved.

【0019】ところで、上記した熱応力はBGAの発熱
時のみならす、発熱状態からの冷却時にも生じ、それぞ
れの場合で熱応力の発生箇所が異なる。例えば、インタ
ーポーザ基板20がセラミックであるBGAを本発明の
プリント配線基板60へ実装する場合、温度上昇時には
プリント配線基板60がインターポーザ基板20に対し
て相対的に伸びる。このため、突起状電極50の外周部
では、図3に破線で囲ったように、最大歪みがインター
ポーザ基板20側では放射方向に沿って内側に生じ、プ
リント配線基板60側では放射方向に沿って外側に生じ
る。
Incidentally, the above-mentioned thermal stress is generated only when the BGA generates heat, and also occurs when cooling from the heat generating state, and the location where the thermal stress is generated differs in each case. For example, when a BGA in which the interposer substrate 20 is ceramic is mounted on the printed wiring board 60 of the present invention, the printed wiring board 60 extends relatively to the interposer substrate 20 when the temperature rises. For this reason, at the outer peripheral portion of the protruding electrode 50, as indicated by the broken line in FIG. 3, the maximum distortion occurs on the interposer substrate 20 side in the radial direction and on the printed wiring board 60 side in the radial direction. Occurs on the outside.

【0020】これに対して、温度下降時にはプリント配
線基板60がインターポーザ基板20に対して相対的に
収縮するため、最大歪みの発生箇所が前記温度上昇時と
は逆になる。すなわち、図4に破線で囲ったように、イ
ンターポーザ基板20側では放射方向に沿って外側に生
じ、プリント配線基板60側では放射方向に沿って内側
に生じる。
On the other hand, when the temperature decreases, the printed wiring board 60 contracts relatively to the interposer substrate 20, so that the location where the maximum distortion occurs is opposite to that when the temperature rises. That is, as indicated by the broken line in FIG. 4, the light emission occurs outward in the radial direction on the interposer substrate 20 side, and the light emission occurs in the radial direction on the printed wiring board 60 side.

【0021】ここで、温度が高い状況下では、はんだの
クリープ現象が起りやすく接合部が変形し易いため、高
温状態では残留歪みが減少する傾向にある。これに対し
て、低温状態に移行する場合はクリーブ現象が起り難い
ので、高温状態に移行する場合と比較して大きな残留歪
みが発生する。すなわち、温度下降時の方が接合部にク
ラックが発生しやすい。したがって、プリント配線基板
60の熱膨張係数K60とインターポーザ基板20の熱膨
張係数K20とを比較し、K60>K20ならば、前記図1に
関して説明したように、引き出し配線を放射方向に沿っ
て内側に引き出し、K20>K60ならば、図5に示したよ
うに、引き出し配線を放射方向に沿って外側に引き出す
ようにすれば良い。
Here, when the temperature is high, the creep phenomenon of the solder is likely to occur and the joint is easily deformed, so that the residual strain tends to decrease at a high temperature. On the other hand, when the state shifts to the low temperature state, the cleave phenomenon hardly occurs, so that a large residual strain is generated as compared with the case where the state shifts to the high temperature state. In other words, cracks are more likely to occur at the joints when the temperature drops. Therefore, the coefficient of thermal expansion K60 of the printed wiring board 60 is compared with the coefficient of thermal expansion K20 of the interposer board 20, and if K60> K20, as described with reference to FIG. If K20> K60, as shown in FIG. 5, the lead wiring may be drawn outward in the radial direction.

【0022】なお、基板の最外周および最外周から1〜
2列目迄の電極パッド601に関しては、一般的に周辺
回路への配線引き回しの容易さから、図1とは逆に中心
から外側に向かって配線を引出すことが多い。この場合
は配線の容易さと信頼性とのバランスを考慮して、いず
れの側へ引出すかを決定すればよい。ただし、外周部の
電極パッドでも、例えば、電源端子やGND端子のよう
に直近のビアから内層に接続するような場合や、あるい
は内側に配置された電極パッドでビアを通して内層ある
いは裏面で配線を引回す必要がある場合は、ビアを歪み
の中心方向に形成し、そこまでの配線に関しても歪みの
中心方向に引出してビアに接続するような配線パターン
とすればよい。
The outermost circumference of the substrate and 1 to 1 from the outermost circumference
Regarding the electrode pads 601 up to the second row, wiring is generally drawn outward from the center in the opposite direction to that in FIG. In this case, it is only necessary to determine which side to pull out in consideration of the balance between ease of wiring and reliability. However, the outer electrode pads may be connected to the inner layer from the nearest via, for example, a power supply terminal or a GND terminal, or a wiring may be drawn on the inner layer or the back surface through the via with the inner electrode pad. If it is necessary to turn the via, a via may be formed in the direction of the center of the strain, and the wiring up to that may be drawn out in the direction of the center of the strain and connected to the via.

【0023】上記したように、本実施形態によれば、電
極パッド601の形状を大型化することなく、既存の引
き出し配線604を利用して突起状電極と基板表面との
接触角度を大きくすることができるので、基板面積を大
型化することなく、したがって基板の実装密度を低下さ
せることなく、突起状電極と基板との接合強度を向上さ
せることができる。
As described above, according to the present embodiment, the contact angle between the protruding electrode and the substrate surface can be increased by using the existing lead wiring 604 without increasing the size of the electrode pad 601. Therefore, the bonding strength between the protruding electrode and the substrate can be improved without increasing the substrate area, and without reducing the mounting density of the substrate.

【0024】なお、プリント配線基板60の表面に形成
するソルダーレジスト層605を、前記図2に示したよ
うに電極パッド601から所定のクリアランスを設けて
形成しても、ソルダーレジスト層605の形成誤差等に
より、図6に示したように、ソルダーレジスト層605
の開口605aに対して電極パッド601が偏心し、引
き出し配線604が露出しなくなる可能性がある。
Note that even if the solder resist layer 605 formed on the surface of the printed wiring board 60 is formed with a predetermined clearance from the electrode pad 601 as shown in FIG. As shown in FIG. 6, the solder resist layer 605
There is a possibility that the electrode pad 601 is eccentric with respect to the opening 605a, and the extraction wiring 604 is not exposed.

【0025】したがって、ソルダーレジスト層605に
形成する開口は、図7に示したように、引き出し配線6
04を露出させるための領域605bを別途に追加した
形状とするか、あるいは図8に示したように、引き出し
配線604の引き出し方向に長径の楕円形状605c等
とすることが望ましい。このようにすることにより、ソ
ルダーレジスト層605の形成誤差等にかかわらず、引
き出し配線604を少なくとも電極パッド601との接
続部近傍において露出させることができる。
Therefore, the opening formed in the solder resist layer 605 is, as shown in FIG.
It is preferable that a region 605b for exposing the substrate 04 is separately added, or as shown in FIG. 8, an elliptical shape 605c having a longer diameter in the lead-out direction of the lead-out wiring 604. By doing so, the lead wiring 604 can be exposed at least in the vicinity of the connection portion with the electrode pad 601 irrespective of the formation error of the solder resist layer 605 and the like.

【0026】[0026]

【発明の効果】本発明によれば、電極パッドの形状を大
型化することなく、その引き出し配線を利用して突起状
電極と基板表面との接触角度を大きくすることができる
ので、基板面積を大型化することなく、したがって基板
の実装密度を低下させることなく、突起状電極の接合強
度を向上させることができる。
According to the present invention, the contact angle between the protruding electrode and the surface of the substrate can be increased by utilizing the lead-out wiring without increasing the size of the electrode pad. It is possible to improve the bonding strength of the protruding electrodes without increasing the size, and thus without reducing the mounting density of the substrate.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施形態であるプリント配線基板
の平面図である。
FIG. 1 is a plan view of a printed wiring board according to a first embodiment of the present invention.

【図2】本発明の第2実施形態である半導体実装装置の
主要部の平面図および断面図である。
FIG. 2 is a plan view and a cross-sectional view of a main part of a semiconductor mounting device according to a second embodiment of the present invention.

【図3】応力歪の発生原理を説明するための断面図であ
る。
FIG. 3 is a cross-sectional view for explaining the principle of generation of stress strain.

【図4】応力歪の発生原理を説明するための断面図であ
る。
FIG. 4 is a cross-sectional view for explaining the principle of generation of stress strain.

【図5】本発明の他の実施形態であるプリント配線基板
の平面図である。
FIG. 5 is a plan view of a printed wiring board according to another embodiment of the present invention.

【図6】ソルダーレジスト層と電極パッドとの位置関係
を示した平面図である。
FIG. 6 is a plan view showing a positional relationship between a solder resist layer and an electrode pad.

【図7】ソルダーレジスト層と電極パッドとの位置関係
を示した平面図である。
FIG. 7 is a plan view showing a positional relationship between a solder resist layer and an electrode pad.

【図8】ソルダーレジスト層と電極パッドとの位置関係
を示した平面図である。
FIG. 8 is a plan view showing a positional relationship between a solder resist layer and an electrode pad.

【図9】従来のBGAおよびその実装構造を示した断面
図である。
FIG. 9 is a cross-sectional view showing a conventional BGA and its mounting structure.

【図10】従来の突起状電極による基板の接合構造を示
した断面図である。
FIG. 10 is a cross-sectional view showing a conventional bonding structure of a substrate using protruding electrodes.

【符号の説明】[Explanation of symbols]

20…インターポーザ基板、50…突起状電極、60…
プリント配線基板、601…電極パッド、602…ラン
ド、603…ビア、604…引き出し配線、605…ソ
ルダーレジスト層
20 ... interposer substrate, 50 ... protruding electrode, 60 ...
Printed wiring board, 601: electrode pad, 602: land, 603: via, 604: lead-out wiring, 605: solder resist layer

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】 突起状電極が溶融接合される複数の電極
パッドと、 前記各電極パッドから引き出された引き出し配線とを具
備し、 前記各引き出し配線が、所定の変形中心を基点とした放
射方向に沿って引き出されたことを特徴とするプリント
配線基板。
A plurality of electrode pads to which the protruding electrodes are melt-bonded; and lead wires drawn from the respective electrode pads, wherein each of the lead wires has a radial direction with a predetermined deformation center as a base point. A printed wiring board, wherein the printed wiring board has been drawn out along.
【請求項2】 前記引き出し配線は、変形中心を基点と
した放射方向に沿って内側に引き出されたことを特徴と
する請求項1に記載のプリント配線基板。
2. The printed wiring board according to claim 1, wherein the lead-out wiring is drawn inward along a radial direction with a deformation center as a base point.
【請求項3】 前記引き出し配線は、変形中心を基点と
した放射方向に沿って外側に引き出されたことを特徴と
する請求項1に記載のプリント配線基板。
3. The printed wiring board according to claim 1, wherein the lead-out wiring is drawn out in a radial direction with the deformation center as a base point.
【請求項4】 前記プリント配線基板の表面には、少な
くとも各電極パッドおよびその引き出し配線の一部を露
出させる窓部を除いて絶縁膜が形成され、前記窓部は、
各電極パッドごとに各引き出し配線の引き出し方向に長
径であることを特徴とする請求項1ないし3のいずれか
に記載のプリント配線基板。
4. An insulating film is formed on a surface of the printed wiring board except for a window portion exposing at least a part of each electrode pad and a lead-out wiring thereof, and the window portion includes:
4. The printed wiring board according to claim 1, wherein each of the electrode pads has a longer diameter in a lead-out direction of each lead-out wiring.
【請求項5】 絶縁基板の一方の主面に半導体素子を搭
載し、他方の主面に突起状電極が形成された半導体装置
を、表面に電極パッドが形成されたプリント配線基板上
に、前記突起状電極と電極パッドとが接合されるように
実装してなる半導体実装装置において、 前記プリント配線基板に形成された各電極パッドの引き
出し配線が、所定の変形中心を基点とした放射方向に沿
って引き出されたことを特徴とする半導体実装装置。
5. A semiconductor device having a semiconductor element mounted on one main surface of an insulating substrate and a protruding electrode formed on the other main surface is mounted on a printed circuit board having electrode pads formed on the surface. In a semiconductor mounting device in which a protruding electrode and an electrode pad are mounted so as to be joined, the lead-out wiring of each electrode pad formed on the printed wiring board extends along a radial direction with a predetermined deformation center as a base point. A semiconductor mounting device characterized by being drawn out.
【請求項6】 前記プリント配線基板は、その熱膨脹係
数が前記絶縁基板よりも大きく、前記引き出し配線は、
変形中心を基点とした放射方向に沿って内側に引き出さ
れたことを特徴とする請求項5に記載の半導体実装装
置。
6. The printed wiring board has a larger coefficient of thermal expansion than the insulating substrate, and the lead-out wiring is
6. The semiconductor mounting device according to claim 5, wherein the semiconductor mounting device is drawn inward along a radial direction with the deformation center as a base point.
【請求項7】 前記プリント配線基板は、その熱膨脹係
数が前記絶縁基板よりも小さく、前記引き出し配線は、
変形中心を基点とした放射方向に沿って外側に引き出さ
れたことを特徴とする請求項5に記載の半導体実装装
置。
7. The printed wiring board has a smaller coefficient of thermal expansion than the insulating substrate, and the lead-out wiring is
6. The semiconductor mounting device according to claim 5, wherein the semiconductor mounting device is drawn outward along a radial direction with the deformation center as a base point.
【請求項8】 前記プリント配線基板の表面には、少な
くとも各電極パッドおよびその引き出し配線の一部を露
出させる窓部を除いて絶縁膜が形成され、前記窓部は、
各電極パッドごとに各引き出し配線の引き出し方向に長
径であることを特徴とする請求項5ないし7のいずれか
に記載の半導体実装装置。
8. An insulating film is formed on a surface of the printed wiring board except for a window for exposing at least a part of each electrode pad and a lead-out wiring thereof, and the window includes:
8. The semiconductor mounting device according to claim 5, wherein each of the electrode pads has a longer diameter in a lead-out direction of each lead-out wiring.
JP6469099A 1999-03-11 1999-03-11 Printed wiring board and semiconductor mounting structure using the same Pending JP2000261110A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6469099A JP2000261110A (en) 1999-03-11 1999-03-11 Printed wiring board and semiconductor mounting structure using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6469099A JP2000261110A (en) 1999-03-11 1999-03-11 Printed wiring board and semiconductor mounting structure using the same

Publications (1)

Publication Number Publication Date
JP2000261110A true JP2000261110A (en) 2000-09-22

Family

ID=13265410

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6469099A Pending JP2000261110A (en) 1999-03-11 1999-03-11 Printed wiring board and semiconductor mounting structure using the same

Country Status (1)

Country Link
JP (1) JP2000261110A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002185112A (en) * 2000-12-13 2002-06-28 Kyocera Corp Mounting structure for wiring board and semiconductor device
DE10239080A1 (en) * 2002-08-26 2004-03-11 Infineon Technologies Ag Integrated circuit used in wafer level packages comprises an elastically deformable protrusion, a contact unit, and a rewiring unit for electrically connecting an active semiconductor section of the circuit to the contact unit
JP2006108313A (en) * 2004-10-04 2006-04-20 Rohm Co Ltd Packaging board and semiconductor device
JP2006114777A (en) * 2004-10-15 2006-04-27 Toshiba Corp Printed wiring substrate and information processing device mounting the same
US7863525B2 (en) 2008-03-18 2011-01-04 Kabushiki Kaisha Toshiba Printed circuit board and electronic device
US8286124B2 (en) 2009-06-22 2012-10-09 Fujitsu Limited Printed circuit board design assisting method, printed circuit board design assisting device, and storage medium
JP2017022149A (en) * 2015-07-07 2017-01-26 日立オートモティブシステムズ株式会社 Wiring board

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002185112A (en) * 2000-12-13 2002-06-28 Kyocera Corp Mounting structure for wiring board and semiconductor device
DE10239080A1 (en) * 2002-08-26 2004-03-11 Infineon Technologies Ag Integrated circuit used in wafer level packages comprises an elastically deformable protrusion, a contact unit, and a rewiring unit for electrically connecting an active semiconductor section of the circuit to the contact unit
JP2006108313A (en) * 2004-10-04 2006-04-20 Rohm Co Ltd Packaging board and semiconductor device
JP2006114777A (en) * 2004-10-15 2006-04-27 Toshiba Corp Printed wiring substrate and information processing device mounting the same
US7659481B2 (en) 2004-10-15 2010-02-09 Kabushiki Kaisha Toshiba Printed wiring board and information processing device incorporating the board
JP4625674B2 (en) * 2004-10-15 2011-02-02 株式会社東芝 Printed wiring board and information processing apparatus mounting this board
US7863525B2 (en) 2008-03-18 2011-01-04 Kabushiki Kaisha Toshiba Printed circuit board and electronic device
US8286124B2 (en) 2009-06-22 2012-10-09 Fujitsu Limited Printed circuit board design assisting method, printed circuit board design assisting device, and storage medium
JP2017022149A (en) * 2015-07-07 2017-01-26 日立オートモティブシステムズ株式会社 Wiring board

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