JP2000260950A - Semiconductor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve high-frequency characteristics by suppressing an eddy current, even in an inductance element with small dimensions. SOLUTION: A coil is formed on a P-type silicon substrate 1 by a second- layer wiring 11, and a polycrystalline silicon containing an N-type high- concentration impurity is embedded into a hole 5 provided in the P-type silicon substrate 1 at the lower portion of the coil for forming a P-N junction in an area to the P-type silicon substrate 1, and an reverse bias is applied to the P-N junction and hence spreading a depletion layer in the P-type silicon substrate 1 and forming an electrically insulated region.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device incorporating an inductor element and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, transistors,
Incorporation of an inductor element (coil) in addition to resistance and capacitance has been performed. In an integrated circuit that operates at a high frequency, if impedance matching is not performed between the signal source and the input unit, not only will the input signal be distorted, but also the signal will be reflected to the signal source side and cannot be transmitted efficiently. There is a problem. By using not only the resistance and the capacitance but also the inductor element, it is easy to achieve impedance matching, and the above problem can be solved.

FIG. 13 is a schematic sectional view showing a conventional example in which an inductor element is incorporated in a semiconductor device. An oxide film 2 is formed on a P-type silicon substrate 1, and an interlayer insulating film 7 is formed on the oxide film 2. A first-layer wiring 8 and an interlayer insulating film 9 are formed on the interlayer insulating film 7. A second-layer wiring 11 forming a spiral coil is formed on the interlayer insulating film 9, and a first-layer wiring 8 is formed.
Is connected to the center end of the second-layer wiring (coil) 11 through a connection hole 10 provided in the interlayer insulating film 9.

However, when an alternating current is applied to the inductor element incorporated in the semiconductor device, an eddy current is generated in the silicon substrate below the coil by magnetic flux, and power is wasted due to eddy current loss. There is a disadvantage that it will. In particular, when an inductor element is used in a matching circuit or the like, the high-frequency characteristics deteriorate.

Therefore, conventionally, a PN junction is formed by diffusing impurities in the form of islands or stripes from the top surface or the back surface of the silicon substrate below the inductor element, and a depletion layer is applied by applying a reverse bias to the element during operation. The frequency at which the element operates as an inductor has been improved by widening and suppressing the generation of eddy current.

FIG. 14 is a schematic sectional view showing another conventional example in which an inductor element is incorporated in a semiconductor device.
In the P-type silicon substrate 1, a high-concentration N-type impurity diffusion region 16 is formed.
, An N-type impurity diffusion region 15 is formed. Metal interconnection 18 is formed on oxide film 2, and metal interconnection 18 is connected to high-concentration N-type impurity diffusion region 16 through connection hole 17 provided in oxide film 2, 15 is supplied with a potential.

The P-type silicon substrate 1 and the N-type impurity diffusion region 15 form a PN junction, and when a reverse bias is applied between the P-type silicon substrate 1 and the N-type impurity diffusion region 15, A depletion layer region is formed around N-type impurity diffusion region 15. Since the depletion layer region has high electrical insulation, eddy current can be suppressed.

FIG. 15 is a plan view showing a state in which an N-type impurity diffusion region is formed in the conventional silicon substrate shown in FIG. In FIG. 15, N-type impurity diffusion regions 15 having a diameter of 14 μm are arranged at intervals of 4 μm.
Here, it is assumed that when the N-type impurity diffusion region 15 having a depth of 10 μm is formed, it is expanded by 7 μm in the lateral direction. In this case, the area ratio of holes in the depletion layer region is about 55%.

[0009]

In the semiconductor device in which the inductor element shown in FIG. 14 is incorporated, in order to increase the effect of suppressing the eddy current, the depletion layer region is formed deep in the depth direction of the silicon substrate in order to increase the effect. When trying to diffuse the impurity, the impurity region also expands in the lateral direction. Therefore,
Particularly, in the case of an inductor element having a small size, the area of the depletion layer region becomes smaller (the area of the impurity region becomes larger) as compared with the inductor size, so that the effect of reducing the eddy current is hardly obtained, and the high frequency characteristics deteriorate. There's a problem.

An object of the present invention is to provide a semiconductor device incorporating an inductor element capable of improving the effect of suppressing eddy current even in an inductor element having a small size and improving high-frequency characteristics, and a method of manufacturing the same. Is to provide.

[0011]

According to the present invention, there is provided a semiconductor device comprising:
An inductor element is formed on a semiconductor substrate, and polycrystalline silicon containing a high-concentration impurity of the opposite conductivity type is buried in a hole provided in the semiconductor substrate below the inductor element to form a gap between the semiconductor substrate and the semiconductor substrate. Forming a PN junction,
By applying a reverse bias to the PN junction, a depletion layer can be expanded in the semiconductor substrate.

According to the present invention, in a method of manufacturing a semiconductor device having an inductor element incorporated therein, a hole or a trench is formed in a semiconductor substrate below the inductor element.
A semiconductor substrate and polycrystalline silicon containing high-concentration impurities of the opposite conductivity type are grown over the entire surface to fill the holes or trenches, heat treatment is performed to activate the high-concentration impurities, and diffusion is performed to form holes or trenches. A high-concentration impurity region is formed in a semiconductor substrate along a wall surface, and a PN junction is formed between the semiconductor substrate and the high-concentration impurity region.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic sectional view showing a first embodiment of the semiconductor device of the present invention. As shown in FIG.
An oxide film 2 is formed on a mold silicon substrate 1,
Holes 4 are formed in the P-type silicon substrate 1 and the oxide film 2 deeply in the direction perpendicular to the P-type silicon substrate 1.

In the P-type silicon substrate 1, a high concentration N-type impurity region 6 is formed along the wall surface of the hole 4,
The P-type silicon substrate 1 and the high-concentration N-type impurity region 6
An N junction is formed.

Polycrystalline silicon 5 doped with a high concentration N-type impurity is buried in the hole 4.
The polycrystalline silicon 5 deposited on the upper surface of the oxide film 2 is etched to form a potential supply wiring for supplying a potential to the polycrystalline silicon 5 embedded in the hole 4.

An interlayer insulating film 7 is formed on the polycrystalline silicon 5, and a first-layer wiring 8 is formed on the interlayer insulating film 7. An interlayer insulating film 9 is formed on the interlayer insulating film 7 and the first layer wiring 8. A second-layer wiring 11 forming a coil is formed on the interlayer insulating film 9.
The first layer wiring 8 is formed in the connection hole 1 provided in the interlayer insulating film 9.
0 is connected to the second-layer wiring 11.

FIG. 2 is a bird's-eye view of the first-layer wiring and the second-layer wiring in this embodiment. The second-layer wiring 11 forms a spiral coil, and one end of the coil is connected to the first-layer wiring 8 via the connection hole 10. The other end of the coil is connected to another element by a connection wiring (not shown).

The width of the coils is about 10 microns, the thickness is about 0.5 microns, and the spacing between the coils is about 10 microns. Although the number of turns of the coil is less than 1.5 turns because of simplification in FIG. 2, a coil of 3 or 4 turns is actually used.

Next, an example of a manufacturing process of the semiconductor device shown in the first embodiment will be described.

FIGS. 3 to 6 are schematic sectional views of the manufacturing process. First, as shown in FIG. 3, an oxide film 2 is formed on the surface of a P-type silicon substrate 1. Next, as shown in FIG.
A photoresist 3 is formed on the oxide film 2 and the oxide film 2 is patterned using the photoresist 3.

Next, as shown in FIG. 5, after removing the photoresist 3, the P-type silicon substrate 1 is etched using the oxide film 2 as a mask to form a hole 4. Hall 4
Is preferably 1 μm wide and 20 μm deep perpendicular to the substrate surface.

Thereafter, as shown in FIG.
Polycrystalline silicon 5 doped with a type impurity is grown on the entire surface to fill holes 4.

Next, heat treatment is performed to activate and diffuse the N-type impurity, and a high-concentration N-type impurity region 6 is formed in the P-type silicon substrate 1 along the wall surface of the hole 4 to form the P-type silicon. A PN junction is formed between the substrate 1 and the high concentration N-type impurity region 6.

After that, an interlayer insulating film 7 is formed on the polycrystalline silicon 5, and a first-layer wiring 8 is formed on the interlayer insulating film 7. After an interlayer insulating film 9 is formed on the entire surface of the interlayer insulating film 7 and the first layer wiring 8, the second layer wiring 1 is formed on the interlayer insulating film 9.
1 is formed, and the second-layer wiring 11 is connected to the first-layer wiring 8 via the connection holes 10 provided in the interlayer insulating film 9 to manufacture the semiconductor device shown in FIG.

If the silicon substrate is P-type, arsenic, phosphorus and antimony, which are N-type impurities, can be used as high-concentration impurities. If the silicon substrate is N-type, high-concentration impurities can be used. , Boron, indium, and gallium, which are P-type impurities, can be used.

In the semiconductor device incorporating the inductor element in this manner, the P-type silicon substrate 1 and the high-concentration N-type impurity region 6 form a PN junction, and the P-type silicon substrate 1 and the high-concentration N-type impurity When a reverse bias is applied to the region 6, the periphery of the high-concentration N-type impurity region 6 is depleted to form an electrically insulating region, and eddy current can be suppressed.

Next, a second embodiment of the present invention will be described.

FIG. 7 is a schematic sectional view showing a second embodiment of the semiconductor device of the present invention. As shown in FIG.
An oxide film 2 is formed on a mold silicon substrate 1,
Holes 4 are formed in the P-type silicon substrate 1 and the oxide film 2 deeply in the direction perpendicular to the P-type silicon substrate 1.

In the P-type silicon substrate 1, a high-concentration N-type impurity diffusion region 14 is formed along the wall surface of the hole 4. The P-type silicon substrate 1 and the high-concentration N-type impurity diffusion region 14 A PN junction is formed.

On the wall surface of the hole 4 and the oxide film 2, polycrystalline silicon 12 doped with a high concentration N-type impurity
Is formed.

On the polycrystalline silicon 12, a refractory metal 13
Is formed, and the inside of the hole 4 is filled with the refractory metal 13.
The high-melting-point metal 13 further embedded in the hole 4 is etched to form a potential supply line for supplying a potential to the high-melting-point metal 13 buried in the hole 4.

An interlayer insulating film 7 is formed on the refractory metal 13, and a first-layer wiring 8 is formed on the interlayer insulating film 7. An interlayer insulating film 9 is formed on the interlayer insulating film 7 and the first layer wiring 8. A second-layer wiring 11 constituting a coil is formed on the interlayer insulating film 9, and a first-layer wiring 8 is formed in a connection hole 10 provided in the interlayer insulating film 9.
Is connected to the second-layer wiring 11 via the.

The manufacturing process of the second embodiment is the same as that of the first embodiment from FIG. 3 to FIG. In the second embodiment, the hole 4 is formed by etching the P-type silicon substrate 1 using the oxide film 2 as a mask.
As shown in FIG. 8, a polycrystalline silicon 12 doped with a high concentration N-type impurity is formed on the inner surface of the formed hole 4 and the surface of the oxide film 2, and then a refractory metal 13 is formed on the entire surface. The hole 4 is filled with the high melting point metal 13. The subsequent manufacturing steps are the same as in the first embodiment.

As the high-concentration impurities, arsenic, phosphorus, and antimony, which are N-type impurities, can be used if the silicon substrate is P-type, and if the silicon substrate is N-type,
As in the first embodiment, boron, indium, and gallium, which are P-type impurities, can be used. Further, as the high melting point metal 13, tungsten, cobalt, molybdenum, tantalum, platinum, and titanium can be used.

In the above-described semiconductor device, the P-type silicon substrate 1 and the high-concentration N-type impurity diffusion region 14 form a PN junction, and the P-type silicon substrate 1 and the high-concentration N-type impurity When a reverse bias is applied to the diffusion region 14, a depletion layer region is formed around the high-concentration N-type impurity diffusion region 14, and eddy current can be suppressed.

FIG. 9 is a diagram showing the relationship between the frequency and the sharpness Q of the resonance. As shown in FIG. 9, the sharpness Q of the resonance
4 is about 10 in the conventional example, but is about 13 in this embodiment. That is, in this embodiment, the value of Q is improved because the depletion layer region is formed deeper than in the conventional example, and the eddy current can be more effectively suppressed when a high-frequency current flows through the coil. Can be.

FIG. 10 is a plan view showing a state where holes are formed in the silicon substrate. The example shows that the area ratio of holes in the depletion layer region is about 7%. In FIG.
A rectangular hole 4 with a side of 1 μm is about 1.5 μm to 4 μm
The holes 4 may be arranged in any manner as long as the inter-hole region is depleted. The shape of the opening of the hole is not limited to a rectangle, but may be any shape including a substantially circular shape or a substantially rectangular shape.

In the above-described embodiment, the holes are provided in the semiconductor substrate below the coil. However, instead of the holes, a plurality of trenches may be provided in the semiconductor substrate substantially in parallel with each other.

FIG. 11 is a diagram showing the relationship between the expansion of the depletion layer and the impurity concentration of the substrate when a reverse bias voltage of 3 V is applied to the PN junction. FIG. 12 shows holes occupying the depletion layer region at the resonance frequency. FIG. 4 is a diagram showing the area ratio dependency of the above. FIG. 12 shows that when the area ratio of holes is 20% or less, more preferably 15% or less, the effect of improving the resonance frequency is high.

[0041]

As described above, according to the present invention, the lateral diffusion of impurities can be reduced by diffusing impurities from the silicon layer in the holes provided in the semiconductor substrate. Even with an inductor (with a small inductance), the frequency at which the element operates as an inductor can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a first embodiment of an inductor element incorporated in a semiconductor device of the present invention.

FIG. 2 is an overhead view of a first-layer wiring and a second-layer wiring.

FIG. 3 is a schematic cross-sectional view illustrating a manufacturing process according to the first embodiment.

FIG. 4 is a schematic cross-sectional view illustrating a manufacturing process according to the first embodiment.

FIG. 5 is a schematic cross-sectional view illustrating a manufacturing process according to the first embodiment.

FIG. 6 is a schematic cross-sectional view illustrating a manufacturing process according to the first embodiment.

FIG. 7 is a schematic sectional view showing a second embodiment of the present invention.

FIG. 8 is a schematic cross-sectional view illustrating a manufacturing process according to a second embodiment.

FIG. 9 is a diagram showing a relationship between frequency and resonance sharpness Q;

FIG. 10 is a plan view showing a state where holes are formed in a silicon substrate.

FIG. 11 is a diagram showing the relationship between the expansion of a depletion layer and the impurity concentration when a reverse bias voltage of 3 V is applied to a PN junction.

FIG. 12 is a diagram showing the area ratio dependence of holes occupying the depletion layer region of the resonance frequency.

FIG. 13 is a schematic sectional view showing a conventional example of an inductor element.

FIG. 14 is a schematic sectional view showing a conventional example of an inductor element.

FIG. 15 is a plan view showing a state in which an N-type impurity diffusion region is formed in the conventional silicon substrate shown in FIG.

[Explanation of symbols]

 Reference Signs List 1 P-type substrate 2 Oxide film 3 Resist 4 Hole 5, 12 High-concentration N-type impurity-doped polycrystalline silicon 6, 15 High-concentration N-type impurity region 7 Interlayer insulating film 8 First-layer wiring 9 Interlayer insulating film 10 Connection hole 11 Second layer wiring 13 High melting point metal 14, 16 High concentration N-type impurity diffusion region 15 N-type impurity diffusion region 17 Connection hole 18 Metal wiring

Claims (15)

[Claims] An inductor element is formed on a semiconductor substrate,
A PN junction is formed between the semiconductor substrate and the semiconductor substrate by embedding polycrystalline silicon containing a high-concentration impurity of the opposite conductivity type in a hole provided in the semiconductor substrate below the inductor element. A semiconductor device, wherein a depletion layer can be expanded in a semiconductor substrate by applying a bias. 2. An inductor element is formed on a semiconductor substrate.
A PN junction is formed between the semiconductor substrate and the semiconductor substrate by forming a polycrystalline silicon film containing a high-concentration impurity of the opposite conductivity type inside the hole provided in the semiconductor substrate below the inductor element. A semiconductor device, characterized in that a depletion layer can be expanded in a semiconductor substrate by burying a high melting point metal in a hole through a polycrystalline silicon film and applying a reverse bias to the PN junction. 3. The semiconductor device according to claim 2, wherein any one of tungsten, cobalt, molybdenum, tantalum, platinum and titanium is used as said high melting point metal. 4. The semiconductor device according to claim 1, wherein a plurality of said holes are provided at predetermined intervals in said semiconductor substrate.
4. The semiconductor device according to any one of claims 3 to 3. 5. The semiconductor device according to claim 1, wherein said high concentration impurity is P
If the semiconductor substrate is an N-type silicon substrate, it is boron, indium or gallium, which is a P-type impurity if the semiconductor substrate is an N-type silicon substrate. Items 1-4
The semiconductor device according to any one of the above. 6. The semiconductor device according to claim 1, wherein an opening shape of said hole is substantially circular or substantially rectangular. 7. The semiconductor device according to claim 1, wherein said holes are provided in a direction perpendicular to the surface of the semiconductor substrate. 8. An inductor element is formed on a semiconductor substrate,
A semiconductor substrate and polycrystalline silicon containing high-concentration impurities of the opposite conductivity type are embedded in a trench provided in the semiconductor substrate below the inductor element to form a PN between the semiconductor substrate and the semiconductor substrate.
A semiconductor device characterized in that a depletion layer can be expanded in a semiconductor substrate by forming a junction and applying a reverse bias to a PN junction. 9. An inductor element is formed on a semiconductor substrate,
A polycrystalline silicon film containing a high-concentration impurity of the opposite conductivity type is formed in the trench provided in the semiconductor substrate below the inductor element, and a PN is formed between the semiconductor substrate and the semiconductor substrate.
A depletion layer can be expanded in the semiconductor substrate by forming a junction, burying a high melting point metal in the trench through the polycrystalline silicon film, and applying a reverse bias to the PN junction. Semiconductor device. 10. The semiconductor device according to claim 9, wherein one of tungsten, cobalt, molybdenum, tantalum, platinum, and titanium is used as said high melting point metal. 11. The semiconductor device according to claim 8, wherein a plurality of said trenches are provided substantially in parallel with each other in said semiconductor substrate. 12. The high-concentration impurity is an arsenic, phosphorus or antimony which is an N-type impurity if the semiconductor substrate is a P-type silicon substrate, and is a P-type impurity if the semiconductor substrate is an N-type silicon substrate. The boron, indium or gallium which is an impurity.
12. The semiconductor device according to any one of 11. 13. The semiconductor device according to claim 8, wherein said trench is provided in a direction perpendicular to a surface of said semiconductor substrate.
The semiconductor device according to any one of the above. 14. A method of manufacturing a semiconductor device having an inductor element incorporated therein, wherein a hole or a trench is formed in a semiconductor substrate below the inductor element, and polycrystalline silicon containing a high-concentration impurity of a conductivity type opposite to that of the semiconductor substrate is formed. Filling the holes or trenches by growing over the entire surface, performing heat treatment to activate the high-concentration impurities, and performing diffusion to form high-concentration impurity regions in the semiconductor substrate along the wall surfaces of the holes or trenches; A method for manufacturing a semiconductor device, comprising forming a PN junction between a substrate and a high-concentration impurity region. 15. A method for manufacturing a semiconductor device incorporating an inductor element, wherein a hole or a trench is formed in a semiconductor substrate below the inductor element, and a polycrystalline silicon film containing a high-concentration impurity of a conductivity type opposite to that of the semiconductor substrate. Is formed over the entire surface of the polycrystalline silicon film, a high melting point metal is formed on the polycrystalline silicon film, holes or trenches are filled with the high melting point metal, heat treatment is performed to activate the high concentration impurities, diffusion is performed, and holes or trenches are diffused. A method for manufacturing a semiconductor device, comprising: forming a high-concentration impurity diffusion region in a semiconductor substrate along a wall surface of a trench; and forming a PN junction at an interface between the semiconductor substrate and the high-concentration impurity diffusion region.