JP2000260893A - Semiconductor package and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor package for loading a semiconductor element with high density, and for reducing manufacturing cost. SOLUTION: A semiconductor element is loaded on a tape automated bonding(TAB) tape 10, and signal wiring is arranged mainly by wiring 12 of the TAB tape 10, and a wiring layer 22 of a core substrate 20 basically constitutes a power source layer and a ground layer. Thus, the constitution of a package can be simplified, and manufacturing costs can be reduced. Moreover, the TAB tape 10 and the core substrate 20 are manufactured separately, and then by having them electrically and mechanically connected, the flexibility of design is increased and the package size can be reduced. Moreover, the high density of the wiring 12 of the TAB tape 10 can be realized, and the connection with the semiconductor element having large number of input and output signals can be realized with multiple terminals and narrow pitches, and the package size can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly, to a semiconductor package having a semiconductor element mounted on a printed wiring board and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a semiconductor device, an IC chip or an LS
2. Description of the Related Art A semiconductor element such as an I-chip is mounted on a semiconductor element mounting portion provided in a semiconductor package and put to practical use. The resin mold package has a lower manufacturing cost than a ceramic semiconductor package.Especially, a semiconductor element is mounted on a printed wiring board without using a lead frame, and solder balls attached to the electrodes of the printed wiring board are used. BGA (Ball Gr connected to motherboard)
id Array) Package is drawing attention. The BGA package has more pins than the package using a lead frame such as a QFP (Quad Flat Package), so that the number of pins can be increased. Lead pitch is large,
Since the accuracy of the mounter or the like may be low, the production yield is improved. It has advantages such as relatively low manufacturing cost.

In a conventional BGA package, a semiconductor element is mounted on a printed wiring board, and bonding wires, wiring of the printed wiring board, through holes provided in the periphery of the printed wiring board, electrode portions below the printed wiring board, and the like. The electrode portion of the semiconductor element is electrically connected to a solder ball or the like via a via, and is sealed with a mold resin after mounting the semiconductor element.

[0004]

However, the above BGA
In the package, the printed wiring board uses a through-hole board structure that laminates the laminates and connects the conductive patterns with each other through plated through holes. For connection, through holes must be provided to penetrate all the laminated boards. Therefore, the wiring density cannot be increased, and as a result, there is a problem that it is difficult to reduce the size of the semiconductor device.

Accordingly, there is a printed wiring board having a structure called a build-up board. For example, as shown in FIG. 5, this build-up board is formed by alternately stacking a conductor pattern 2 and an insulating layer 3 made of a photosensitive resin on a core board 1 made of a laminated board or the like while forming vias 4. It is formed by (build-up method), and the interlayer connection of the conductor pattern 2 is performed by the via 4. Note that the through hole 5 is formed in the core substrate 1.

As described above, when a build-up board is used as a printed wiring board, the conductor pattern can be miniaturized, and the interlayer connection of the conductor pattern is made by vias formed for each insulating layer. The wiring density can be increased as compared with the case of the hole substrate, so that the semiconductor device can be easily reduced in size.

In a semiconductor device using a build-up substrate as a printed wiring board, a conductor pattern and an insulating layer are alternately stacked on both surfaces of a core substrate to achieve a high-density wiring. If the conductor pattern and the insulating layer were alternately stacked only on one surface of the core substrate, the printed wiring board would be warped, and it was difficult to actually manufacture the printed wiring board.

When conductor patterns and insulating layers are alternately stacked on both surfaces of a core substrate, a high-density wiring is required on the surface of the printed wiring board on the semiconductor element mounting side in order to increase the pitch of the input / output portions of the semiconductor elements. However, a low-density wiring layer such as a power supply layer and a ground layer is formed on the surface of the printed wiring board on the side opposite to the semiconductor element mounting side, and the surface of the printed wiring board on the side opposite to the semiconductor element mounting side and the anti-semiconductor element mounting side There was a large difference in the wiring density between the side surface and the side surface. Therefore, since the conductor pattern and the insulating layer are alternately stacked up to the surface on the side opposite to the semiconductor element mounting side of the printed wiring board where high-density wiring is not required, there is a problem that the manufacturing cost increases.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor package which enables mounting of high-density semiconductor elements and reduces manufacturing costs. It is another object of the present invention to provide a semiconductor package having a large degree of freedom in design and capable of reducing the package size, and a method of manufacturing the same.

[0010]

According to the semiconductor package of the present invention, the printed wiring board includes a semiconductor element mounting portion for mounting the semiconductor element, and a wiring electrically connected to the semiconductor element. The wiring board is provided on the side opposite to the semiconductor element mounting side of the printed wiring board,
It has a wiring layer serving as a power supply layer and / or a ground layer. For this reason, high-density wiring is formed on the printed wiring board,
Since a low-density wiring layer such as a power supply layer and a ground layer is formed on the wiring board, the package structure can be simplified by electrically and mechanically connecting the printed wiring board and the wiring board. Can be. Therefore, the manufacturing cost can be reduced.

Further, by separately manufacturing a printed wiring board and a wiring board and then electrically and mechanically connecting them, the degree of freedom of design is increased and the package size can be reduced.

According to the semiconductor package of the present invention, since the printed wiring board is a film-like substrate having an insulating film, for example, a TAB (Tape) having wiring formed on one or both surfaces of an insulating resin film. Auto
By using a mated bonding tape as a printed wiring board, the density of wiring can be increased. Therefore, it is possible to connect a semiconductor element having a large number of input / output signals with a large number of terminals and a narrow pitch, so that a high-density semiconductor element can be mounted.

As the insulating film, a plastic film such as polyimide, epoxy resin or polyamide, or a film obtained by impregnating and curing a plastic such as polyimide, epoxy resin or polyamide in a base material such as glass nonwoven fabric can be used. .

In order to form wiring on one or both sides of the insulating resin film, a method of etching a foil such as copper (Cu) or a copper alloy, a method of applying Cu plating to a predetermined location,
In addition, a method of using them in combination can be used.

The electrical connection between the wirings of the printed wiring board can be made by drilling the conductive via hole or irradiating a laser to remove unnecessary matter and then plating. Nickel (Ni), gold (A)
The electrode portion can be formed by plating such as u).

The electrical connection between the semiconductor element and the wiring layer of the printed wiring board can be made by wire bonding, flip chip, TAB or the like.

As the wiring substrate, a heat-resistant resin film or a thin laminated plate can be used as a base material. As the material of the film, for example, a resin such as polyimide, polyester, polyamide, or polyetheretherketone is preferable. As the resin for the laminate, epoxy, polyimide, bismaleimide triazine (B
T) and the like are preferable. The wiring can be formed by photolithography, etching, oxidation treatment, or the like of a thin layer of Cu or the like. The laminate can be laminated with epoxy or the like using glass or the like as a reinforcing plate. Electrical connection between the wirings of the laminated board can be made by drilling a conductive via hole or a through-hole plated with Cu or the like or by irradiating a laser to remove unnecessary matter and then plating. The electrode portion can be formed by plating the exposed portion of the wiring with Ni, Au, or the like.

According to the semiconductor package of the third aspect of the present invention, the connecting portion provided between the printed wiring board and the wiring board joins the printed wiring board and the wiring board and forms one of the wirings of the printed wiring board. Section and the wiring layer of the wiring board are electrically connected. Therefore, by using a conductive adhesive, a solder ball, or the like as the connection portion, the connection between the printed wiring board and the wiring board, and the electrical connection between a part of the wiring of the printed wiring board and the wiring layer of the wiring board. Can be performed simultaneously. Therefore, the manufacturing cost can be reduced with a simple configuration.

As the conductive adhesive, for example, an anisotropic conductive sheet formed by dispersing fine conductive particles in a thermosetting resin to form a sheet or an anisotropic conductive paste formed into a paste is used. be able to. Further, as the solder ball, for example, a material such as a lead-tin eutectic solder or a gold-tin eutectic solder can be used.

According to the method of manufacturing a semiconductor package of the present invention, a wiring electrically connected to the semiconductor element is formed on a printed wiring board having a semiconductor element mounting portion for mounting the semiconductor element. A wiring layer serving as a power supply layer and / or a ground layer is formed on a wiring board, and the printed wiring board on which the wiring is formed and the wiring board on which the wiring layer is formed are joined to form a part of the wiring of the printed wiring board and the wiring board Is electrically connected to the wiring layer.

Therefore, by separately manufacturing the printed wiring board and the wiring board and then electrically and mechanically connecting them, the degree of freedom of design is increased and the package size can be reduced.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a plurality of embodiments of the present invention will be described with reference to the drawings. (First Embodiment) A first embodiment in which the present invention is applied to a semiconductor package in which a semiconductor element having a flip-chip structure is mounted will be described with reference to FIGS.

As shown in FIG. 1, the semiconductor package 10
Numeral 0 is composed of a TAB tape 10 as a printed wiring board, a core substrate 20 as a wiring substrate, and a solder ball 30 as a connection.

The TAB tape 10 is formed by forming a wiring 12 made of, for example, Cu foil on a tape carrier 11 made of, for example, an insulating resin film such as a polyimide resin film, and electrically and mechanically connecting electrode pads of a semiconductor element (not shown). Has a solder bump 13 connected to the substrate. The upper surface of the TAB tape 10 on which the solder bumps 13 are provided constitutes a semiconductor element mounting portion. The wiring 12 is electrically connected to a signal wiring of a semiconductor element (not shown) via a solder bump 13. Therefore, the signal wiring and the like of the semiconductor element are routed by the wiring 12. The surface of the wiring 12 is coated with a polyimide coat 14 as a solder resist, and the exposed portion of the wiring 12 is plated with Ni, Au, or the like. The electrode portion 15 is formed on the lower surface of the TAB tape 10 and on the wiring 12 on the core substrate 20 side.

The core substrate 20 is made of, for example, an insulating layer 2 such as BT.
1 and a wiring layer 22 made of Cu or the like as a wiring layer is formed of a thin laminated plate in which an epoxy resin or the like is laminated, and has a through hole 23 plated with Cu or the like. The wiring layer 22 basically constitutes a power supply layer and a ground layer. The surface of the wiring layer 22 is coated with a polyimide coat 24 as a solder resist.
The plating of i, Au, etc. is performed. The electrode section 25 is formed on the wiring layer 22 on the TAB tape side on the upper surface of the core substrate 20.
Are formed on the lower surface of the core substrate 20 and the anti-T
An electrode portion 26 is formed on the wiring layer 22 on the AB tape side.

A solder ball 30 is provided between the TAB tape 10 and the core substrate 20. Solder ball 3
Numeral 0 electrically and mechanically connects a part of the electrode portion 15 of the TAB tape 10 and the electrode portion 25 of the core substrate 20. Therefore, the solder ball 30 is the TAB tape 1
0 and the core substrate 20 and the TAB tape 10
Of the wiring 12 and the wiring layer 22 of the core substrate 20 are electrically connected. The space between the TAB tape 10 and the core substrate 20 is filled with a resin 40 such as epoxy.

According to the above configuration, the signal wiring of the semiconductor element is basically routed by the wiring 12 of the TAB tape 10, but a part of the signal wiring is formed by the wiring layer 2 of the core substrate 20.
It is also possible to handle by 2. And the electrode part 25
PCB (Print Circuit) (not shown) as a motherboard with solder balls or conductive adhesive (not shown)
it Board).

Next, the semiconductor package 100 shown in FIG.
A method of manufacturing the device will be described. First, TAB tape 10
Will be described. (1) As shown in FIGS. 2A and 2B, a TAB tape film in which a Cu foil 112 is bonded to both sides of a tape carrier 111 made of an insulating resin film such as a polyimide resin film is subjected to a known photolithography process. Then, the substrate is put into an etching step to remove unnecessary Cu foil on the upper surface.

(2) As shown in FIG. 2C, a hole 11 is formed in the TAB tape film from which unnecessary Cu foil has been removed from the upper surface.
Then, the tape carrier 11 is manufactured by removing the resin residue.

(3) As shown in FIG. 2 (D), the TAB tape film on which the tape carrier 11 was made was electroless C
Conductive path 1 made of Cu by applying u plating and electrolytic Cu plating
14 is formed.

(4) As shown in FIG.
The TAB tape film on which 4 has been formed is again subjected to a photolithography step and an etching step, and a pattern is formed to form the wiring 12.

(5) As shown in FIGS. 2F and 2G, the surface of the wiring 12 is coated with a polyimide coat 14, the exposed portion of the wiring 12 is plated with Ni, Au, or the like, and the electrode portion is formed on the lower surface. 15 are formed.

(6) As shown in FIG.
The TAB tape 10 is manufactured by providing the solder bumps 13 in the holes on the upper surface of the TAB tape film on which is formed.

Next, a method for manufacturing the core substrate 20 will be described. (7) As shown in FIG. 3, an insulating layer 21 such as BT
A wiring layer 22 of Cu or the like is laminated with an epoxy resin or the like, and Cu
The wiring layer 22 is coated with a polyimide coat 24 on the surface of the wiring layer 22.
The exposed portions are plated with Ni, Au, or the like to form the electrode portions 25 and 26, and the core substrate 20 is manufactured.

Next, the T prepared in the above steps (1) to (6)
The AB tape 10 and the core substrate 20 manufactured in the above step (7) are joined using solder balls 30 as shown in FIG. At this time, the solder balls 30
A part of the electrode portion 15 of the tape 10 and the electrode portion 25 of the core substrate 20 are electrically and mechanically connected. Therefore, the solder ball 30 joins the TAB tape 10 and the core substrate 20, and electrically connects a part of the wiring 12 of the TAB tape 10 and the wiring layer 22 of the core substrate 20. Then, a resin 40 such as epoxy is filled between the TAB tape 10 and the core substrate 20.

In the semiconductor package 100 manufactured as described above, the semiconductor elements are mounted on the TAB tape 10, and the signal wiring is mainly routed by the wiring 12 of the TAB tape 10. Layer 22 is
Basically, it constitutes a power supply layer and a ground layer. Therefore, the configuration of the package is simplified, and thereby the manufacturing cost can be reduced.

Further, the TAB tape 10 and the core substrate 20
Are separately manufactured, and then both are electrically and mechanically connected, whereby the degree of freedom of design is expanded and the package size can be reduced.

Further, the wiring 12 of the TAB tape 10
Can be connected to a semiconductor element having a large number of input / output signals at a large number of terminals and at a narrow pitch, and the package size can be reduced. That is, it is possible to cope with an increase in the number of input / output signals of the semiconductor element and to reduce the package size. Furthermore, the signal wiring length can be shortened as the package size is reduced, and Cu or the like can be used as the wiring material in the TAB tape 10, so that the signal wiring has low resistance and low inductance. can do.
These are particularly effective for semiconductor devices whose operating frequency is increasing.

In the first embodiment of the present invention described above, high-density semiconductor elements can be mounted, manufacturing costs can be reduced, the degree of freedom in designing a semiconductor device can be increased, and the package size can be reduced. can do.

In the first embodiment, the TAB tape 10 and the core substrate 20 are joined by using the solder balls 30, but in the present invention, the TAB tape and the core substrate are joined by using a conductive adhesive. Is also good.

In the first embodiment, the insulating layer 21 such as BT is used.
And a wiring layer 22 made of Cu or the like, which is laminated with an epoxy resin or the like, is used for the core substrate 20. However, in the present invention, the core substrate is not limited to its material and configuration, and a resin film or the like Good.

(Second Embodiment) T of the first embodiment shown in FIG.
A second embodiment in which the method of manufacturing the AB tape 10 is changed will be described with reference to FIG. The substantially same parts as those in the first embodiment are denoted by the same reference numerals.

A method of manufacturing the TAB tape of the second embodiment will be described. (1) As shown in FIGS. 4A and 4B, a TAB tape film in which a Cu foil 112 is bonded to both sides of a tape carrier 111 made of an insulating resin film such as a polyimide resin film is subjected to a known photolithography process. And an etching process, and a pattern is formed.
To form

(2) As shown in FIG. 4C, a hole 163 is formed in the TAB tape film on which the wiring 62 has been formed, and the resin residue is removed to manufacture the tape carrier 61. (3) As shown in FIGS. 4D and 4E, the surface of the wiring 62 is coated with a polyimide coat 64, and the exposed portion of the wiring 62 is plated with Ni, Au or the like to form an electrode portion 65 on the lower surface. I do.

(4) As shown in FIG.
Hole 163 on the upper surface of the TAB tape film in which
The TAB tape 60 is manufactured by providing the solder bumps 63 on the substrate.

The TAB tape 60 manufactured in the steps (1) to (5) and the core substrate manufactured in the step (7) of the first embodiment are connected to each other by using a conductive adhesive or a solder ball. Joined,
A semiconductor package is manufactured.

Also in the second embodiment, the semiconductor element is TA
The signal wiring is mounted on the B tape 60 and the signal wiring is mainly routed by the wiring 62 of the TAB tape 60, and the wiring layer of the core substrate basically constitutes a power supply layer and a ground layer. Therefore, the configuration of the package is simplified, and thereby the manufacturing cost can be reduced.

Further, by separately manufacturing the TAB tape 60 and the core substrate and then electrically and mechanically connecting them, the degree of freedom of design is increased and the package size can be reduced.

Further, the wiring 62 of the TAB tape 60
Can be connected to a semiconductor element having a large number of input / output signals at a large number of terminals and at a narrow pitch, and the package size can be reduced.

In the embodiments of the present invention described above,
Although the present invention is applied to a semiconductor package having a TAB tape having a single-layer structure, it is needless to say that the present invention can be applied to a semiconductor package having a TAB tape having a multi-layer structure.

In the above embodiments, the present invention is applied to a semiconductor package in which a semiconductor element having a flip-chip structure is mounted. However, the bonding between the semiconductor element and the TAB tape is not limited to the flip chip, but may be performed by wire bonding. Or TAB.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a first embodiment in which the present invention is applied to a semiconductor package on which a semiconductor element having a flip-chip structure is mounted.

FIG. 2 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor package according to a first embodiment of the present invention and showing a TAB tape;

FIG. 3 is a schematic cross-sectional view for explaining a method of manufacturing a semiconductor package according to a first embodiment of the present invention and illustrating a core substrate.

FIG. 4 is a schematic cross-sectional view illustrating a method for manufacturing a semiconductor package according to a second embodiment of the present invention and showing a TAB tape;

FIG. 5 is a schematic sectional view showing a conventional build-up substrate.

DESCRIPTION OF SYMBOLS 10 TAB tape (printed wiring board) 11 Tape carrier 12 Wiring 13 Solder bump 14 Polyimide coat 15 Electrode part 20 Core substrate (Wiring board) 21 Insulation layer 22 Wiring layer 23 Through hole 24 Polyimide coat 25, 26 Electrode Part 30 Solder ball (connection part) 60 TAB tape (printed wiring board) 61 Tape carrier 62 Wiring 63 Solder bump 64 Polyimide coat 65 Electrode part

Claims (4)

[Claims] A semiconductor element mounting portion for mounting a semiconductor element, a printed wiring board having a wiring electrically connected to the semiconductor element, and a printed wiring board provided on an anti-semiconductor element mounting side of the printed wiring board;
A wiring board having a wiring layer serving as a power supply layer and / or a ground layer. 2. The semiconductor package according to claim 1, wherein said printed wiring board is a film-like substrate having an insulating film. 3. The printed wiring board is provided between the printed wiring board and the wiring board to join the printed wiring board and the wiring board, and a part of wiring of the printed wiring board and a wiring layer of the wiring board are formed. 3. The semiconductor package according to claim 1, further comprising: a connecting portion that electrically connects the semiconductor package. 4. A step of forming a wiring electrically connected to the semiconductor element on a printed wiring board having a semiconductor element mounting portion for mounting the semiconductor element, and a wiring layer serving as a power supply layer and / or a ground layer Forming the wiring on the wiring board, bonding the printed wiring board on which the wiring is formed, and the wiring board on which the wiring layer is formed, and electrically connecting a part of the wiring of the printed wiring board and the wiring layer of the wiring board. A method of manufacturing a semiconductor package, comprising the steps of: