JP2000260183A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to perform processing to an access to virtual space without causing a delay in the operation and an increase in the circuit area by selecting a word line corresponding to a row address where a memory cell exists, to an input of a row address where no memory cell exists. SOLUTION: A row address decoder 1 selects a word line for reading by a combination of the logical values 0 and 1 of a signal from the row address lines ADR0-ADR(n-1) at the time of read accessing. Since there are only m (2n-1<m<2n) pieces of word lines which should intrinsically be 2n pieces, a virtual space for (2n-m) pieces of lines is formed in the logical address space. The read access to the virtual space is allotted in a physical address by doubly mapping this virtual address space in a prescribed part in the physical address space. This allotment is executed by the address decoder 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DRAM and an SRA.
The present invention relates to a semiconductor memory device configured by arranging word lines and bit lines such as M in a grid pattern and arranging memory cells at respective intersections thereof. Related to the device.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor memory device, bit lines and word lines are arranged in a grid on a substrate, and data is stored in memory cells arranged at intersections thereof. In this semiconductor memory device, data is read from each memory cell by selecting a bit line and a word line, specifying a data address, and accessing data. Then, the data read from the memory cell is input to the next buffer or sense amplifier via the bit line.

The selection of such a word line is performed by a row address decoder based on a control signal input from the row address line. In this row address decoder, a word line is selected by a combination of logical values 0 and 1 of a signal from the row address line, so that a maximum of 2 ⁿ word lines can be controlled by ⁿ row address lines.

In a semiconductor memory device, 2 ⁿ word lines are not always provided for ⁿ row address lines, and the number of word lines may be smaller than 2 ^n. . In this case, depending on the application, an attempt may be made to access a data address (virtual address space) that does not physically exist through a word line that does not exist.

FIG. 4 is an explanatory view schematically showing a conventional semiconductor memory device. As shown in the figure, in a semiconductor memory device, n bit lines B0 to B (n-1) and m word lines
W0 to W (m-1) are wired in a grid pattern, and memory cells M (0,0) to M (m-1, n-1) are arranged at respective points.

In the semiconductor memory device shown in FIG. 1, bit lines B0 to B (n-1) are connected to buffers BUF0 to BUF (n-1) at the next stage. The m word lines W0 to W (m-1) are connected to a row address decoder 61, and the row address decoder 61 is connected to n row address lines ADR0 to ADR (n-1). Have been. Here, n and m is the number of bit lines and word lines are integers, m is a value greater than small and 2 ^n-1 than 2 ^n.

As shown in FIG. ^{1, since} there are only m (2 ⁿ⁻¹ <m <2 ⁿ ) word lines that should originally have 2 ⁿ word lines, a virtual address space that does not physically exist in the logical address space Are formed for 2 ⁿ -m lines.

Conventionally, in order to process such read access to the virtual address space, a dummy word line DW is connected to the row address decoder 61 in place of such 2 ⁿ -m word lines, and the dummy address line DW is connected. A circuit 60 configured by connecting transistors G0 to G (n-1) to memory cell positions on a word line DW is added.

According to the additional circuit 60, when a read access is made to an address where no memory cell exists, the transistors G0 to G (n-1) use the bit line B0.
To B (n-1) can be forcibly fixed to the VDD or GND level, and the next-stage buffers BUF0 to BUF generated when the bit lines B0 to B (n-1) enter a floating state.
(n-1) or the through current can be prevented from continuing to flow in the sense amplifier.

[0010]

However, in the conventional additional circuit 60 described above, the bit lines B0 to B (n-1) are connected to the VD
Transistors G0 to G for fixing to D or GND level
Connecting G (n-1) to the bit lines B0-B (n-1) increases the parasitic capacitance of the bit lines B0-B (n-1), causing a problem that the reading speed is reduced.

Further, since it is necessary to provide such an additional circuit 60 for all bit lines B0 to B (n-1), there is a problem that the area of the entire RAM circuit increases.

The present invention has been made in view of the above circumstances, and its purpose is to cause a delay in operation and an increase in circuit area in a semiconductor memory device having a word number other than a power of two. It is an object of the present invention to propose a semiconductor memory device capable of performing a process for accessing a virtual space without any need.

[0013]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention arranges a number of word lines other than a power of 2 and a plurality of bit lines in a grid pattern, and stores a memory at each intersection thereof. In a semiconductor memory device configured by arranging cells and selecting the word line by a combination of 0 and 1 which are logical values of a signal from a row address line, a memory for a row address input where no memory cell exists is provided. It has a row address decoder circuit for selecting a word line corresponding to the row address where the cell exists.

According to the present invention, a memory cell (virtual address space) that does not physically exist is double mapped to a specific portion in a physically existing memory cell (physical address space). Accordingly, read access to the virtual address space can be allocated to the physical address space, and the signal current input to the virtual address space can be processed without providing a special additional circuit.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (Structure of Semiconductor Memory Device) An embodiment of a semiconductor memory device according to the present invention will be described below. FIG. 1 is a schematic diagram showing an overall configuration of a semiconductor memory device 10 according to the present embodiment. In the semiconductor memory device 10 shown in the figure, n bit lines B0 to B (n-1)
m word lines W0 to W (m-1) are wired in a grid pattern, and memory cells M (0,0) to M (m-1, n-1) are arranged at respective points. ing.

The bit lines B0 to B (n-1) are connected to the next buffer BU.
Connected to F0 to BUF (n-1). In addition, word lines W0 to W
(m-1) is connected to the row address decoder 1, and this row address decoder 1 has n row address lines ADR0 to ADR0 to
ADR (n-1) is connected. Here, n and m is the number of bit lines and word lines are integers, m is a value greater than small and 2 ^n-1 than 2 ^n.

At the time of read access, the row address decoder 1 selects a word line to be read based on a combination of logical values 0 and 1 of signals from the row address lines ADR0 to ADR (n-1). In the present embodiment, as shown in the figure, since there are only m (2 ^n-1 <m <2 ⁿ ) word lines that should be originally 2 ⁿ , there are 2 ⁿ −m word lines in the logical address space. A virtual address space will be formed.

FIG. 2 is a diagram showing the relationship between the logical address space 2 and the physical address space 3 that actually exists. As shown in the figure, the logical address space 2 has a portion 2a corresponding to the portions 3a and 3b of the physical address space 3, respectively.
2b and a virtual address space 2c.

Here, the logical address space means a logical address space formed by 2 ⁿ word lines that can be selected by n row address lines ADR0 to ADR (n-1), The space refers to a physical address space formed by m word lines W0 to W (m-1) that actually exist.

Further, the virtual address space refers to a virtual address space formed by 2 ⁿ -m word lines that do not actually exist, and exists in the logical address space. In the present embodiment, this virtual address space is formed by m + 1 (≦ 2 ⁿ ) and subsequent word lines that do not exist.

In the semiconductor memory device 10 according to the present embodiment, the virtual address space 2c is doubly mapped to the portion 3b in the physical address space 3 so that the read access to the virtual address space 2c is performed in the physical address space. 3 is assigned. In this embodiment, the allocation to the physical address space 3 is as follows.
This is performed by the row address decoder 1.

(Configuration and Operation of Row Address Decoder 1)
FIGS. 3A and 3B show the internal structure and operation of the row address decoder 1. FIG. Here, for convenience, the description will be made assuming that there are two row address lines and three word lines.

As shown in FIG. 2A, in the row address decoder 1, the row address line ADR0 is connected to the inverting circuit 40 and AN.
The row address line ADR1 is similarly input to the inverting circuit 41 and the AND circuit 52. The output ADR0N of the inverting circuit 40 is input to the AND circuit 50, and the output ADR1N of the inverting circuit 41 is input to the AND circuits 50 and 51. In particular, only ADR1 is input to the AND circuit 52, and the AND circuit 52 outputs one value only when the input from ADR1 is one value.

The inverting circuits 40 and 41 invert the input signal value. When the 0 value is input, the signal is output as 1 value, and when the 1 value is input, the signal is output as 0 value. I do. Also, the AND circuits 50 to 52 calculate 1 value and 1
It outputs a 1 value only when a value is input, and outputs a 0 value otherwise.

According to such a row address decoder 1, as shown in FIG. 1B, one of the word lines W0 to W2 is selectively used according to the combination of signals input from the row address lines ADR0 and ADR1. One value can be output from any one of them.

For example, when ADR0 is 0 and ADR1 is 1, W0
Is input from ADR0N and 0 from ADR1N and outputs 0, and W1 is 0 from ADR0 and 0 from ADR1N.
And W2 receives 1 from ADR1 and outputs 1,
As a result, W2 is selected.

On the other hand, if ADR0 is 1 and ADR1 is also 1, the fourth word line, which should exist, should be selected. In this embodiment, however, the fourth word line is selected. W2 is selected. That is, when 1 is input from ADR0 and 1 is also input from ADR1, W0 outputs 0 from ADR0N and 0 from ADR1N and outputs 0, and W1 outputs 1 from ADR0 and AD
0 is input from R1N and 0 is output, and W2 is 1 from ADR1.
Is input and 1 is output. As a result, also in this case, W2 is selected.

According to the row address decoder 1 having such a configuration, read access to a non-existing word line can be allocated to an existing word line, and the virtual address space 2c is assigned to the portion 3b in the physical address space 3. Can be mapped doubly.

Although the description has been made here assuming that n = 2 and m = 3, by repeatedly providing the above configuration,
It can be applied in the range of ^n-1 <m < ²ⁿ .

[0030]

As described above, according to the semiconductor memory device of the present invention, in a semiconductor memory device having a number of words other than a power of two, operation delay and an increase in circuit area are not caused. It is possible to determine the signal level of the bit line, and it is possible to prevent a through current from continuing to flow in the buffer or the sense amplifier of the next stage.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a memory device 10 according to an embodiment of the present invention.

FIG. 2 is a schematic diagram showing an operation of the memory device 10 according to the embodiment of the present invention, and shows a relationship between a logical address space and a physical address space.

FIG. 3 is an explanatory diagram showing a row address decoder according to the embodiment of the present invention, wherein (a) is an internal structure thereof,
(B) shows an example of the mapping.

FIG. 4 is a block diagram illustrating a schematic configuration of a conventional memory device.

[Explanation of symbols]

1: row address decoder, 2: logical address space, 2c
... virtual address space 3 ... physical address space, B0 to B (n-1) ... bit lines, W0 to W
(m-1) ... word lines ADR0 to ADR (n-1) ... row address lines, M (0, 0) to M (m-1, n-1) ...
Memory cell

Claims (1)

[Claims] 1. A circuit comprising a number of word lines other than a power of 2 and a plurality of bit lines arranged in a grid pattern, and a memory cell arranged at each intersection thereof, and a logic of a signal from a row address line. In a semiconductor memory device for selecting the word line by a combination of values 0 and 1, a row address for selecting a word line corresponding to a row address where a memory cell is present in response to an input of a row address where no memory cell is present A semiconductor memory device comprising a decoder circuit.