JP2000259701A - Verification device, verifying method and computer- readable recording medium storing verification program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the labor and time required for verification. SOLUTION: The verification device is provided with a static circuit analyzing means 116 which extracts path information of a logic circuit by using the structure of the logic circuit for verification, and specification information to classify it into a long path which is possible to generate a delay problem and a short path in no connection with the delay problem, a form verification analyzing means 117 for extracting a group of cones of the logic circuit by using structure information of the logic circuit, a circuit dividing means 118 for classifying the group of the cones into a high act area through which the long path passes and a low act area through which the long path does not pass, a function verifying means 113 which executes function verification without considering the delay program by using a verifying pattern and structure information of the logic circuit and retains information concerning the verifying pattern passing through the high act area as activity information, a verifying pattern classifying means 120 classifying the verifying pattern into a low pattern passing through the high act area and an act pattern which does not pass through the high act area, and a delay verifying means 114 for delay verification of the high act area with the low pattern as an input.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a verification device, a verification method, and a computer-readable recording medium storing a verification program for performing design verification of a logic circuit by inputting a verification pattern to the logic circuit. The present invention relates to a technology that significantly reduces the labor and time required for verification.

[0002]

2. Description of the Related Art In general, it is determined whether or not a logic circuit such as a logic LSI satisfies an initial specification.
If the specification is not satisfied, a design verification process using a computer such as a computer system is performed to correct the defect.

In a conventional design verification process, as shown in FIG. 6, a delay circuit of an entire logic circuit 1 in which an analog circuit 3 and a circuit 4 manually manufactured are built together with a logic circuit 2 having design specifications. When performing the verification, the accuracy of the verification of the delay problem varies for each circuit block, which may cause a problem in the reliability of the entire delay verification. Verification is performed in duplicate to improve the reliability of design verification.

[0004]

As described above, in the conventional logic circuit design verification technology, both the function verification and the delay verification are performed for all the verification regions in the logic circuit.
As a result, the following technical problems to be solved have emerged.

That is, in the conventional logic circuit design verification technology, since delay analysis is performed even in a verification area where only function verification is sufficient, the time required to verify the entire logic circuit is enormous. It has become something. With the shortening of construction time and cost reduction being called for, these technical problems must be improved promptly.

Further, in the conventional design verification technology, function verification and delay verification are performed in a mixed manner. Therefore, the cause of a defect in a logic circuit is related to the function or to the delay. Can not be identified.

As described above, the conventional logic circuit design verification technology requires a great deal of labor and time for verification and cannot perform efficient design verification.

The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a verification device that reduces the labor and time required for verification and enables efficient design verification. is there.

It is another object of the present invention to provide a verification method that reduces the labor and time required for verification and enables efficient design verification.

A further object of the present invention is to provide a computer-readable recording medium storing a verification program which reduces the labor and time required for verification and enables efficient design verification.

[0011]

In order to solve the above-mentioned technical problems, the inventor classifies a logic circuit to be verified into a region related to a delay problem and a region not related to a delay problem, and delays only a region related to the delay problem. It has been proposed that by performing the verification process, the labor and time required for the verification can be reduced and efficient design verification can be performed.

Reflecting such an idea, the first aspect of the present invention
The feature of is that the path information of the logic circuit is extracted by using the structure and specification information of the logic circuit to be verified, and the path information is classified into a long path which may cause a delay problem and a short path which does not relate to the delay problem. Static circuit analysis means, formal verification analysis means for extracting a cone group of a logic circuit using structural information of the logic circuit, and a circuit for classifying the cone group into a high-act area where a long path passes and a low-act area where a long path does not pass Function verification means for performing function verification without considering a delay problem using the division means and the verification pattern and the structure information of the logic circuit, and storing information on the verification pattern passing through the high-act area as the activity information; and The verification pattern is used to define a low pattern that passes through the high-act area and an act pattern that does not pass through the high-act area. And the verification pattern classification similar means,
The present invention resides in a verification device including a delay verification unit that performs a delay verification of a high-act area by using a low pattern as an input.

As a result, the delay verification process is performed only on the region related to the delay problem, and it is not necessary to perform the duplication work of the function verification and the delay verification on all the circuit regions, so that the labor and time required for the verification are greatly reduced. Can be reduced.

A second feature of the present invention is a static circuit analysis step of extracting path information of a logic circuit by using the structure and specification information of a logic circuit to be verified, and the path information may cause a delay problem. Classification step for classifying into a long path having a characteristic and a short path which does not relate to the delay problem, a formal verification analysis step for extracting a cone group of a logic circuit using structural information of the logic circuit, and a long path passing through the cone group Performs functional verification without considering delay problems using circuit division steps and verification patterns and logic circuit structure information that classifies into high-act areas and low-act areas where long paths do not pass, and activates information on verification patterns that pass through the high-act areas. A function verification step of storing the verification pattern as information, and a verification pattern using the activity information. A verification pattern classification step of classifying into a act pattern which does not pass through the low pattern and Haiakuto region passes, lies in the verification method comprising the delay verification step of performing a delay verification of Haiakuto region low pattern as input.

As a result, it is not necessary to perform the delay verification process only on the region related to the delay problem and perform the duplication work of the function verification and the delay verification on all the circuit regions, so that the labor and time required for the verification are greatly reduced. Can be reduced.

Furthermore, a third feature of the present invention is that path information of a logic circuit is extracted using the structure and specification information of a logic circuit to be verified, and the path information is extracted from a long path and a delay which may cause a delay problem. Static circuit analysis processing that classifies the path as a short path regardless of the problem, formal verification analysis processing that extracts the cone group of the logic circuit using the structural information of the logic circuit, and the high-act area and long path where the long path passes through the cone group Performs circuit division processing to classify the data into low-act areas that do not pass, performs function verification without considering delay issues using verification patterns and logic circuit structure information, and stores information on verification patterns that pass through high-act areas as activity information Function verification processing, and a low pattern and a high-act area passing a high-act area through a verification pattern using activity information. A verification program that includes a verification pattern classification process of classifying an act pattern that does not pass through, and a delay verification process of performing a delay verification of a high-act region by using a low pattern as an input, and causing a computer to execute these processes. It is to be a computer-readable recording medium in which it is stored.

As a result, the delay verification process is performed only on the region related to the delay problem, and it is not necessary to perform the duplication work of the function verification and the delay verification on all the circuit regions, so that the labor and time required for the verification are greatly reduced. Can be reduced.

Here, as a computer-readable recording medium, it is desirable to use a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, a magnetic tape, a digital video disk, or the like.

Verification means switching means (processing) for automatically switching the verification means between the function verification means and the delay verification means based on whether or not the verification area is a high-act area.
Is preferably provided.

Further, the verification pattern is defined by the specification of the logic circuit.
It is preferable that a verification pattern dividing unit for dividing the data into a plurality of verification patterns based on the control information and the tester analysis information be provided.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, referring to FIGS. 3 and 4, "short path", "long path",
The terms “cone”, “high-act area”, “low-act area”, “activity information”, “low pattern”, and “act pattern” will be briefly described.

(Short Pass / Long Pass) A verification device, a verification method, and a computer-readable recording medium storing a verification program according to the embodiment of the present invention are subjected to static circuit analysis, as shown in FIG. Then, based on a margin (designated margin) value of an allowable delay time designated by a user, the path is classified into those that may cause a delay problem and those that do not. In this specification, a path that may cause a delay problem is defined as a “long path” and a path that does not involve delay is defined as a “short path”, and the paths are classified.

(Cone, High-act Area, Low-act Area) In a computer-readable recording medium storing a verification device, a verification method, and a verification program according to the embodiment of the present invention, FIG. “corn” group 151a as shown in a),
b, c, d, e, f, and g are extracted, and the extracted “cone” group is further classified into a “high-act area” where a long path passes and a “low-act area” where a long path does not pass. The “cone” referred to in this specification has the same definition as the “cone” obtained by general formal verification analysis, and as shown in FIG.
52a, b, c, d, e, f, and the conical area defined for each, describe the delay and input information related to each register. Therefore, the information on the delay and the input signal in the entire area of the logic circuit 150 can be described by the information on the “cone”. In this specification, a “cone” that a long path that may cause a delay passes is defined as a “high-act area”, and a “cone” that a long path does not pass is defined as a “low-act area”.

(Activity Information, Low Pattern, Act Pattern) In a computer-readable recording medium storing a verification device, a verification method, and a verification program according to an embodiment of the present invention, information on a verification pattern passing through a high-act area. Is stored as “activity information”, and the verification patterns are classified into “low pattern” passing through the high-act area and “act pattern” not passing through the high-act area using the “activity information” (FIG. 4B).
reference).

A verification device, a verification method, and a computer-readable recording medium storing a verification program according to an embodiment of the present invention will be described below with reference to FIGS.

First, the configuration of the verification device according to the embodiment of the present invention will be described with reference to FIG.

A verification system 1 according to an embodiment of the present invention
Reference numeral 00 denotes a verification device 110 for performing function verification and delay verification of a logic circuit, an input device 130 for inputting various commands and data related to the verification device 110, and an output from the verification device 110 such as a verification result and an error display. Output device 140
Further, the verification device 110 extracts path information using the structure and specification information of the logic circuit to be verified,
A static circuit analyzing means 116 for classifying path information into a long path which may cause a delay problem and a short path which does not relate to the delay problem, and a format for extracting a cone group of the logic circuit using the structure information of the logic circuit Verification analysis means 117
And a circuit dividing means 118 for classifying a cone group into a high-act area where a long path passes and a low-act area where a long path does not pass, and performs function verification without considering a delay problem using a verification pattern and structure information of a logic circuit,
Function verification means 113 for storing information on a verification pattern passing through a high-act area as activity information, and verification pattern division means for dividing the verification pattern into a plurality of verification patterns based on logic circuit specification / control information and tester analysis information 119, a verification pattern classifying means 120 for classifying a verification pattern into a low pattern passing through a high-act area and an act pattern not passing through a high-act area using the activity information, and various data necessary for verification of the activity information and the like. The storage means 121 for storing, the delay verification means 114 for performing the delay verification using the low pattern as an input, and the function verification means 113 and the delay verification means 114 for automatically verifying the verification means based on whether or not the verification area is a high-act area. Verification means switching section 115 for switching to function verification means 1
A function library (storage means) 111 for storing various data used by the device 13 and a timing library (storage means) 11 for storing various data used by the delay verification means 114
2 is provided.

Next, a verification method according to the embodiment of the present invention will be described with reference to FIG.

When verifying a logic circuit using the verification method of the present invention, (1) (input circuit information / logic synthesis constraint, step S10
1) First, the structure and specification information (logic synthesis constraint) of the logic circuit to be verified are input to the static circuit analysis means 116.

(2) (Static circuit analysis, step S10)
2) Next, a static circuit analysis is performed to obtain the path distribution information shown in FIG.

(3) (Path Information Classification, Step S10)
3) Subsequently, the path distribution information is classified into a long path which may cause a delay problem and a short path which does not relate to the delay problem.

(4) (Format verification analysis, step S10
4) Next, formal verification analysis is performed using the structural information of the logic circuit to be verified, and a cone group of the logic circuit is extracted.

(5) (Circuit division processing, step S10)
5) Next, the cone group is classified into a high-act area where the long path passes and a low-act area where the long path does not pass.

(6) (Function Verification, Step S106) Subsequently, function verification without considering the delay problem is performed by using the verification pattern and the structure information of the logic circuit, and the information on the verification pattern passing through the high-act area is converted into the activity level. Save as information.

(7) (Verification Pattern Division Processing, Step S107) Next, the verification pattern input using the DRC (Design Rule Check) result information such as the specification control information of the logic circuit and the tester analysis data is further divided into a plurality of verification patterns. Divide into verification patterns.

(8) (Verification Pattern Classification Processing, Step S108) Subsequently, a plurality of verification patterns are high-acted by using the activity information and taking into account the grouping of asynchronous patterns such as time-division / reset signals of very large patterns. It is classified into a low pattern that passes through the area and an act pattern that does not pass through the high-act area.

(9) (Verification area discrimination, step S10)
9) Next, it is determined whether the logic circuit area to be verified is a high-act area.

The verification area goes to the high-act area → (delay verification, step S110). The verification area goes to the low-act area → verification is completed because it is not necessary to perform delay analysis. (10) (delay verification, step S110) Finally, the low pattern is verified. Input as a pattern, perform delay verification of the high-act area, and perform sign-off.

Here, (verification pattern division processing, step S107) may not be necessarily performed. That is,
This verification pattern division processing is a step that enables more detailed verification by increasing the number of verification patterns. Therefore, when it is desired to perform higher-speed verification even if the verification accuracy is somewhat low, this step can be omitted. The time required for verification can be reduced.

The verification system 100 according to the embodiment of the present invention has, for example, an appearance as shown in FIG.
That is, the verification device 110 according to the embodiment of the present invention is configured by incorporating each element of the verification device in the computer system 160. Computer system 16
0 has a floppy disk drive 161 and an optical disk drive 163. Then, the floppy disk 162 is inserted into the floppy disk drive 161, and the optical disk 164 is inserted into the optical disk drive 163, and a predetermined read operation is performed. 160. In addition, by connecting an appropriate drive device to the computer system 160, the verification program can be installed using, for example, the ROM 165 serving as a memory device or the cartridge 166 serving as a magnetic tape device. It is.

The verification device 110 according to the embodiment of the present invention may be programmed and stored in a computer-readable recording medium. When the verification program is executed, the recording medium is read into a computer system, the verification program is stored in a recording unit such as a memory in the computer system, and the processing in the verification program is executed. The verification device and the method according to the embodiment can be realized on a computer system. Here, the recording medium is, for example,
It refers to a computer-readable medium on which a program can be recorded, such as a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, a magnetic tape, and a digital video disk.

Thus, it should be appreciated that the present invention encompasses various embodiments not described herein. Therefore, the present invention must be limited only by the matters specifying the invention according to the claims that are reasonable from this disclosure.

[0043]

As described above, according to the verification apparatus of the present invention, the modules used for the logic verification and the delay verification are independently provided, the function verification process is performed, and the logic circuit is connected to the area related to the delay problem. Since the delay verification process is performed only on the area related to the delay problem after being classified into the area where no delay verification is required, both the function verification and the delay verification are not performed until the area where the delay verification is not necessary. It can be reduced to In addition, since the function verification means and the delay verification means can be automatically switched based on whether or not the verification area is a high-act area, the verification means is switched from the first verification to perform more efficient verification. It can be carried out.

Further, according to the verification method of the present invention, the function verification processing is performed, the logic circuit is classified into a region related to the delay problem and a region not related to the delay problem, and the delay verification process is performed only on the region related to the delay problem. Since both the function verification and the delay verification are not performed in an area where the verification is not necessary, the labor and time required for the verification can be greatly reduced.

Further, according to the computer-readable recording medium storing the verification program of the present invention, the function verification process is performed, and the logic circuit is classified into a region related to the delay problem and a region not related to the delay problem. Since the delay verification process is performed only on the region, both the function verification process and the delay verification process are not performed up to the region where the delay verification is not necessary, and the labor and time required for the verification can be greatly reduced. In addition, since the function verification processing and the delay verification processing can be automatically switched based on whether the verification area is the high-act area, the verification processing is switched from the first verification, and more efficient verification is performed. It can be carried out.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a verification system according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating a verification method according to the embodiment of the present invention.

FIG. 3 is a diagram for explaining a path classification method according to the embodiment of the present invention.

FIG. 4 is a diagram for explaining a concept used in the present invention.

FIG. 5 is a schematic diagram showing an overview of a verification system according to an embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a typical logic circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Whole logic circuit 2 Logic circuit 3 Analog circuit 4 Manual circuit 100 Verification system 110 Verification device 111 Function library 112 Timing library 113 Function verification means 114 Delay verification means 115 Verification means switching unit 116 Static circuit analysis means 117 Format verification analysis means 118 circuit dividing means 119 verification pattern dividing means 120 verification pattern classification means 121 storage means 130 input device 140 output device 150 logic circuit 151a, b, c, d, e, f, g, h cones 152a, b, c, d, e, f, g register 160 computer system 161 floppy disk drive 162 floppy disk 163 optical disk drive 164 optical disk 165 ROM 166 cartridge

Claims (10)

[Claims] 1. A module used for logic verification and delay verification are provided independently, and a logic circuit to be verified is classified into a region related to a delay problem and a region not related to the delay problem, and the delay verification is performed only in a region related to the delay problem. A verification method characterized by the following. 2. The verification method according to claim 1, wherein the logic verification is performed regardless of the existence of the delay problem, and the delay verification is performed after the logic verification. 3. The path information of a logic circuit to be verified is extracted using the structure and specification information of the logic circuit to be verified, and the path information is converted into a long path which may cause a delay problem and a short path which does not relate to the delay problem. Static circuit analysis means for classifying the logic circuit into: a formal verification analysis means for extracting a cone group of the logic circuit using structural information of the logic circuit; a high-act area through which the long path passes through the cone group; and A circuit dividing means for classifying the circuit into a low-act area through which a long path does not pass; and using a verification pattern and structural information of the logic circuit,
A function verification unit that performs function verification without considering a delay problem and stores information regarding a verification pattern passing through the high-act area as activity information; and using the activity information, passes the verification pattern through the high-act area. A verification pattern classifying means for classifying a low pattern to be performed and an act pattern which does not pass through the high-act area; and a delay verification means for performing delay verification of the high-act area by inputting the low pattern. 4. A static circuit analysis step of extracting path information of a logic circuit using a structure and specification information of the logic circuit to be verified, and converting the path information into a long path that may cause a delay problem. A path classification step of classifying the path into a short path not related to a delay problem; a formal verification analysis step of extracting a cone group of the logic circuit by using the structure information of the logic circuit; and the long path passing through the cone group. Using a verification pattern and the structure information of the logic circuit to classify the high-act area and the low-act area through which the long path does not pass.
A function verification step of performing function verification without considering a delay problem and storing information on a verification pattern passing through the high-act area as activity information; and passing the verification pattern through the high-act area using the activity information. A verification pattern classification step of classifying into a low pattern to be performed and an act pattern that does not pass through the high-act area, and a delay verification step of performing delay verification of the high-act area by using the low pattern as an input. 5. The path information of a logic circuit to be verified is extracted using the structure and specification information of the logic circuit to be verified, and the path information is converted into a long path which may cause a delay problem and a short path which does not relate to the delay problem. A static circuit analysis process that classifies the logic circuit into: a formal verification analysis process for extracting a cone group of the logic circuit using the structure information of the logic circuit; and a high-act area through which the long path passes through the cone group. Using a circuit partitioning process for classifying into a low-act area that does not pass through a long path, and using a verification pattern and structural information of the logic circuit,
A function verification process that does not consider a delay problem and stores information on a verification pattern passing through the high-act area as activity information, and passing the verification pattern through the high-act area using the activity information A verification pattern classification process of classifying a low pattern to be performed and an act pattern that does not pass through the high-act region, and a delay verification process of performing delay verification of the high-act region by using the low pattern as an input, and execute these processes on a computer. A computer-readable recording medium storing a verification program. 6. A verification means switching unit for automatically switching a verification means between the function verification means and the delay verification means based on whether a verification area is a high-act area. 3. The verification device according to 3. 7. A verification unit switching process for automatically switching a verification unit between the function verification unit and the delay verification unit based on whether or not the verification region is a high-act region, and executes this process on a computer. A computer-readable recording medium storing the verification program according to claim 5. 8. The apparatus according to claim 3, further comprising a verification pattern dividing unit that divides the verification pattern into a plurality of verification patterns based on specification / control information of the logic circuit and tester analysis information. Verification device. 9. The verification method according to claim 4, further comprising a verification pattern dividing step of dividing the verification pattern into a plurality of verification patterns based on specification / control information and tester analysis information of the logic circuit. . 10. A process for dividing a verification pattern into a plurality of verification patterns based on specification / control information and tester analysis information of the logic circuit, and causing a computer to execute this process. A computer-readable recording medium storing the verification program according to claim 5.