JP2000258509A - Method for testing semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make currents for measuring on-resistance values to be made to flow to individual switch elements to be tested even when no exclusive external terminal is provided for leading out an internal common node to the outside of a semiconductor integrated circuit. SOLUTION: In a semiconductor integrated circuit A, a switch element 7 for supplying current which is only turned on in a test mode is connected in advance to an internal power source 8. In the test mode, currents are made to flow to switching elements 1, 2, and 3 to be tested in the directions toward external terminal 11, 12, and 13 from an internal common node 4 by turning on the switch element 7 and, at the same time, individually turning on the switch elements 1, 2, and 3 or simultaneously turning on some of the elements 11, 12, and 13 and the value of the current flowing out from each external terminal in each case is measured. The on-resistance value R1, R2, and R3 of each switch element 11, 12, and 13 is found by solving simultaneous equations which can be held by the measurement.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit test method for measuring the on-resistance value of a test switch element connected to an internal common node in a semiconductor integrated circuit. The present invention relates to a technique for enabling a test for measuring an on-resistance value to be performed without any trouble without providing a dedicated external terminal for drawing out to the outside of a circuit.

[0002]

2. Description of the Related Art FIG. 4 shows a test method for a conventional semiconductor integrated circuit. 4, B is a semiconductor integrated circuit, 31, 32, and 33 are switch elements to be tested.
34 is an internal common node of the test switch elements 31, 32, 33, 35 is an internal circuit, and 36 is a control signal S31, S3 for on / off control of the test switch elements.
2, a control signal output circuit for outputting S33, 41, 42,
Reference numeral 43 denotes an external terminal connected to each of the test target switch elements 31, 32, 33 on the opposite side of the internal common node 34;
Reference numeral 4 denotes a dedicated external terminal connected to the internal common node 34 for extracting the internal common node 34 to the outside of the semiconductor integrated circuit B; 51, a DC ammeter; and 52, an external power supply for testing.

The test target switch elements 31, 32, 33
Are connected between the external terminals 41, 42, 43 and the internal common node 34, respectively, and are turned on / off by individual control signals S31, S32, S33 output from the control signal output circuit 36. The internal common node 34 is an internal circuit 35
It is connected to the. In the test mode, control is performed such that any one of the switch elements 31, 32, and 33 to be tested is turned on. The internal common node 34 connected to the internal circuit 35 is connected to a dedicated external terminal 44. The external terminals 41, 42, and 43 are commonly connected outside the semiconductor integrated circuit B, and a series circuit of a DC ammeter 51 and a DC power supply 52 is inserted between the common connection point and a dedicated external terminal 44. ing.

As described above, the dedicated external terminal 44 is pulled out from the internal common node 34, and the external terminals 41, 42, 43
And a control signal S3
One of the test target switch elements 31, 32, and 33 is turned on by any one of S1, S32, and S33, and the current flowing therethrough is measured by the DC ammeter 51, so that the test target switch elements 31, 32, and 33 are turned on. Specify the resistance value.

[0005]

The above-mentioned prior art has the following problems. As a means for applying a DC power supply necessary to supply a current to the switch element to be tested, both the high potential side (power side) terminal and the low potential side (ground side) terminal are external to the semiconductor integrated circuit B. Is required. That is, the internal common node 34 of the plurality of test target switch elements 31, 32, 33 is drawn out, and an external terminal 44 dedicated to the test is provided at the end thereof. However, when the number of external terminals is limited as a semiconductor integrated circuit, there is a problem that the assignment becomes difficult.

The present invention has been made in order to solve the above-mentioned problem, and has a dedicated external terminal for extracting an internal common node to the outside for measuring an on-resistance value of a switch element to be tested. The purpose is to be able to perform the measurement without it.

[0007]

SUMMARY OF THE INVENTION A method for testing a semiconductor integrated circuit according to the present invention comprises an internal power supply or an internal power supply for flowing a current from an internal common node to an external terminal or vice versa. A test switch element is provided between the ground and the internal common node. Alternatively, a closed loop is secured between the switch element to be tested and an external terminal connected thereto with another switch element to be tested. Then, the on-resistance value of each test target switch element is specified by the solution of the simultaneous equations obtained by measuring the value of the current flowing through each external terminal. According to such a method, a current for measuring the on-resistance value of each test target switch element can be passed without providing a dedicated external terminal for drawing out the internal common node to the outside of the semiconductor integrated circuit. Thus, even when the number of external terminals is limited as a semiconductor integrated circuit, a test for measuring the on-resistance value of the switch element to be tested can be performed without hindrance.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The method for testing a semiconductor integrated circuit according to claim 1 of the present invention requires the following. It is assumed that the method is a semiconductor integrated circuit test method for measuring the on-resistance values of a plurality of test target switch elements each having one end connected to an internal common node and the other end individually connected to an external terminal. Inside the semiconductor integrated circuit, a current supply switch element that is turned on only in the test mode is connected to an internal power supply in advance. In the test mode, the switch elements for current supply are turned on, and a plurality of switch elements to be tested are turned on individually and some at the same time to supply a current to the switch elements to be tested in a direction from the internal common node to the external terminal. And measure the value of the current flowing out of each external terminal in each case. The on-resistance value of each test target switch element is determined based on solving simultaneous equations that can be established by this measurement. According to this method, even if a dedicated external terminal for drawing out the internal common node to the outside of the semiconductor integrated circuit is not provided, the on-resistance of each test target switch element from the internal power supply via the current supply switch element is provided. A current for measuring the value can be passed.

According to a second aspect of the present invention, there is provided a method for testing a semiconductor integrated circuit, based on the same premise, that a grounding switch element which is turned on only in a test mode is previously connected to an internal ground inside the semiconductor integrated circuit. Keep it. In the test mode, the grounding switch elements are turned on, and a plurality of switch elements to be tested are turned on individually and several simultaneously, so that a current flows through the switch elements to be tested in a direction from the external terminal toward the internal common node. In each case, the value of the current flowing into each external terminal is measured. The on-resistance value of each test target switch element is determined based on solving simultaneous equations that can be established by this measurement. According to this method, the current from the external power supply is released to the internal ground via the grounding switch element without providing a dedicated external terminal for extracting the internal common node to the outside of the semiconductor integrated circuit. A current for measuring the on-resistance value can be passed through the switch element to be tested.

According to a third aspect of the present invention, there is provided a method for testing a semiconductor integrated circuit according to the third aspect of the present invention, wherein a positive electrode of an external power supply for testing is connected to one of the external terminals and the other one of the external terminals is connected. Connect a negative electrode to the crab. That is, the switch element to be tested and the switch element to be tested are connected in a closed loop. A current flows in a direction from the external terminal to the internal common node in a test target switch element in which the test target switch element connected to those external terminals is turned on, and flows in a direction from the internal common node to the external terminal in another test target switch element. The current flows in the direction, and the value of the current flowing at that time is measured.
The on-resistance value of each test target switch element is obtained based on solving simultaneous equations that can be established by this measurement. According to this method, the current from the positive electrode of the external power supply is applied to each switch element to be tested so that the current from the positive electrode of the external power supply goes to the negative electrode without providing a dedicated external terminal for extracting the internal common node to the outside of the semiconductor integrated circuit. On the other hand, a current for measuring the on-resistance value can flow.

Hereinafter, specific embodiments of a method for testing a semiconductor integrated circuit according to the present invention will be described in detail with reference to the drawings.

[Embodiment 1] Embodiment 1 is a first embodiment.
In response to the above, a DC power supply for applying a bias to the test target switch element is obtained inside the semiconductor integrated circuit,
The ground is obtained outside the semiconductor integrated circuit.
FIG. 1 is a diagram illustrating a test method of the semiconductor integrated circuit A according to the first embodiment. Here, as indicated by reference numerals 1, 2, and 3, there are three test target switch elements, and one end of each of the test target switch elements 1, 2, and 3 is connected to the internal circuit 5 via the internal common node 4. It is assumed that The first test target switch element 1 is turned on / off by a control signal S1 from a control signal output circuit 6, and the second test target switch element 2 is also controlled by a control signal S2 and a third switch element. The on / off control of the test target switch element 3 is similarly performed by the control signal S3. The other ends of the test target switch elements 1, 2, 3 are connected to external terminals 11, 12, 1, 1, respectively.
3 is connected. As a measure for measuring the on-resistance value of each of the test target switch elements 1, 2, 3 in such a semiconductor integrated circuit A, the semiconductor integrated circuit A
Is provided in advance with a current supply switch element 7,
One end of the current supply switch element 7 is connected to the internal power supply 8, and the other end is connected to the internal common node 4.

In a test for measuring the on-resistance values of the test target switch elements 1, 2, 3, the external terminals 11, 12,
DC ammeters 21, 22, 23 are connected between each of the external grounds 13 and the external ground 14. The DC voltage from the internal power supply 8 is Vdd. Although the on-resistance value of each of the test target switch elements 1, 2, 3 is unknown, it is represented by the symbol R
To be represented by _1, R _2, R _3. The on-resistance of the current supply switch element 7 is R ₀ .

First, the current supply switch element 7 is turned on by the control signal S4. Next, the control signal output circuit 6 outputs the control signal S1 to turn on the first test target switch element 1. As a result, the current supply switch element 7, the internal common node 4, the first test target switch element 1, the external terminal 11, the DC ammeter 2
1. A current flows through the path of the external ground 14. When the current value measured by the DC ammeter 21 this time and i _1,

[0015]

(Equation 1)

The following holds. Next, the output of the control signal S1 is stopped, and instead, the control signal S2 is output from the control signal output circuit 6.
Is output to turn on the second test target switch element 2, and the current flowing through the current supply switch element 7 and the second test target switch element 2 is measured by the DC ammeter 22 connected to the external terminal 12. Assuming that the current value measured by the DC ammeter 22 is i ₂ ,

[0017]

(Equation 2)

The following holds. Further, the output of the control signal S2 is stopped, and the control signal S
3 is output to turn on the third test target switch element 3, and the current flowing through the current supply switch element 7 and the third test target switch element 3 is measured by the DC ammeter 23 connected to the external terminal 13. . If the current value measured by the DC ammeter 23 is i ₃ ,

[0019]

(Equation 3)

The following holds. The unknowns are R ₁ , R ₂ , R ₃ ,
Since there are four of R ₀ , another equation is needed. Therefore, the control signals S1, S
2, S3 to output three test target switch elements 1,
2 and 3 are both turned on, and the DC ammeter 21,
The current values measured at 22 and 23 are respectively ia ₁ , ia ₂ and i
and a _3, a sum of these current values and ia _0. What is important here is not a separate current value, which is the total current value ia _0. The three switch elements 1, 2 and 3 to be tested are connected in parallel, and the combined resistance value is Rz.

[0021]

(Equation 4)

[0022]

(Equation 5)

[0023]

(Equation 6)

By solving the simultaneous equations (1), (2), (3), and (6), the on-resistance value R ₀ of the current supply switch element 7 is determined, and the three test target switch elements are further determined. On-resistance values R ₁ , R ₂ , R _{3 of 1} , ₂ , ₃
To identify.

As described above, according to the semiconductor integrated circuit test method of the first embodiment, the external terminals 11, 12, and 13 connected to the test target switch elements 1, 2, and 3 are connected to the external ground 14. Since the current supply switch element 7 for connecting the internal common node 4 of the switch elements 1, 2 and 3 to be tested to the internal power supply 8 is provided inside the semiconductor integrated circuit A, A current for measuring the on-resistance value can flow to the switch elements 1, 2 and 3 to be tested, and the internal common node 4
Switch elements 1, 2, 3, and 3 without providing a dedicated external terminal for extracting
The respective on-resistance values R ₁ , R ₂ and R ₃ can be measured. In other words, even when the number of external terminals is limited as a semiconductor integrated circuit, a test for measuring the on-resistance value of the switch element to be tested can be performed without any hindrance.

When the test is completed, the current supply switch element 7 is turned off. That is, it is necessary to remove the influence of the internal power supply 8 on the internal circuit 5. In normal use, if there is no problem if the internal power supply 8 is always connected to the internal circuit 5, there is no need to interpose the current supply switch element 7 in the first place. However, since there is actually a problem, the current supply switch element 7 is inserted, and the current supply switch element 7 is turned on only in the test mode, and is turned off in the normal use state.

Although three DC ammeters 21, 22, and 23 are used in the above-described test method, it is not always necessary to use three DC ammeters.
1, 12, 13 may be changed each time, or the external terminals 11, 12, 1, 1
3 may be connected in common, and one DC ammeter may be inserted between the common connection point and the external ground 14.
In this case, the total current value ia _{0 in the} expression (4) can be measured by the one DC ammeter.

In the above test method, all three switch elements 1, 2 and 3 to be tested are turned on in order to obtain the fourth equation (6) of the simultaneous equations relating to the solution. , It is not necessary to do so,
Any two switch elements to be tested may be turned on. For example, the test target switch elements 1 and 2 are turned on, and the total current value at that time is ia. Parallel connection 2
Resistance value Rz of the two test target switch elements 1 and 2
Is

[0029]

(Equation 7)

[0030]

(Equation 8)

It is sufficient to solve the simultaneous equations. This is a simpler solution.

The test method described above is for the case where the number of switch elements to be tested is three. However, the present invention is not limited to this. The test method of the first embodiment is also applicable to the case where there are two switch elements to be tested. The method can be similarly applied, and can be similarly applied to a case where the number of switch elements to be tested is four or more.

Assuming that the number of switch elements to be tested commonly connected to the internal common node is, for example, five, the simultaneous equations are as follows:

[0034]

(Equation 9)

## EQU1 ##

[Embodiment 2] Embodiment 2 is the second embodiment.
In response to the above, a DC power supply for applying a bias to the test target switch element is required outside the semiconductor integrated circuit,
The ground is determined inside the semiconductor integrated circuit.
FIG. 2 is a diagram illustrating a test method of the semiconductor integrated circuit A according to the second embodiment. The same reference numerals as in FIG. 1 of the first embodiment indicate the same components in FIG. 2 of the second embodiment, and the connection relationship between them is as described above. Detailed description is omitted. The configuration specific to the second embodiment is as follows. As a measure for measuring the on-resistance value of each of the test target switch elements 1, 2 and 3 in the semiconductor integrated circuit A, a ground switch element 9 is provided in advance inside the semiconductor integrated circuit A, and the ground switch element 9 is provided. One end is connected to the internal ground 10 and the other end is connected to the internal common node 4.

In the test for measuring the on-resistance values of the switch elements 1, 2 and 3 to be tested, the external terminals 11, 12 and
13 and the external power supply 15
1, 22, 23 are connected. The DC voltage from the external power supply 15 is Vdd, the on-resistance values of the test switch elements ₁ , ₂ , ₃ are R1, R2, R3, and the on-resistance value of the ground switch element 9 is _R0 .

First, the ground switch element 9 is turned on by the control signal S5. Next, the control signal output circuit 6
The control signal S1 is output to turn on the first test target switch element 1. As a result, a current flows from the external power supply 15 through the path of the DC ammeter 21, the external terminal 11, the first test target switch element 1, the internal common node 4, the ground switch element 9, and the internal ground 10. When the current value measured by the DC ammeter 21 this time and i _1,

[0039]

(Equation 10)

The following holds. Next, the output of the control signal S1 is stopped, and instead, the control signal S2 is output from the control signal output circuit 6.
Is output to turn on the second test target switch element 2, and the current flowing through the second test target switch element 2 and the ground switch element 9 is measured by the DC ammeter 22 connected to the external terminal 12. Assuming that the current value measured by the DC ammeter 22 is i ₂ ,

[0041]

[Equation 11]

Holds. Further, the output of the control signal S2 is stopped, and the control signal S
3 is output to turn on the third test target switch element 3, and the current flowing through the third test target switch element 3 and the grounding switch element 9 is measured by the DC ammeter 23 connected to the external terminal 13. If the current value measured by the DC ammeter 23 is i ₃ ,

[0043]

(Equation 12)

Holds. The unknowns are R ₁ , R ₂ , R ₃ ,
Since there are four of R ₀ , another equation is needed. Therefore, the control signals S1, S
2, S3 to output three test target switch elements 1,
2 and 3 are both turned on, and the DC ammeter 21,
The current values measured at 22 and 23 are ib ₁ , ib ₂ and i
and b _3, the sum of these current values and ib _0. What is important here is not a separate current value, which is the total current value ib _0. The three switch elements 1, 2 and 3 to be tested are connected in parallel, and the combined resistance value is Rz.

[0045]

(Equation 13)

[0046]

[Equation 14]

[0047]

(Equation 15)

The above (10), (11), (12),
By solving the simultaneous equations of (15), the on-resistance R ₀ of the grounding switch element 9 is obtained, and the on-resistances R ₁ , R 3 of the three test target switch elements 1, 2, 3 are further determined.
₂ and R ₃ are specified.

As described above, according to the method for testing a semiconductor integrated circuit of the second embodiment, the external terminals 11, 12, and 13 connected to the switch elements 1, 2, and 3 to be tested are connected to the external power supply 15. And a ground switch element 9 for connecting the internal common node 4 of the test switch elements 1, 2, 3 to the internal ground 10.
Is provided inside the semiconductor integrated circuit A, a current for measuring the on-resistance value can be applied to each of the test target switch elements 1, 2, 3, and the internal common node 4 is connected to the semiconductor integrated circuit A. The on-resistance values R ₁ , R ₂ , and R ₃ of each of the test target switch elements ₁ , ₂ , and ₃ can be measured without providing a dedicated external terminal for drawing out to the outside. In other words, even when the number of external terminals is limited as a semiconductor integrated circuit, a test for measuring the on-resistance value of the switch element to be tested can be performed without any hindrance.

When the test is completed, the ground switch element 9 is turned off. That is, it is necessary to remove the influence of the internal ground 10 on the internal circuit 5. In normal use, if there is no problem if the internal ground 10 is always connected to the internal circuit 5, it is not necessary to interpose the grounding switch element 9 in the first place. However, since there is actually a problem, the grounding switch element 9 is inserted, and the grounding switch element 9 is turned on only in the test mode, and is turned off in the normal use state.

Although three DC ammeters 21, 22, and 23 are used in the above test method, it is not always necessary to use such a method, and one DC ammeter is connected to the external terminal 1
1, 12, 13 may be changed each time, or the external terminals 11, 12, 1, 1
3 may be connected in common, and one DC ammeter may be inserted between the common connection point and the external power supply 15. In this case, (13) the total current value ib ₀ of equation can be measured by one ammeter thereof.

In the above test method, all three switch elements 1, 2 and 3 to be tested are turned on in order to obtain the fourth equation (15) of the simultaneous equations involved in the solution. It is not always necessary to do so, and any two switch elements to be tested may be turned on. For example, the test target switch elements 1 and 2 are turned on, and the total current value at that time is ib. The combined resistance value R of the two test switch elements 1 and 2 connected in parallel
z is

[0053]

(Equation 16)

[0054]

[Equation 17]

It is sufficient to solve the simultaneous equations. This is a simpler solution.

The test method described above is for the case where the number of switch elements to be tested is three. However, the present invention is not limited to this. The test method of the second embodiment can be applied to the case where there are two switch elements to be tested. The method can be similarly applied, and can be similarly applied to a case where the number of switch elements to be tested is four or more.

Assuming that the number of switch elements to be tested commonly connected to the internal common node is, for example, five, the simultaneous equations are as follows:

[0058]

(Equation 18)

Is as follows.

[Embodiment 3] Embodiment 3 is the third embodiment.
In order to draw out the internal common node to the outside of the semiconductor integrated circuit, one switch element to be tested and an external terminal connected thereto are used. FIG. 3 is a diagram illustrating a test method of the semiconductor integrated circuit A according to the third embodiment.
The same reference numerals as those in FIG. 1 of the first embodiment indicate the same components in FIG. 3 of the third embodiment, and the connection relationship between them is as described above. Detailed description is omitted. The configuration specific to the third embodiment is as follows. Both a DC power supply for applying a bias to the test target switch element and a ground are required outside the semiconductor integrated circuit A. Current supply switch element 7 in the first embodiment
Also, the switch element 9 for grounding in the second embodiment is not provided.

In the test of the measurement of the on-resistance values of the switch elements 1, 2 and 3 to be tested, first, the positive terminal of the external power supply 16 is connected to the external terminal 11 connected to the first switch element 1 to be tested. The DC ammeter 2 is connected to the external terminal 12 connected to the second switch element 2 to be tested.
The negative terminal of the external power supply 16 is connected to the external power supply 16 via the DC ammeter 22 to the external terminal 13 connected to the third switch element 3 to be tested. DC voltage from external power supply 16 is Vdd
The on-resistance values of the test target switch elements ₁ , ₂ , and ₃ are R1, R2, and R3.

First, the control signal S is output from the control signal output circuit 6.
1 to turn on the first switch element 1 to be tested, and output the control signal S2 to turn on the second switch element 2 to be tested. As a result, external power supply 1
6 to the external terminal 11, the first test target switch element 1, the internal common node 4, the second test target switch element 2, the external terminal 12, the DC ammeter 21, and the negative terminal of the external power supply 16. A closed loop circuit is formed in the path, and current flows through the closed loop circuit. When the current value measured by the DC ammeter 21 this time and i _12,

[0063]

[Equation 19]

Is established. Next, while the control signal S1 is being output, the control signal S2 is stopped. Instead, the control signal S3 is output from the control signal output circuit 6 to turn on the third test target switch element 3, and the first test target is turned on. A current flowing through the switch element 1 and the third test target switch element 3 is measured by a DC ammeter 22 connected to the external terminal 13. Assuming that the current value measured by the DC ammeter 22 is i ₁₃ ,

[0065]

(Equation 20)

Is satisfied.

Next, the DC ammeter 2 connected to the external terminal 12
1 is removed and the positive terminal of the external power supply 16 is removed from the external terminal 11 and connected to the external terminal 12 instead. Then, the output of the control signal S1 is stopped, and the control signal output circuit 6
The control signals S2 and S3 are output to turn on the second test target switch element 2 and the third test target switch element 3. As a result, from the positive terminal of the external power supply 16 to the external terminal 12, the second test switch element 2, the internal common node 4, the third test switch element 3, the external terminal 13, the DC ammeter 22, the external power supply 16 A closed loop circuit is formed on the path of the negative terminal of the above, and a current flows through this closed loop circuit. When the current value measured by the DC ammeter 22 this time and i _23,

[0068]

(Equation 21)

Is established. Since there are _three unknowns, R ₁ , R ₂ and R ₃ , the above (19), (20), and (21)
By solving the simultaneous equations, the on-resistance values R ₁ , R ₂ , and R ₃ of the _three test target switch elements ₁ , ₂ , and ₃ are specified.

As described above, in the method of testing a semiconductor integrated circuit according to the third embodiment, the current is applied to any two of the switch elements to be tested. Common node 4
And the other switch element to be tested is caused to flow from the internal common node 4 to the outside, so that both the positive side and the negative side of the bias can be obtained outside the semiconductor integrated circuit A. It is possible. Therefore, the current supply switch element 7 as in the first embodiment and the ground switch element 9 as in the second embodiment need not be provided inside the semiconductor integrated circuit A. Element 7 and switch element 9 for grounding
It is not necessary to specifically measure an on-resistance value R ₀ that is not required to be measured. Since the current flows through the two switch elements to be tested in opposite directions, the internal common node 4 is connected to the outside of the semiconductor integrated circuit A with one of the switch elements to be tested and the external terminal connected thereto. Since it is drawn out, it is necessary to measure the on-resistance values R ₁ , R ₂ , and R ₃ of the switch elements ₁ , ₂ , and ₃ to be tested without providing a dedicated external terminal as in the case of the conventional technology. Can be. In other words, even when the number of external terminals is limited as a semiconductor integrated circuit, a test for measuring the on-resistance value of the switch element to be tested can be performed without any hindrance. In the case of the third embodiment, the solution of the simultaneous equations is the simplest and the circuit configuration is also the simplest.

In the above test method, two DC ammeters 21 and 22 are used, but it is not always necessary to do so, and one DC ammeter is connected to the external terminals 11 and 1.
You may make it change to each of 2 and 13 each time.

The above-described test method has been described for the case where the number of switch elements to be tested is three. However, the present invention is not limited to this. Can be applied in a similar manner.

Assuming that the number of switch elements to be tested commonly connected to the internal common node is, for example, five, the simultaneous equations are as follows:

[0074]

(Equation 22)

Is as follows.

[0076]

According to the present invention with respect to the method of testing a semiconductor integrated circuit, each test target switch element can be provided without providing a dedicated external terminal for leading an internal common node to the outside of the semiconductor integrated circuit. A current for measuring the on-resistance value can be passed, and even when the number of external terminals is limited as a semiconductor integrated circuit, the test for measuring the on-resistance value of the switch element to be tested can be performed without restriction. Can be performed without hindrance.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing a test method of a semiconductor integrated circuit according to a first embodiment of the present invention together with a circuit configuration;

FIG. 2 is a connection diagram showing a test method of a semiconductor integrated circuit according to a second embodiment of the present invention together with a circuit configuration;

FIG. 3 is a connection diagram showing a test method of a semiconductor integrated circuit according to a third embodiment of the present invention together with a circuit configuration;

FIG. 4 is a connection diagram showing a conventional test method of a semiconductor integrated circuit together with a circuit configuration;

[Explanation of symbols]

A: semiconductor integrated circuit, 1, 2, 3 ... switch element to be tested, 4 ... internal common node, 5 ... internal circuit, 6 ... control signal output circuit, 7 ... switch element for current supply, 8 ... internal power supply, 9 ... Switch element for grounding, 10 ... internal ground, 1
1, 12, 13 ... external terminal, 14 ... external ground, 1
5, 16 ... external power supply, 21, 22, 23 ... DC ammeter

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G028 AA02 AA03 BB11 CG02 DH01 DH03 FK02 LR01 2G032 AD03 AE07 AE09 AE14 AH02 AK15 5F038 BE05 BE08 CD15 DF14 DF16 DT09 EZ20 9A001 BB05 GG01 HKK35 KK05

Claims (3)

[Claims] 1. A semiconductor integrated circuit test method for measuring the on-resistance value of a plurality of test target switch elements each having one end connected to an internal common node and the other end individually connected to an external terminal, Turn on the current supply switch elements that are connected to the internal power supply in advance and turn on only in the test mode, and turn on a plurality of test target switch elements individually or simultaneously at the same time, in the direction from the internal common node to the external terminal. A test method for a semiconductor integrated circuit, in which a current flows through a switch element to be tested, and an on-resistance value of each switch element to be tested is determined based on a value of a current flowing out of each external terminal in each case. 2. A test method for a semiconductor integrated circuit, comprising measuring on-resistance values of a plurality of test target switch elements each having one end connected to an internal common node and the other end individually connected to an external terminal, Turn on the ground switch elements that are connected to the internal ground in advance and turn on only in the test mode, and turn on a plurality of test target switch elements individually or simultaneously at the same time to test in the direction from the external terminal to the internal common node A test method for a semiconductor integrated circuit, wherein a current flows through a target switch element, and an on-resistance value of each test target switch element is obtained based on measuring a value of a current flowing into each external terminal in each case. 3. A test method for a semiconductor integrated circuit for measuring on-resistance values of a plurality of test target switch elements each having one end connected to an internal common node and the other end individually connected to an external terminal, A switch element to be tested in which the positive electrode of the external power supply for testing is connected to one of the external terminals, the negative electrode is connected to another of the external terminals, and the switch element to be connected is turned on to those external terminals Is based on measuring the value of the current flowing in the direction from the external common terminal to the internal common node and flowing in the direction from the internal common node to the external terminal in another test target switch element. A semiconductor integrated circuit test method for determining an on-resistance value of each switch element to be tested.