JP2000258500A5 - - Google Patents

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Publication number
JP2000258500A5
JP2000258500A5 JP1999061157A JP6115799A JP2000258500A5 JP 2000258500 A5 JP2000258500 A5 JP 2000258500A5 JP 1999061157 A JP1999061157 A JP 1999061157A JP 6115799 A JP6115799 A JP 6115799A JP 2000258500 A5 JP2000258500 A5 JP 2000258500A5
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JP
Japan
Prior art keywords
scan chains
input terminals
scan
changing
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1999061157A
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Japanese (ja)
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JP4283369B2 (en
JP2000258500A (en
Filing date
Publication date
Application filed filed Critical
Priority to JP06115799A priority Critical patent/JP4283369B2/en
Priority claimed from JP06115799A external-priority patent/JP4283369B2/en
Publication of JP2000258500A publication Critical patent/JP2000258500A/en
Priority to US10/452,195 priority patent/US7036060B2/en
Publication of JP2000258500A5 publication Critical patent/JP2000258500A5/ja
Application granted granted Critical
Publication of JP4283369B2 publication Critical patent/JP4283369B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Description

【特許請求の範囲】
【請求項1】
シフトスキャン方式で設計された半導体集積回路であって、
少なくとも2つのテストデータ入力端子と、
前記テストデータ入力端子よりも数の多い複数のスキャンチェーンと、
選択された1つの前記スキャンチェーンにデータを供給するために、前記少なくとも2つのテストデータ入力端子を選択的に結線し、第1のテストモードと第2のテストモードの両方において、前記少なくとも2つのテストデータ入力端子の各々を、選択された1つの前記スキャンチェーンに結線する結線変更回路と、を有し、
前記第1のテストモードにおいて前記少なくとも2つのテストデータ入力端子の各々が結線されるスキャンチェーンの組は、前記第2のテストモードにおいて少なくとも2つの入力端子の各々が結線されるスキャンチェーンの組と異なる半導体集積回路。
【請求項2】
請求項1の半導体集積回路であって、
前記スキャンチェーンの各々は、シフトレジスタとして動作する複数のフリップフロップ回路を有し、
前記結線変更回路は、少なくとも2つの前記スキャンチェーンを1つの入力端子にて相互に結線し、
全ての前記スキャンチェーンは、シフトレジスタとして同時に動作する機能を有し、
前記結線変更回路は、少なくとも2つの前記スキャンチェーンの組を変更する機能を有し、前記変更する動作は、前記結線変更回路に入力されるフェーズ信号の値に応じて実行される半導体集積回路。
【請求項3】
請求項1の半導体集積回路であって、
前記スキャンチェーンの各々は、シフトレジスタとして動作する複数のフリップフロップ回路を有し、
前記結線変更回路は、少なくとも2つの前記スキャンチェーンを1つの入力端子にて相互に結線し、
前記スキャンチェーンからデータを読み出すための出力端子の数は、前記スキャンチェーンの数よりも少なく、
全ての前記スキャンチェーンは、シフトレジスタとして同時に動作する機能を有し、
前記結線変更回路は、少なくとも2つの前記スキャンチェーンの組を変更する機能を有し、前記変更する動作は、前記結線変更回路に入力されるフェーズ信号の値に応じて実行される半導体集積回路。
[Claims]
[Claim 1]
A semiconductor integrated circuit designed by the shift scan method.
At least two test data input terminals and
With multiple scan chains, which are larger than the test data input terminals
The at least two test data input terminals are selectively connected in order to supply data to the one selected scan chain, and the at least two test data input terminals are connected in both the first test mode and the second test mode. It has a connection change circuit that connects each of the test data input terminals to one selected scan chain.
The set of scan chains in which each of the at least two test data input terminals is connected in the first test mode is the set of scan chains in which each of the at least two input terminals is connected in the second test mode. Different semiconductor integrated circuits.
2.
The semiconductor integrated circuit of claim 1.
Each of the scan chains has a plurality of flip-flop circuits that act as shift registers.
The connection change circuit connects at least two of the scan chains to each other at one input terminal.
All the scan chains have a function of operating as shift registers at the same time.
The connection changing circuit has a function of changing at least two sets of the scan chains, and the changing operation is executed according to the value of a phase signal input to the connection changing circuit.
3.
The semiconductor integrated circuit of claim 1.
Each of the scan chains has a plurality of flip-flop circuits that act as shift registers.
The connection change circuit connects at least two of the scan chains to each other at one input terminal.
The number of output terminals for reading data from the scan chain is less than the number of scan chains.
All the scan chains have a function of operating as shift registers at the same time.
The connection changing circuit has a function of changing at least two sets of the scan chains, and the changing operation is executed according to the value of a phase signal input to the connection changing circuit.

JP06115799A 1998-09-22 1999-03-09 Semiconductor integrated circuit Expired - Fee Related JP4283369B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP06115799A JP4283369B2 (en) 1999-03-09 1999-03-09 Semiconductor integrated circuit
US10/452,195 US7036060B2 (en) 1998-09-22 2003-06-03 Semiconductor integrated circuit and its analyzing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP06115799A JP4283369B2 (en) 1999-03-09 1999-03-09 Semiconductor integrated circuit

Publications (3)

Publication Number Publication Date
JP2000258500A JP2000258500A (en) 2000-09-22
JP2000258500A5 true JP2000258500A5 (en) 2006-03-30
JP4283369B2 JP4283369B2 (en) 2009-06-24

Family

ID=13163034

Family Applications (1)

Application Number Title Priority Date Filing Date
JP06115799A Expired - Fee Related JP4283369B2 (en) 1998-09-22 1999-03-09 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JP4283369B2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004093462A (en) 2002-09-02 2004-03-25 Oki Electric Ind Co Ltd Semiconductor integrated circuit and its testing method
JP4520103B2 (en) * 2003-04-02 2010-08-04 ルネサスエレクトロニクス株式会社 Scan test pattern input method and semiconductor integrated circuit
KR20050078704A (en) * 2004-01-31 2005-08-08 삼성전자주식회사 The scan based automatic test pattern generation test circuit and test method thereby and scan chain reordering method
JP4815326B2 (en) * 2006-10-31 2011-11-16 富士通株式会社 Integrated circuit timing failure improvement apparatus, integrated circuit timing failure diagnosis apparatus and method, and integrated circuit
JP2009042017A (en) * 2007-08-08 2009-02-26 Nec Electronics Corp Scan path circuit and semiconductor integrated circuit
JP2009150726A (en) * 2007-12-19 2009-07-09 Panasonic Corp Semiconductor device
JP5421409B2 (en) * 2012-03-02 2014-02-19 Wit株式会社 Appearance inspection apparatus and appearance inspection method
JP6221433B2 (en) * 2013-07-09 2017-11-01 株式会社ソシオネクスト Semiconductor integrated circuit

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