JP2000252386A - Display - Google Patents

Display

Info

Publication number
JP2000252386A
JP2000252386A JP5187799A JP5187799A JP2000252386A JP 2000252386 A JP2000252386 A JP 2000252386A JP 5187799 A JP5187799 A JP 5187799A JP 5187799 A JP5187799 A JP 5187799A JP 2000252386 A JP2000252386 A JP 2000252386A
Authority
JP
Japan
Prior art keywords
electrode
extended
semiconductor element
display device
driving semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5187799A
Other languages
Japanese (ja)
Other versions
JP3974725B2 (en
Inventor
Kenichi Komurasaki
賢一 小紫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP5187799A priority Critical patent/JP3974725B2/en
Publication of JP2000252386A publication Critical patent/JP2000252386A/en
Application granted granted Critical
Publication of JP3974725B2 publication Critical patent/JP3974725B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

PROBLEM TO BE SOLVED: To prevent variable display and a connection failure between an electrode terminal of a semiconductor device for driving and an electrode pad of an extended electrode. SOLUTION: On a non-indication region of a signal-side substrate, a pattern of extended electrodes 18(18a, 18b, (18c)) is formed and a semiconductor device for driving is bonded face down. Electrode pads 20a of the extended electrodes 18a are arranged by a pitch P1 and electrode pads 20b of the extended electrodes 18b, (18c) are arranged by a pitch P2. In correspondence with these electrodes pads 20a, 20b, electrode terminals of the semiconductor device for driving are also formed by the same pitches P1, P2. The extended width L of each electrode pad 20a and the width D of each electrode terminal 21a for output are so set as to satisfy (L-D)<(P2-P1).

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は駆動用半導体素子を
フェイスダウンにて実装してなる液晶表示装置やEL表
示装置などの表示装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device such as a liquid crystal display device or an EL display device in which a driving semiconductor element is mounted face-down.

【0002】[0002]

【従来の技術】公知の液晶表示装置を図4〜図9により
説明する。図4はCOG方式の液晶表示装置1の平面
図、図5は図4のX−X断面線による断面図、図6は駆
動用半導体素子付近の要部断面図、図7は駆動用半導体
素子付近の要部平面図、図8は駆動用半導体素子が搭載
される電極パッド群の要部平面図である。
2. Description of the Related Art A known liquid crystal display device will be described with reference to FIGS. 4 is a plan view of the COG-type liquid crystal display device 1, FIG. 5 is a cross-sectional view taken along the line XX of FIG. 4, FIG. 6 is a cross-sectional view of a main part near the driving semiconductor element, and FIG. FIG. 8 is a plan view of a main part of the vicinity, and FIG. 8 is a plan view of a main part of an electrode pad group on which a driving semiconductor element is mounted.

【0003】COG方式の液晶表示装置1によれば、内
面にITOの透明電極2、3が形成されたガラス基板か
ら成る走査側基板4と信号側基板5が対向して配置さ
れ、各透明電極2、3の上にはポリイミド系樹脂の配向
膜が設けられ、さらに双方の基板4、5はシール部材6
を介して固定され、たとえば樹脂球状体からなるスペー
サ7でもって基板間隔を一定にして、液晶8が封入され
ている。駆動用半導体素子9が信号側基板5の非表示部
領域12上に設けられ、さらに入力ケーブル用のFPC
10と接続されている。
According to the COG type liquid crystal display device 1, a scanning side substrate 4 and a signal side substrate 5 each formed of a glass substrate having ITO transparent electrodes 2 and 3 formed on the inner surface thereof are arranged to face each other. An alignment film of a polyimide resin is provided on each of the substrates 2 and 3.
The liquid crystal 8 is sealed with the spacing between the substrates fixed by a spacer 7 made of, for example, a resin spherical body. A driving semiconductor element 9 is provided on the non-display area 12 of the signal-side substrate 5, and an FPC for an input cable is provided.
10 is connected.

【0004】また、両者の基板4、5でもって表示部1
1をなし、信号側基板5の非表示部領域12上に、表示
部11をなす多数の透明電極3を延在し、他方の走査側
基板4上の透明電極2もAgペースト13を通して信号
側基板5の非表示部領域12上に延在し、これらで延在
電極14をなす。
[0004] The display unit 1 is provided by both substrates 4 and 5.
1 and a large number of transparent electrodes 3 forming a display unit 11 extend on the non-display area 12 of the signal side substrate 5, and the transparent electrode 2 on the other scanning side substrate 4 also passes through the Ag paste 13 on the signal side. It extends over the non-display area 12 of the substrate 5 and forms an extended electrode 14.

【0005】しかも、駆動用半導体素子9を信号側基板
5上に搭載するには、フェイスダウンにて直接実装する
方式が用いられている。すなわち、金からなる駆動用半
導体素子9のバンプ電極22でもって、エポキシを主成
分とした樹脂中に導電粒子を分散させた異方導電樹脂2
3を介して電気的機械的に接続させる。
Moreover, in order to mount the driving semiconductor element 9 on the signal side substrate 5, a method of directly mounting the semiconductor element 9 face down is used. That is, the anisotropic conductive resin 2 in which conductive particles are dispersed in a resin containing epoxy as a main component is formed by the bump electrodes 22 of the driving semiconductor element 9 made of gold.
3 through an electromechanical connection.

【0006】そして、信号側基板5上の駆動用半導体素
子9が搭載される領域には、図7および図8に示すよう
に延在電極14のパターンを形成している。
In the region on the signal side substrate 5 where the driving semiconductor element 9 is mounted, a pattern of the extended electrode 14 is formed as shown in FIGS.

【0007】各駆動用半導体素子9は長尺形状であり、
表示部11の周辺にそってほぼ平行に配設し、また、駆
動用半導体素子9の搭載面には四周に沿って多数の電極
端子を配列している。駆動用半導体素子9の長辺に配列
された電極端子群のうち一方辺には入力用電極端子が配
列され、これに対応して信号側基板5上には入力用電極
15が配列され、他方の電極端子群は出力用電極端子で
あり、これに対応して信号側基板5上には延在電極14
aが形成されている。駆動用半導体素子9の両短辺に配
列された出力用電極端子群と接続される延在電極14
b、14cも形成されている。
Each of the driving semiconductor elements 9 has a long shape.
A large number of electrode terminals are arranged along the periphery of the display unit 11 in a substantially parallel manner along the periphery of the display unit 11 and on the mounting surface of the driving semiconductor element 9 along four circumferences. An input electrode terminal is arranged on one side of the electrode terminal group arranged on the long side of the driving semiconductor element 9, and an input electrode 15 is arranged on the signal side substrate 5 correspondingly, Are electrode terminals for output, and correspondingly, the extended electrodes 14 are provided on the signal side substrate 5.
a is formed. Extended electrode 14 connected to output electrode terminal groups arranged on both short sides of drive semiconductor element 9
b, 14c are also formed.

【0008】また、駆動用半導体素子9の電極端子群に
ついては、各電極端子を各辺ともにほぼ均等な間隔でも
って配列し、これに対応して延在電極14a、14b、
14cの各端部に設けた電極パッドも同じピッチで配列
されている。
In the electrode terminal group of the driving semiconductor element 9, the electrode terminals are arranged at substantially equal intervals on each side, and the extended electrodes 14a, 14b,.
The electrode pads provided at each end of 14c are also arranged at the same pitch.

【0009】図8は延在電極14aの電極パッド16a
と、延在電極14bの電極パッド16bとを、ともにピ
ッチP1にて配列した場合を示し、電極パッド16a上
に配される出力用電極端子17a、ならびに電極パッド
16b上に配される出力用電極端子17bも示す。
FIG. 8 shows an electrode pad 16a of the extended electrode 14a.
And the electrode pads 16b of the extended electrodes 14b are arranged at a pitch P1. An output electrode terminal 17a disposed on the electrode pad 16a and an output electrode terminal disposed on the electrode pad 16b Terminal 17b is also shown.

【0010】[0010]

【発明が解決しようとする課題】しかしながら、上記の
ような液晶表示装置1においては、延在電極14aと延
在電極14b、14cとの間にて、駆動用半導体素子9
に至る配線長に差があり、配線長の長い延在電極14
b、14cは延在電極14aに比べて配線抵抗が大きく
なり、これにより、表示むらなどの画質劣化が生じてい
た。
However, in the liquid crystal display device 1 described above, the driving semiconductor element 9 is provided between the extended electrode 14a and the extended electrodes 14b and 14c.
The length of the extended electrode 14 having a long wiring length
The wiring resistances of b and 14c are larger than those of the extended electrode 14a, and as a result, image quality deterioration such as display unevenness has occurred.

【0011】また、駆動用半導体素子9を実装する場
合、図9に示すようにy軸方向に振れ易いことから、駆
動用半導体素子9の出力用電極端子17a、17bと、
電極パッド16a、16bとの位置関係にずれが生じ、
このような振れに伴う傾斜角度θが大きくなると、とく
に電極パッド16bと出力用電極端子17bとの位置関
係において顕著なずれが生じ、その結果、駆動用半導体
素子9の出力用電極端子17bにて接続不良が発生する
という課題があった。
When the driving semiconductor element 9 is mounted, it tends to swing in the y-axis direction as shown in FIG. 9, so that the output electrode terminals 17a and 17b of the driving semiconductor element 9
The positional relationship between the electrode pads 16a and 16b is shifted,
When the inclination angle θ due to such a shake becomes large, a remarkable shift occurs particularly in the positional relationship between the electrode pad 16b and the output electrode terminal 17b, and as a result, the output electrode terminal 17b of the driving semiconductor element 9 There is a problem that a connection failure occurs.

【0012】本発明者は上記事情に鑑みて鋭意研究を重
ねた結果、長辺方向にピッチP1にて電極端子を配列
し、短辺方向にピッチP2にて電極端子を配列した駆動
用半導体素子を用いて、長辺方向に配列した電極パッド
における延在寸法幅Lと電極端子幅Dとの関係が(L−
D)<(P2−P1)となるように規定した電極パッド
群上にフェイスダウン接続することで、双方の課題がと
もに解消し得ることを見い出した。
The inventor of the present invention has conducted intensive studies in view of the above circumstances. As a result, a driving semiconductor device having electrode terminals arranged at a pitch P1 in the long side direction and electrode terminals at a pitch P2 in the short side direction. Is used, the relationship between the extended dimension width L and the electrode terminal width D in the electrode pads arranged in the long side direction is (L−
D) It has been found that both problems can be solved by performing face-down connection on an electrode pad group defined so that <P2-P1.

【0013】本発明は上記知見により完成されたもので
あり、その目的は表示むらならびに駆動用半導体素子の
電極端子と延在電極の電極パッドとの間の接続不良をな
くし、これによって高品質かつ高信頼性の液晶表示装置
を提供することにある。
The present invention has been completed based on the above findings, and has as its object to eliminate uneven display and poor connection between the electrode terminals of the driving semiconductor element and the electrode pads of the extended electrodes, thereby achieving high quality and high quality. An object of the present invention is to provide a highly reliable liquid crystal display device.

【0014】また、本発明の他の目的はかかる接続不良
をなくすことで、製造歩留りを高めて、生産コストを低
減させ、これによって低コストな液晶表示装置を提供す
ることにある。
Another object of the present invention is to provide a low cost liquid crystal display device by eliminating the connection failure, thereby increasing the production yield and reducing the production cost.

【0015】さらにまた、本発明の他の目的は表示むら
と接続不良の双方を解消するための設計条件が規定され
たことで、製造工程管理を容易になり、これによっても
生産コストを下げることにある。
Still another object of the present invention is to simplify the manufacturing process management by design conditions for eliminating both display unevenness and poor connection, thereby reducing the production cost. It is in.

【0016】[0016]

【問題点を解決するための手段】本発明の表示装置は、
液晶、ELなどの矩形状の表示部を有する基板の非表示
部領域上に、表示部を構成する多数の電極を延在し端部
に電極パッド群を形成し、表示部の周辺にそってほぼ平
行に配設した長尺状の駆動用半導体素子の各電極端子で
もって電極パッド群上にフェイスダウン接続した構成に
おいて、長辺方向にピッチP1にて、短辺方向にピッチ
P2にて電極端子を配列した上記駆動用半導体素子を、
長辺方向に配列した電極パッドにおける延在寸法幅Lと
電極端子幅Dとの関係が(L−D)<(P2−P1)と
なるように規定した電極パッド群上に配設せしめたこと
を特徴とする。
[Means for Solving the Problems] The display device of the present invention comprises:
On a non-display area of a substrate having a rectangular display such as a liquid crystal or an EL, a large number of electrodes constituting the display are extended to form an electrode pad group at an end, and the electrode pads are formed along the periphery of the display. In a configuration in which each electrode terminal of a long driving semiconductor element arranged substantially in parallel is face-down connected to an electrode pad group, the electrodes are arranged at a pitch P1 in the long side direction and at a pitch P2 in the short side direction. The driving semiconductor element having the terminals arranged therein,
The electrode pads are arranged on an electrode pad group defined such that the relationship between the extended dimension width L and the electrode terminal width D in the electrode pads arranged in the long side direction is (LD) <(P2-P1). It is characterized by.

【0017】[0017]

【発明の実施の形態】以下、本発明の表示装置を液晶表
示装置でもって例示する。本発明は図4と図5に示すC
OG方式の液晶表示装置1と同じ構成であって、駆動用
半導体素子の電極端子配列構造および基板上の電極パッ
ド配列構造に特徴があることで、その部分を図1〜図3
により説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a display device of the present invention will be exemplified by a liquid crystal display device. The present invention uses the C shown in FIGS.
It has the same configuration as that of the OG type liquid crystal display device 1 and is characterized by the electrode terminal arrangement structure of the driving semiconductor element and the electrode pad arrangement structure on the substrate.
This will be described below.

【0018】図1は液晶表示装置1aに搭載した駆動用
半導体素子付近の要部平面図、図2は図1のY−Y線の
断面図、図3は駆動用半導体素子が搭載される電極パッ
ド群の要部平面図である。なお、従来の液晶表示装置1
と同一部材には同一符号を付す。
FIG. 1 is a plan view of a main portion near a driving semiconductor element mounted on the liquid crystal display device 1a, FIG. 2 is a cross-sectional view taken along line YY of FIG. 1, and FIG. 3 is an electrode on which the driving semiconductor element is mounted. It is a principal part top view of a pad group. The conventional liquid crystal display device 1
The same reference numerals are given to the same members.

【0019】液晶表示装置1aによれば、信号側基板5
の非表示部領域12上には延在電極18のパターンが形
成され、駆動用半導体素子9aが延在電極18上にフェ
イスダウンにて接続される。
According to the liquid crystal display device 1a, the signal side substrate 5
The pattern of the extended electrode 18 is formed on the non-display portion region 12 of FIG. 1, and the driving semiconductor element 9 a is connected face-down on the extended electrode 18.

【0020】駆動用半導体素子9aの搭載面には四周に
そって多数の電極端子が配列され、長辺に配列された電
極端子群のうち一方は入力用電極端子であり、信号側基
板5上の入力用電極19と接合され、他方の電極端子群
は出力用電極端子であり、延在電極18aと接合され
る。さらに駆動用半導体素子9aの両短辺に配列された
出力用電極端子群については、延在電極18b、18c
と接続される。
On the mounting surface of the driving semiconductor element 9a, a large number of electrode terminals are arranged along four circumferences. One of the electrode terminals arranged on the long side is an input electrode terminal. The other electrode terminal group is an output electrode terminal, and is joined to the extended electrode 18a. Further, regarding the output electrode terminal groups arranged on both short sides of the driving semiconductor element 9a, the extended electrodes 18b, 18c
Connected to

【0021】そして、図3に示すように延在電極18a
の電極パッド20aはピッチP1にて配列し、延在電極
18b、18cの電極パッド20bはピッチP2にて配
列し、これら電極パッド20a、20bに対応し、駆動
用半導体素子9aの電極端子群も同じピッチP1、P2
にて形成される。また、同図にて、電極パッド20aお
よび電極パッド20bと、駆動用半導体素子9aの出力
用電極端子21aおよび出力用電極端子21bとの位置
関係を示す。なお、出力用電極端子21aと出力用電極
端子21bは一般的な矩形状であるが、これに限定され
るものではなく、円形状、楕円状、角状であってもよ
い。
Then, as shown in FIG.
Are arranged at a pitch P1, the electrode pads 20b of the extended electrodes 18b, 18c are arranged at a pitch P2, and correspond to these electrode pads 20a, 20b, and the electrode terminal group of the driving semiconductor element 9a is also arranged. Same pitch P1, P2
Is formed. Further, FIG. 3 shows the positional relationship between the electrode pads 20a and 20b and the output electrode terminals 21a and 21b of the driving semiconductor element 9a. The output electrode terminals 21a and the output electrode terminals 21b have a general rectangular shape, but are not limited thereto, and may have a circular shape, an elliptical shape, or a square shape.

【0022】本発明においては、電極パッド20aの延
在寸法幅Lと、出力用電極端子21aの電極端子幅Dと
の関係が(L−D)<(P2−P1)となるように規定
している。
In the present invention, the relationship between the extended dimension width L of the electrode pad 20a and the electrode terminal width D of the output electrode terminal 21a is defined so that (LD) <(P2-P1). ing.

【0023】上記構成の液晶表示装置1aにおいては、
かかる規定に基づいてP2>P1であることから、延在
電極18b(もしくは18c)の線幅は延在電極18a
の線幅に比べて大きくなり、これにより、抵抗率が小さ
くなることで、延在電極18bの配線長が延在電極18
aの配線長に比べて長くても、双方間での抵抗差が小さ
くでき、さらには抵抗差をほとんどなくすこともでき、
その結果、信号波形になまりが生じなくなり、表示むら
が防ぐことができた。このような(L−D)は、10〜
30μm、好適には20〜24μmにするとフェイスダ
ウン実装装置の搭載バラツキを十分に吸収できるという
点でよい。
In the liquid crystal display device 1a having the above structure,
Since P2> P1 based on such a rule, the line width of the extended electrode 18b (or 18c) is
The line width of the extended electrode 18b can be reduced by reducing the resistivity of the extended electrode 18b.
Even if it is longer than the wiring length of a, the resistance difference between both can be reduced, and furthermore, the resistance difference can be almost eliminated.
As a result, the signal waveform was not rounded, and display unevenness was prevented. Such (LD) is 10 to
When the thickness is 30 μm, preferably 20 to 24 μm, the variation in mounting of the face-down mounting device can be sufficiently absorbed.

【0024】しかも、駆動用半導体素子9aをフェース
ダウンする際に、所定の配設部位より振れた場合に、電
極パッド20bおよび駆動用半導体素子9aの出力用電
極端子21bとの位置関係において、その振れがもっと
も顕著になるが、ピッチP2をピッチP1に比べて大き
くすることで、その振れの度合いが低減される。そし
て、双方のピッチ差(P2−P1)を(L−D)よりも
大きくすることで、とくに電極パッド20bと出力用電
極端子21bとの間にて接続不良が発生しなくなり、最
大の効果が得られている。
In addition, when the drive semiconductor element 9a is face-down, if it swings from a predetermined disposition portion, the position of the electrode pad 20b and the output electrode terminal 21b of the drive semiconductor element 9a is reduced. Although the vibration is most remarkable, the degree of the vibration is reduced by making the pitch P2 larger than the pitch P1. By making the pitch difference (P2−P1) larger than (LD), a connection failure does not occur particularly between the electrode pad 20b and the output electrode terminal 21b, and the maximum effect is obtained. Have been obtained.

【0025】つぎに一例を示すと、延在電極18b、1
8cの配線長が2.5mmであり、また、延在電極18
aの配線長が1mm、ピッチP1が70μm(電極パッ
ド20aの幅:40μm、各電極パッド20aの隙間:
30μm)、(L−D)が40μmである場合には、ピ
ッチP2を110μm以上にすることで、駆動用半導体
素子9aをフェースダウンした際に振れがあっても、電
極パッド20bと出力用電極端子21bとの間にて接続
不良が発生しなくなった。そして、延在電極18b、1
8cの線幅sについては、延在電極18aとの間にて抵
抗差をなくすために、40μm×(2.5mm/1m
m)=100μmにするとよい。
Next, as an example, the extended electrodes 18b, 1
8c has a wiring length of 2.5 mm.
a has a wiring length of 1 mm, a pitch P1 of 70 μm (width of the electrode pad 20a: 40 μm, a gap between the electrode pads 20a:
30 μm) and (LD) are 40 μm, the pitch P2 is set to 110 μm or more, so that the electrode pad 20 b and the output electrode are provided even if the drive semiconductor element 9 a shakes down when faced down. The connection failure with the terminal 21b no longer occurs. Then, the extended electrodes 18b, 1
The line width s of 8 c is 40 μm × (2.5 mm / 1 m
m) = 100 μm.

【0026】なお、本発明は上記実施形態例に限定され
るものではなく、本発明の要旨を逸脱しない範囲内で種
々の変更や改良等は何ら差し支えない。たとえば、この
実施形態例では液晶表示装置でもって説明しているが、
これに代えてEL表示装置等の他の表示装置においても
同様な作用効果が得られる。
It should be noted that the present invention is not limited to the above embodiment, and various changes and improvements may be made without departing from the scope of the present invention. For example, in this embodiment, a description is given using a liquid crystal display device.
Instead, the same operation and effect can be obtained in other display devices such as an EL display device.

【0027】[0027]

【発明の効果】以上のとおり、本発明の表示装置によれ
ば、表示部を有する基板の非表示部領域上に多数の電極
を延在し端部に電極パッド群を形成し、駆動用半導体素
子の各電極端子でもって電極パッド群上にフェイスダウ
ン接続した場合に、長辺方向にピッチP1にて、短辺方
向にピッチP2にて電極端子を配列した上記駆動用半導
体素子を、長辺方向に配列した電極パッドにおける延在
寸法幅Lと電極端子幅Dとの関係が(L−D)<(P2
−P1)となるように規定した電極パッド群上に配設し
たことで、表示むらならびに駆動用半導体素子の電極端
子と延在電極の電極パッドとの間の接続不良をなくし、
これによって製造歩留りを高めて、生産コストを低減さ
せ、これによって低コストかつ高品質・高信頼性の液晶
表示装置が提供できた。
As described above, according to the display device of the present invention, a large number of electrodes extend on the non-display portion region of the substrate having the display portion, and electrode pad groups are formed at the end portions. When face-down connection is made on the electrode pad group with each electrode terminal of the element, the driving semiconductor element having the electrode terminals arranged at a pitch P1 in the long side direction and at a pitch P2 in the short side direction is connected to the long side. The relationship between the extended dimension width L and the electrode terminal width D in the electrode pads arranged in the direction is (LD) <(P2
-P1), by disposing on the electrode pad group defined to be non-uniformity, it is possible to eliminate display unevenness and connection failure between the electrode terminal of the driving semiconductor element and the electrode pad of the extended electrode,
As a result, the production yield was increased, and the production cost was reduced. As a result, a low-cost, high-quality, high-reliability liquid crystal display device could be provided.

【0028】また、本発明においては、表示むらと接続
不良の双方を解消するための設計条件が規定されたこと
で、製造工程管理を容易になり、これによっても生産コ
ストを下げることができた。
Further, in the present invention, the design conditions for eliminating both the display unevenness and the connection failure are defined, so that the manufacturing process management is facilitated and the production cost can be reduced. .

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る液晶表示装置の要部平面図であ
る。
FIG. 1 is a plan view of a main part of a liquid crystal display device according to the present invention.

【図2】図1に示すY−Y線の断面図である。FIG. 2 is a sectional view taken along line YY shown in FIG.

【図3】本発明に係る液晶表示装置の電極パッド群の要
部平面図である。
FIG. 3 is a main part plan view of an electrode pad group of the liquid crystal display device according to the present invention.

【図4】COG方式の液晶表示装置の平面図である。FIG. 4 is a plan view of a COG type liquid crystal display device.

【図5】図1に示すX−X線の断面図である。FIG. 5 is a sectional view taken along line XX shown in FIG. 1;

【図6】COG方式の液晶表示装置の要部断面図であ
る。
FIG. 6 is a sectional view of a main part of a liquid crystal display device of a COG system.

【図7】COG方式の液晶表示装置の要部平面図であ
る。
FIG. 7 is a plan view of a main part of a COG liquid crystal display device.

【図8】従来の液晶表示装置における電極パッド群の要
部平面図である。
FIG. 8 is a plan view of a main part of an electrode pad group in a conventional liquid crystal display device.

【図9】駆動用半導体素子の実装振れを示す平面図であ
る。
FIG. 9 is a plan view showing a mounting deflection of the driving semiconductor element.

【符号の説明】[Explanation of symbols]

1、1a 液晶表示装置 2、3 透明電極 4 走査側基板 5 信号側基板 6 シール部材 8 液晶 9、9a 駆動用半導体素子 11 表示部 12 非表示部領域 14、14a、14b、14c、18、18a、18
b、18c延在電極 15 入力用電極 16a、16b 電極パッド 17a、17b 出力用電極端子 20a、20b 電極パッド 23 異方導電樹脂 P1、P2 ピッチ L 電極パッド20aの延在寸法幅 D 出力用電極端子の電極端子幅
DESCRIPTION OF SYMBOLS 1, 1a Liquid crystal display device 2, 3 Transparent electrode 4 Scanning substrate 5 Signal side substrate 6 Sealing member 8 Liquid crystal 9, 9a Driving semiconductor element 11 Display part 12 Non-display part area 14, 14a, 14b, 14c, 18, 18a , 18
b, 18c extension electrode 15 input electrode 16a, 16b electrode pad 17a, 17b output electrode terminal 20a, 20b electrode pad 23 anisotropic conductive resin P1, P2 pitch L extension dimension width of electrode pad 20a D output electrode terminal Electrode terminal width

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 3/34 501 H05K 3/34 501E Fターム(参考) 2H092 GA45 GA48 GA60 NA01 NA15 NA29 PA02 PA03 5C094 AA03 AA42 AA43 AA44 AA48 BA27 BA43 CA19 DA09 DB02 DB10 FA01 GB01 5E319 AA03 AB05 AC11 BB16 CC61 GG09 GG15 5E336 AA04 BC34 EE08 GG21 5F044 KK01 KK11 QQ02 ──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. 7 Identification code FI Theme coat ゛ (Reference) H05K 3/34 501 H05K 3/34 501E F term (Reference) 2H092 GA45 GA48 GA60 NA01 NA15 NA29 PA02 PA03 5C094 AA03 AA42 AA43 AA44 AA48 BA27 BA43 CA19 DA09 DB02 DB10 FA01 GB01 5E319 AA03 AB05 AC11 BB16 CC61 GG09 GG15 5E336 AA04 BC34 EE08 GG21 5F044 KK01 KK11 QQ02

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】液晶、ELなどの矩形状の表示部を有する
基板の非表示部領域上に、上記表示部を構成する多数の
電極を延在し、その端部に電極パッド群を形成し、表示
部の周辺にそってほぼ平行に配設した長尺状の駆動用半
導体素子の各電極端子でもって上記電極パッド群上にフ
ェイスダウン接続した表示装置であって、長辺方向にピ
ッチP1にて、短辺方向にピッチP2にて電極端子を配
列した前記駆動用半導体素子を、長辺方向に配列した電
極パッドにおける延在寸法幅Lと電極端子幅Dとの関係
が(L−D)<(P2−P1)となるように規定した電
極パッド群上に配設せしめたことを特徴とする表示装
置。
1. A large number of electrodes constituting the display section are extended on a non-display section area of a substrate having a rectangular display section such as a liquid crystal display or an EL display, and an electrode pad group is formed at an end thereof. A display device which is face-down connected to the electrode pad group with each electrode terminal of a long driving semiconductor element disposed substantially in parallel along the periphery of the display section, wherein a pitch P1 is set in a long side direction. In the above, the relationship between the extended dimension width L and the electrode terminal width D in the electrode pads arranged in the long side direction with respect to the driving semiconductor element in which the electrode terminals are arranged at the pitch P2 in the short side direction is (LD). A display device characterized by being disposed on an electrode pad group defined so as to satisfy (P2-P1).
JP5187799A 1999-02-26 1999-02-26 Display device Expired - Lifetime JP3974725B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5187799A JP3974725B2 (en) 1999-02-26 1999-02-26 Display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5187799A JP3974725B2 (en) 1999-02-26 1999-02-26 Display device

Publications (2)

Publication Number Publication Date
JP2000252386A true JP2000252386A (en) 2000-09-14
JP3974725B2 JP3974725B2 (en) 2007-09-12

Family

ID=12899123

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5187799A Expired - Lifetime JP3974725B2 (en) 1999-02-26 1999-02-26 Display device

Country Status (1)

Country Link
JP (1) JP3974725B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6822720B2 (en) * 2000-03-09 2004-11-23 Advanced Display Inc. Liquid crystal display having improved connection between TFT and TCP

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6822720B2 (en) * 2000-03-09 2004-11-23 Advanced Display Inc. Liquid crystal display having improved connection between TFT and TCP
US7102721B2 (en) 2000-03-09 2006-09-05 Advanced Display Inc. Liquid crystal display having different shaped terminals configured to become substantially aligned

Also Published As

Publication number Publication date
JP3974725B2 (en) 2007-09-12

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