JP2000252367A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To satisfy a wiring lifetime by a single layer and to suppress an increase in a chip area to a minimum limit by altering current densities of wiring widths of power supply wirings and output signal wirings in shapes so as to become constant, corresponding one narrow part of the widths to the other wide part, approaching the parts and forming the parts. SOLUTION: In order to contract a wiring area, power supply wirings 22 and an output signal wirings 23 are changed stepwise in wiring widths. Since a current flowing to the wirings 32 is large in a portion D and a current flowing to the wirings 22 is the smallest in a portion A, the portions where the currents are least correspond to one another. Thus, the wirings 22 and the wirings 32 are disposed so that the widest part B of the wirings 22 and the narrowest part C of the wirings 32 are disposed to be the same position and the narrowest part A of the wirings and the widest part D of the wirings 32 are disposed at the same position. Further, the wirings 22 and the wirings 32 are approached to satisfy wiring lifetime and its wiring area can be contracted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a reduced wiring width and improved integration.

[0002]

2. Description of the Related Art In recent years, the speed of operation of a semiconductor integrated circuit has been increased,
With the miniaturization of the process, the current density of the wiring is increasing. One of the factors that determine the wiring life is electromigration, and the higher the current density flowing through the wiring,
It is known that the wiring life is shortened. Therefore, in recent years, it has become difficult to satisfy the wiring life, and as a countermeasure, the width of the output signal wiring of a transistor that outputs a large current has to be increased.

FIG. 4A is a plan view showing a power supply wiring and an output signal wiring of a CMOS. CMOS is nMOS
And pMOS, and the drains of these transistors are connected to each other. The power supplied from the two power supply wirings 101 and 102 is
In the figure, a supply is supplied to the source of one of the transistors provided with the gate electrode constituted by the gate electrode wiring 110 via the conductive layer of the via CH shown by a black square, and the output signal wiring 201 is supplied from the drain of the transistor via the via. Is output to

As shown in FIG. 4A, when the widths of the power supply wirings 101 and 102 and the output signal wiring 201 are simply increased, the increase in the wiring width directly leads to an increase in the chip area. Therefore, a method for suppressing an increase in wiring width is required.

[0005] For example, Japanese Patent No. 283
In Japanese Patent No. 3291, as shown in FIG. 4B, two or more branch vias 210 are provided on the output signal wiring 202, and the upper wiring layer is connected to the output signal wiring 202 and arranged in parallel. As a result, two current paths are provided, and a method is employed in which the current density is reduced and the wiring life is satisfied without increasing the wiring width.

[0006]

However, there are few places where the upper aluminum wiring is not used in recent peripheral circuits of a two-layer aluminum product, and the upper wiring is often passed over the transistor. There are limited places where two layers can be used to provide two current paths. Therefore, in a place where the output signal wiring cannot be formed into a two-layer structure, the wiring width must be increased as in the conventional case, and the wiring area becomes large.

For this reason, the effect of the two-layered output signal wiring cannot be said to be sufficient, and a further reduction in the wiring area is required.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor integrated circuit device which can satisfy the wiring life with a single layer and can minimize an increase in chip area. I do.

[0009]

According to a first aspect of the present invention, a power supply line for supplying power to a transistor and an output signal line through which an output signal of the transistor flows are in the same layer. In the semiconductor integrated circuit device provided above and in parallel adjacent to each other,
The wiring width of each of the power supply wiring and the output signal wiring is formed so as to be different so as to keep the current density constant, and the power supply wiring and the output signal wiring are any one of them. The configuration is such that a portion having a narrow wiring width and a portion having a wide wiring width correspond to and are formed close to each other.

According to the invention having such a configuration, by changing the wiring width so that the current density becomes constant, the current in the power supply wiring gradually decreases from the supply side to the terminal side. The output signal wiring gathers the output signal from the transistor as it goes from the terminal side to the output side, and the current increases because the wiring width can be narrowed as it goes.
The wiring width can be increased from the terminal side to the output side.
Combining and approaching the wide and narrow portions of these wirings makes it possible to keep the current density low and satisfy the wiring life while reducing the wiring area, as compared to the case where the wiring width is simply widened. However, an increase in chip area can be minimized.

According to a second aspect of the present invention, in the semiconductor integrated circuit device according to the first aspect, the directions of currents flowing through the power supply wiring and the output signal wiring are the same.

According to the invention having such a configuration, when the current density flowing through the wiring is made constant, the wiring width is gradually narrowed toward the downstream side where the current of the power supply wiring flows, while the output signal wiring is provided with the current flowing through the power supply wiring. Since the width of the wiring can be gradually increased toward the downstream side, if the current flows through these wirings on the same side, the area of the wiring can be reduced by combining the wide part and the narrow part.

According to a third aspect of the present invention, in the semiconductor integrated circuit device according to the first or second aspect, the transistor forms a CMOS.

According to the invention having such a configuration, the power supply current becomes almost the output current, which is effective in the case of a CMOS in which the output signal wiring must be widened.

According to a fourth aspect of the present invention, there is provided the semiconductor integrated circuit device according to any one of the first to third aspects, wherein one of the power supply wiring and the output signal wiring has a gradually increasing width. Are formed in a stepped shape in which the line width gradually becomes narrower, and the stepped steps are combined with each other.

According to the invention having such a configuration, if the wiring is formed in a stepped shape, the area of the wiring can be reduced by combining the wide part and the narrow part while keeping the current density substantially constant. .

According to a fifth aspect of the present invention, in the semiconductor integrated circuit device according to any one of the first to fourth aspects, the line width of one of the power supply wiring and the output signal wiring is gradually increased while the other is wider. Are formed in a tapered shape in which the line width gradually becomes narrower, and the taper in the opposite direction is combined.

According to the invention having such a configuration, if the wiring is formed in a tapered shape, the area of the wiring can be reduced by combining the wide part and the narrow part while keeping the current density substantially constant. .

According to a sixth aspect of the present invention, in the semiconductor integrated circuit device according to any one of the first to fifth aspects, the output signal wiring is wired on both sides thereof.
In this configuration, a signal current is supplied from the power supply wiring of the book.

According to the invention having such a configuration, since a large current flows through the output signal wiring and the wiring width must be increased, the present invention can be suitably applied.

[0021]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a plan view showing the concept of the semiconductor integrated circuit device of the present invention. This semiconductor integrated circuit device is constituted by CMOS. A CMOS is composed of two transistors, an nMOS and a pMOS. The drains of these transistors are connected to each other, and power is supplied to the source of each transistor.

In FIG. 1A, two gate electrode wirings 10 each forming a gate electrode of a CMOS transistor forming two CMOSs are provided. Also,
Two power supply wirings 21 are provided in parallel with the gate electrode wiring 10, and the power supply wirings 21 are connected to the sources of the respective transistors constituting the CMOS via vias 20a. Also, the output signal wiring 3 through which the current output by the switching of these transistors flows.
Reference numeral 1 is connected to the drains of two transistors constituting the CMOS via a via 30a.

In the CMOS, since the current supplied from the power supply wiring 21 is output almost directly to the output signal wiring 31, the wiring width of the output signal wiring 31 needs to be substantially equal to the wiring width of the power supply wiring. This FIG. 1 (a)
When power is supplied from both sides as shown in the above, the wiring width of the output signal wiring 31 is the total wiring width of the power supply wirings 21 on both sides. Therefore, in CMOS, the area occupied by the wiring increases, and the increase in the wiring width directly leads to an increase in the chip area.

Referring to FIG. 1A, the magnitude of the current flowing through the output signal wiring will be considered. Since the output signal from the via in the middle of the wiring is added to the output signal wiring 31, the current value decreases in the order of B → A in FIG. As a result, if the current density is kept constant, the wiring width must be wide at the position B,
In FIG. 1A, the wiring width of the power supply wiring can be narrowed toward the end by removing the dark hatched portion in FIG. 1A from the original wide power supply line. It becomes possible. Similarly, FIG.
Referring to (b), the power supply wiring 22 branches off the current to the transistor, so that the current value becomes smaller as going to the downstream side in the order of D → C. Therefore, at the position of D, the wiring width must be wide. , C, the wiring width can be reduced.

Therefore, by removing the portions shown by the dark hatched lines in FIG. 1B from the original wide power supply wiring and the output signal wiring so as to keep the current density constant in the output transistor, the output signal is reduced. The width of the wiring can be narrowed as it goes to the terminal side away from the output side, and the power supply wiring can be narrowed as it goes downstream, so that the power supply wiring and the output signal wiring can be stepped. It becomes possible.

However, as shown in FIG. 1 (a), when the supply and output directions of the source are the same, a current flows in the direction of the arrow indicated by the broken line I in the figure, so that the current of the source becomes A. And the output current is concentrated in B. If the wiring width is widened to satisfy the wiring life, the wiring becomes wide at the position B, and the area increases.

In the present invention, in order to reduce the wiring area,
As shown in FIG. 1B, the power supply wiring 22 and the output signal wiring 32 both have the wiring width changed stepwise, and the current flows in the direction of the dashed line II in the drawing. The direction of the current flowing through 22 and the direction of the current flowing through output signal wiring 32 are the same. Since the portion D has the largest current flowing through the power supply wiring 32 and the portion A has the smallest current flowing through the output signal wiring 22, the portion having the least current and the portion having the least current mutually. Will correspond. Thus, the widest part B of the output signal wiring 22 and the narrowest part C of the power supply wiring 32 are arranged at the same position, and the narrowest part A of the output signal wiring and the widest part of the power supply wiring 32 are arranged. D
Can be arranged at the same position. Further, by bringing the power supply wiring 22 and the output signal wiring 32 close to each other,
It is possible to reduce the wiring area while securing a wiring width that satisfies the wiring life.

In FIG. 2A, the power supply wiring 22 and the output signal wiring 33 are formed stepwise by removing the dark hatched portions in FIG. 1B, and the power supply wiring 22 and the output signal wiring are formed. 32 is a plan view of the semiconductor integrated circuit device in a state where the current flows in the same direction and the wirings are arranged close to each other.

In FIG. 2A, the power supply wiring and the output signal wiring are formed stepwise, but as shown in FIG. 2B, the wiring of the power supply wiring 23 and the output signal wiring 33 is formed. Can also be tapered,
Similarly, the area of the wiring can be reduced without increasing the current density.

Further, as shown in FIG. 2 (c), even when power is supplied from only one side of the transistor, the power supply wiring 24 and the output signal wiring 34 are formed in a stepped or tapered shape. The area of the wiring can be reduced.

FIG. 2D shows an example in which the present invention is applied to a semiconductor integrated circuit device in which gates are divided and arranged repeatedly. A power supply wiring 25 supplies power to both CMOSs and outputs an output signal. A current flows from the power supply on both sides to the wiring 35.

Next, how much effect is actually obtained will be described with reference to FIG. Here, we will proceed with the following four conditions.

1. The wiring film thickness is set to 0.5 μm. 2. The source supply current is set to 6i [mA] and supplied from both sides. 3. In order to satisfy the wiring life, the current density must be 4i [m
A / μm ² ] or less. 4. The minimum spacing / width of the wiring is 1 μm / 1 μm.

FIG. 3A shows a case where the entire wiring width is simply widened, and FIG. 3B shows a case where the wiring width is changed stepwise according to the current.

Considering the case where power is supplied from both sides as shown in FIG. 3A, the current value supplied to the output signal wiring is 12i because the source supply current 6i [mA] is supplied from both sides. [MA]. Assuming that the wiring width is H, the cross-sectional area of the wiring is 0.5 H [μm ² ], and the current density must be 4 i [mA / μm ² ] or less in order to satisfy the wiring life. The formula is as follows.

12i [mA] ÷ 0.5 H [μm ² ] = 4
i [mA / μm ² ]

When the wiring width H of the output signal wiring is obtained from the above equation, it is 6 μm to satisfy the wiring life of the output signal wiring.
m or more. In addition, since the current supplied to the source is 6i [mA], the width of the power supply wiring is required to be 3 µm or more in the same calculation. Considering the above, the result is as shown in FIG.

Next, the current branched from the via is shown in FIG.
Consider using (b). Since the diffusion layer resistance and the via resistance are much larger than the wiring resistance, the current flowing through each via has substantially the same value. The current value supplied to the source is 6i
[MA], and if there are six vias, a current of i [mA] flows through each via. From this, the current values flowing through the points 9, 10, 11, 12, 13, and 14 indicated by the circles corresponding to the vias of the output signal wiring are i, 2i, 3i, 4i, 5i, and 6i [ m
A]. From that, each point 9,
The required wiring widths for 10, 11, 12, 13, 14 are 1, 2, 3, 4, 5, 6 μm or more, respectively.

Next, considering the power supply wiring, the current values are the points 15, 16, 1 indicated by the circled numbers.
0.5i, i, at the positions of 7, 18, 19, 20 respectively
1.5i, 2i, 2.5i, 3i [mA],
The wiring widths are 0.5, 1, 1.5, 2, 2.5, 3 respectively.
μm is required. However, since the minimum wiring width is 1 μm, the width of the power supply wiring is 1, 1, 1.5, 2, 2.5, 3 μm. Taking the above into consideration, if the output wiring width is made stepwise, it becomes as shown by the hatched wiring in FIG. As a result, when the width of the wiring is simply increased, the width of the CMOS transistor is required to be 14 μm, whereas the width of the CMOS transistor is 10 μm, which is compared with the case where the wiring width is simply increased (in the case of extending in the same direction). Thus, the width of 4 μm can be reduced. Therefore, the chip area can be reduced, and the degree of integration can be improved.

In the above description, a CMOS has been described as an example. However, the present invention is not limited to the CMOS, and a power supply line for supplying power to the transistor and an output signal line connected to the transistor are provided. The present invention can be applied to a semiconductor integrated circuit device provided adjacently and in parallel on the same layer.

[0041]

As described above, according to the semiconductor integrated circuit device of the present invention, the wiring area can be reduced without reducing the wiring life, and the chip area can be reduced.

[Brief description of the drawings]

FIGS. 1A and 1B are plan views showing the concept of a semiconductor integrated circuit device according to the present invention. FIG.
Indicates the case where the power supply and output directions are opposite.

FIGS. 2A and 2B are plan views showing a semiconductor integrated circuit device of the present invention, wherein FIG. 2A shows a case where wiring is stepped, FIG. 2B shows a case where wiring is tapered, and FIG. In the case of (d), (d) is a case where the gate wiring is divided and arranged repeatedly.

3A and 3B are plan views illustrating the effect of the semiconductor integrated circuit device according to the present invention. FIG.
(B) shows a case where the wiring width is changed stepwise according to the current.

4A and 4B are plan views showing a conventional semiconductor integrated circuit device, wherein FIG. 4A shows a case where a wiring is simply thickened, and FIG. 4B shows a case where a wiring has a two-layer structure.

[Explanation of symbols]

 10 gate electrode wiring 20a via 22,23 power supply wiring 30a via 32,33 output signal wiring

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[Procedure amendment]

[Submission date] January 7, 2000 (2000.1.7)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

3. A semiconductor integrated circuit device according to claim 1 or 2, wherein the semiconductor integrated circuit device in which the direction of the respective currents flowing in said output signal lines and the power supply line is equal to or the same.

6. The semiconductor integrated circuit device according to claim 1 , wherein one of the power supply wiring and the output signal wiring has a gradually increasing width and the other has a gradually decreasing width. A semiconductor integrated circuit device, wherein tapered portions in mutually opposite directions are combined.

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0009

[Correction method] Change

[Correction contents]

[0009]

According to a first aspect of the present invention, a power supply line for supplying power to a transistor and an output signal line through which an output signal of the transistor flows are in the same layer. In the semiconductor integrated circuit device provided above and in parallel adjacent to each other,
The width of the power supply wiring is wide on the power supply side,
As the distance from the power supply side decreases, the output signal becomes narrower.
The wiring width of the signal is wide on the output side and away from the output side
, The power supply wiring and the output signal
The wiring is configured such that one of the narrow wiring width portions and the other of the wide wiring width portions correspond to and are formed close to each other.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0010

[Correction method] Change

[Correction contents]

In the semiconductor integrated circuit device according to the second aspect , power is supplied to the transistor through the plurality of vias.
Power supply wiring and transistor output via multiple vias
Output signal wiring that outputs force signals is next to each other on the same layer
In semiconductor integrated circuit devices provided in parallel in contact with
The wiring width of the power supply wiring and the output signal wiring
Changes corresponding to the position of each of the plurality of vias.
And the power supply wiring and the
The output signal wiring has a narrower one of them
The part and the other part with the larger wiring width correspond and are formed close to each other
There is a configuration that has been.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction contents]

According to the invention of this structure, by changing the wiring width such that the current density is constant, since the power supply line gradually current decreases toward the distal side from the supply side, the distal side The output signal wiring gathers the output signal from the transistor as it goes from the terminal side to the output side, and the current increases because the wiring width can be narrowed as it goes.
The wiring width can be increased from the terminal side to the output side.
Combining and approaching the wide and narrow portions of these wirings makes it possible to keep the current density low and satisfy the wiring life while reducing the wiring area, as compared to the case where the wiring width is simply widened. However, an increase in chip area can be minimized.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0012

[Correction method] Change

[Correction contents]

[0012] The semiconductor integrated circuit device according to claim 3 has a configuration in which the direction of the respective currents flowing in said output signal lines and the power supply line becomes the same direction.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0013

[Correction method] Change

[Correction contents]

According to the invention of this structure, when the current density flowing through the wire constant, gradually narrowing the wiring width toward the downstream side of the flow of the current of the power supply lines, while the output signal lines of the current Since the width of the wiring can be gradually increased toward the downstream side, if the current flows through these wirings on the same side, the area of the wiring can be reduced by combining the wide part and the narrow part.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction contents]

According to a fourth aspect of the present invention, there is provided the semiconductor integrated circuit device according to the first aspect, wherein one of the power supply wiring and the output signal wiring has a gradually increasing line width and the other has a line width. It is formed in a step shape gradually narrowing, and has a configuration in which stepped steps are combined with each other.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction contents]

According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit device.
3. The semiconductor device according to claim 2, wherein the power supply wiring and
And the width of one of the output signal wirings gradually increases,
Of the plurality of vias so that
Steps are formed corresponding to each position,
It has a configuration in which step-like steps are combined.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction contents]

According to the fourth and fifth aspects of the present invention, if the wiring is configured in a stepped manner, the area of the wiring can be reduced by combining the wide part and the narrow part while keeping the current density almost constant. Can be.

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction contents]

According to a sixth aspect of the present invention, in the semiconductor integrated circuit device, one of the power supply wiring and the output signal wiring has a tapered shape in which one line width gradually increases and the other line width gradually narrows. It has a configuration in which directional tapers are combined.

[Procedure amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction contents]

According to the invention of this structure, when forming the interconnection tapered, while maintaining the current density substantially constant, by combining a wide portion and a narrow portion, it is possible to reduce the area of the wiring .

[Procedure amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction contents]

In addition, the semiconductor integrated circuit device of the present invention
Means that the output signal wiring is
A structure in which a signal current is supplied from the power supply wiring
be able to.

[Procedure amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction contents]

The semiconductor integrated circuit device of the present invention is
A structure applied to an OS transistor can be employed.

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Claims (6)

[Claims] 1. A semiconductor integrated circuit device in which a power supply line for supplying power to a transistor and an output signal line through which an output signal of the transistor flows are provided adjacent to and in parallel on the same layer, wherein the power supply line And the wiring width of each of the output signal wirings is changed so as to keep the current density constant, and one of the power supply wiring and the output signal wiring has a narrower wiring width. A semiconductor integrated circuit device, wherein a portion and a portion having a larger wiring width correspond to and are formed close to each other. 2. The semiconductor integrated circuit device according to claim 1, wherein directions of respective currents flowing through said power supply wiring and said output signal wiring are the same. 3. The semiconductor integrated circuit device according to claim 1, wherein said transistor forms a CMOS. 4. The semiconductor integrated circuit device according to claim 1, wherein one of the power supply wiring and the output signal wiring has a gradually increasing line width and the other has a gradually decreasing line width. A semiconductor integrated circuit device, wherein the steps are combined with each other. 5. The semiconductor integrated circuit device according to claim 1, wherein one of the power supply wiring and the output signal wiring has a gradually increasing width and the other has a gradually decreasing width. And a taper in mutually opposite directions is combined. 6. The semiconductor integrated circuit device according to claim 1, wherein said output signal wiring has a structure in which a signal current flows from two power supply wirings wired on both sides thereof. A semiconductor integrated circuit device characterized by the above-mentioned.