JP2000236267A - Remote-control carrier generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily improve the generation accuracy of a remote-control carrier signal without using a reference clock by a high-speed oscillator or sharply increasing the circuit scale. SOLUTION: This circuit is equipped with a carrier counter 12, an inverter 13, an MPX 14, a mode control circuit 15, a 1/2 frequency-dividing circuit 16, and a delay circuit 17. The carrier counter 12 counts leading edges or trailing edges of the output signal SG1 of the MPX 14 and generates a remote-control carrier signal Do having previously set cycles and duty. The 1/2 frequency- dividing circuit 16 and delay circuit 17 make the MPX 14 switch the output between the reference clock Di and its inverted signal NDi by cycles of the remote-control carrier signal Do with a timing, where the leading edge and trailing edge of the remote-control carrier signal Do do not coincide each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a remote control carrier generation circuit for generating a remote control carrier signal used for a remote control of a home electric appliance or the like.

[0002]

2. Description of the Related Art In recent years, the number of products using a remote controller has increased remarkably due to the increase of home electric appliances and various media such as digital broadcasts. Improvement is essential. FIG. 4 shows a block diagram of a conventional remote control carrier generation circuit. The conventional remote control carrier generation circuit 40 includes a carrier counter 41 for setting a cycle and a duty of a remote control carrier signal Do (hereinafter, referred to as “carrier signal Do”). The carrier counter 41 receives one edge (rising edge or falling edge) of the input reference clock Di.
, And generates and outputs a carrier signal Do with a cycle and duty preset in the carrier counter 41.

FIG. 5 shows a conventional remote control carrier generation circuit 4.
6 is a timing chart at 0. When the carrier counter 41 is operated, the carrier counter 41 is reset, outputs a carrier signal Do of “H (high)” level, and starts counting one edge (here, a rising edge) of the reference clock Di. When a preset duty (here, the reference clock Di is counted for 5 counts) is counted, the carrier signal Do is set to the “L (low)” level. Then, when a preset period (here, the reference clock Di is counted for 10 counts) is counted, the carrier counter 41 is reset. Thereafter, the same operation is repeated.

[0004]

However, in the conventional remote control carrier generation circuit 40, the cycle of the output carrier signal Do is determined by the cycle of the reference clock Di, and the precision of the cycle of the carrier signal Do is not determined. For improvement, the period of the input reference clock Di is changed, that is, the oscillator connected to the microcomputer or the like is changed to a high-speed oscillator, or the carrier counter 41 is set to both edges (rising edge and rising edge) of the reference clock Di. A significant increase in circuit size was required to enable counting at the falling edge.

An object of the present invention is to provide a remote control carrier generation circuit capable of easily improving the generation accuracy of a remote control carrier signal without using a reference clock by a high-speed oscillator and without significantly increasing the circuit scale. To provide.

[0006]

A remote control carrier generation circuit according to the present invention comprises a clock inversion / non-inversion circuit for inputting a reference clock and switching and outputting between the reference clock and its inverted signal, and a clock inversion / non-inversion circuit. A carrier counter that counts one of a rising edge and a falling edge of an output signal, generates and outputs a remote control carrier signal having a preset cycle and duty, and inputs a remote control carrier signal, and outputs a rising edge and a rising edge of the remote control carrier signal. A control circuit is provided for causing the clock inverting / non-inverting circuit to switch the output between the reference clock and its inverted signal at a timing that does not coincide with the falling edge and for each cycle of the remote control carrier signal.

[0007] According to this configuration, the carrier counter includes:
By counting a reference clock and its inverted signal which are alternately output from the clock inverting / non-inverting circuit for each cycle of the remote control carrier signal and whose switching timing does not coincide with the rising edge and the falling edge of the remote control carrier signal. In addition, it is possible to generate the remote control carrier signal by controlling its cycle at a cycle of 1/2 of the reference clock, and it is possible to improve the generation accuracy of the remote control carrier signal. Furthermore, the carrier counter counts one of the rising edge and the falling edge of the output signal of the clock inverting / non-inverting circuit without using the reference clock from the high-speed oscillator as the reference clock. There is no significant increase.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a remote control carrier generation circuit according to an embodiment of the present invention.
In FIG. 1, reference numeral 10 denotes a remote control carrier generation circuit according to the present embodiment, 11 denotes a clock control circuit, 12 denotes a carrier counter, 13 denotes an inverter, 14 denotes a multiplexer (hereinafter referred to as “MPX”), 15 denotes a mode control circuit, and 16 denotes a mode control circuit. A 1/2 frequency dividing circuit and 17 are delay circuits.

The remote control carrier generation circuit 10 of the present embodiment receives a reference clock Di, generates and outputs a remote control carrier signal Do (hereinafter, referred to as a "carrier signal Do"), and includes a clock control circuit 11 and a carrier counter. 12 are provided.

The clock control circuit 11 includes an inverter 13
, MPX 14, mode control circuit 15, 分 frequency dividing circuit 16, and delay circuit 17. MPX
The reference clock Di is input to one input terminal of the inverter 14 and the input terminal of the inverter 13, and the inverted signal NDi inverted by the inverter 13 is input to the other input terminal of the MPX 14.

The mode control circuit 15 receives the carrier signal Do output from the carrier counter 12 and controls whether or not to output the carrier signal Do to the 回路 frequency dividing circuit 16. The output signal is fixed to the “L (low)” level when the signal is not output to the ／ divider circuit 16. The signal output from the mode control circuit 15 is input to the 分 frequency dividing circuit 16, and the frequency-divided signal SG 2 divided by に よ り by the 分 frequency dividing circuit 16 is input to the delay circuit 17. In the delay circuit 17, the delay time is set to a time shorter than a half cycle of the reference clock Di using a gate delay or the like. The delay signal SG3 delayed by the delay circuit 17 becomes a control signal of the MPX14. The MPX 14 selects and outputs one of two inputs (a reference clock Di and its inverted signal NDi) according to the level of the delay signal SG3.

The inverter 13 and the MPX 14 constitute a clock inverting / non-inverting circuit. Also, the carrier signal D is provided by the 1/2 frequency dividing circuit 16 and the delay circuit 17.
The reference clock Di and its inverted signal ND are supplied to the MPX 14 at a timing that does not coincide with the rising edge and the falling edge of the signal o, and for each cycle of the carrier signal Do.
A control circuit for switching the output with i is configured.

A control clock signal SG1 output from the MPX 14 of the clock control circuit 11 is input to an input terminal of the carrier counter 12. The carrier counter 12 is similar to the carrier counter 41 in the conventional example.
One edge (rising edge or falling edge) of the input signal (here, the control clock signal SG1) is counted, and the carrier signal Do is generated and output to the carrier counter 12 at a preset cycle and duty.

Next, the operation of the remote control carrier generation circuit 10 of the present embodiment will be described with reference to FIGS. 2 and 3. FIG. 2 is a timing chart in the case where the output carrier signal Do is controlled at a cycle of の of the reference clock Di, and FIG. 3 is an output carrier signal Do.
Is a timing chart in a case where is controlled by the cycle of the reference clock Di. Here, the carrier counter 1
2 counts the falling edge of the control clock signal SG1 and outputs a carrier signal Do having a preset cycle and duty. Here, the preset cycle is 10 counts of the control clock signal SG1. And the preset duty is five counts of the control clock signal SG1. MPX14
Outputs the reference clock Di as the control clock signal SG1 when the delay signal SG3 is at "H (high)" level, and outputs the inverted signal NDi of the reference clock Di as the control clock when the delay signal SG3 is at "L (low)" level. It is to be output as signal SG1.

First, a case where the carrier signal Do shown in FIG. 2 is controlled at a cycle of 1/2 of the reference clock Di will be described. In this case, the mode control circuit 15 receives the carrier signal Do output from the carrier counter 12 and outputs the carrier signal Do to the 1/2 frequency dividing circuit 16 as it is. The carrier signal Do becomes a signal SG2 which is frequency-divided by a 1/2 frequency dividing circuit 16, and this frequency-divided signal SG2 becomes a delayed signal SG3 which is delayed by a delay circuit 17, and this delayed signal SG
The control clock signal SG1 output from the MPX 14 controlled by the control unit 3 is input to the carrier counter 12.

[0016] In still a time t _1, when the carrier counter 12 is reset, the carrier counter 12 counts the falling edge of the control clock signal SG1 is inputted, the preset period and outputs a carrier signal Do of the duty I do. At this time, since the carrier signal Do is at the “H” level, the frequency-divided signal SG2 obtained by dividing the carrier signal Do by と な り first goes to the “H” level, whereby the delay time of the delay circuit 17 (t ₂ −t) ₁₎ the time t ₂ the delay signal SG3 after becomes "H" level. Because until the time t ₂ the delay signal SG3 is at "L" level, MPX
14 outputs an inverted signal NDi of the reference clock Di as the control clock signal SG1, the delayed signal at time t ₂ SG3
Becomes "H" level, the MPX 14 outputs the reference clock Di.
As the control clock signal SG1.

The counts falling edge of the carrier counter 12 control the clock signals SG1, at time t ₄ when the carrier signal Do is one cycle output, the carrier counter 12 is reset, the falling edge of the control clock signal SG1 again It counts and outputs a carrier signal Do having a preset cycle and duty. At time t ₄ the carrier signal Do is one cycle output, divided signal SG
2 becomes the "L" level, the delay time (t ₅ -t ₄₎ time t ₅ to the delay signal SG3 after the than this delay circuit 17 becomes "L" level. In until the time t ₅ the delay signal S
Because G3 is at "H" level, MPX14 outputs the reference clock Di as the control clock signal SG1, the time t ₅ the delay signal SG3 becomes "L" level MPX1
4 outputs the inverted signal NDi of the reference clock Di as the control clock signal SG1.

Thereafter, by repeating this operation, the carrier signal D controlled at a half cycle of the reference clock Di is obtained.
o can be generated.

Next, a case where the carrier signal Do shown in FIG. 3 is controlled by the cycle of the reference clock Di will be described. In this case, the mode control circuit 15 does not output the carrier signal Do input from the carrier counter 12 to the 分 frequency dividing circuit 16 but fixes the output to the １ ／ frequency dividing circuit 16 to “L” level. I have. Therefore, the frequency-divided signal SG2 output from the 1/2 frequency dividing circuit 16 is also fixed at the "L" level, and the delay signal SG3 is also fixed at the "L" level, so that the MP controlled by the delay signal SG3
In this case, X14 always outputs the inverted signal NDi of the reference clock Di as the control clock signal SG1. The carrier counter 12 counts the falling edge of the inverted signal NDi of the reference clock Di, which is the control clock signal SG1, so that the reference clock D
It generates and outputs a carrier signal Do controlled in a cycle of i.

As described above, according to the present embodiment, the carrier counter 12 outputs the clock signal from the clock control circuit 11 alternately every cycle of the carrier signal Do, and sets the alternate switching timing to the rising edge and the rising edge of the carrier signal Do. By counting the reference clock Di that does not coincide with the falling edge and the inverted signal NDi thereof, it is possible to generate the carrier signal Do by controlling the cycle thereof at half the cycle of the reference clock Di. The accuracy of Do generation can be improved.
Further, without using the reference clock by the high-speed oscillator as the reference clock Di, the carrier counter 12
Counts one of the rising edge and the falling edge of the output signal SG1 of the clock control circuit 11, and does not greatly increase the circuit scale. As described above, the generation accuracy of the remote control carrier signal can be easily improved without using the reference clock by the high-speed oscillator or significantly increasing the circuit scale.

A mode control circuit 15 is provided as in the present embodiment, and the carrier signal Do is divided by a 1/2 frequency dividing circuit 16.
By fixing the selected output of the MPX 14 to one side without inputting the carrier signal Do, the carrier signal Do controlled by the cycle of the reference clock Di can be generated as in the related art.

[0022]

As described above, according to the remote control carrier generation circuit of the present invention, the cycle of the remote control carrier signal can be determined without using a reference clock by a high-speed oscillator or greatly increasing the circuit size. It is possible to control and generate the signal at a half cycle of the clock, and an excellent effect that the accuracy of generating the remote control carrier signal can be easily improved is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram of a remote control carrier generation circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart according to the embodiment of the present invention.

FIG. 3 is a timing chart according to the embodiment of the present invention.

FIG. 4 is a block diagram of a conventional remote control carrier generation circuit.

FIG. 5 is a timing chart in a conventional remote control carrier generation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Clock control circuit 12 Carrier counter 13 Inverter 14 Multiplexer 15 Mode control circuit 16 1/2 frequency divider 17 Delay circuit

Claims (1)

[Claims] 1. A clock inverting circuit for receiving a reference clock and switching and outputting the reference clock and its inverted signal.
A non-inverting circuit, a carrier counter that counts one of a rising edge and a falling edge of an output signal of the clock inverting / non-inverting circuit, generates and outputs a remote control carrier signal having a preset cycle and duty, and the remote control. A carrier signal is input, and the reference clock and its inverted signal are output to the clock inverting / non-inverting circuit at a timing that does not match the rising edge and the falling edge of the remote control carrier signal, and for each cycle of the remote control carrier signal. A remote control carrier generation circuit, comprising: a control circuit for performing switching between the two.