JP2004187492A - Semiconductor device and control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To add a dead time by a flexible and simple configuration in a semiconductor device generating complementary PWM signals for the purpose of inverter control, for example. <P>SOLUTION: In a dead time addition portion 2A, a time until a figure of a timer 22 reaches a setting value of a register 24a is added as a first dead time when a first PWM signal PWM1 rises whereas a time until the figure of the timer 22 reaches a setting value of the register 24b is added as a second dead time at a rise time of a second PWM signal PWM2. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

  The present invention relates to a semiconductor device that generates a complementary PWM signal, for example, for inverter control, and particularly to a technique for adding a dead time to a complementary PWM signal.

  An inverter circuit 5 having a configuration in which two switching elements 51 and 52 are connected in series as shown in FIG. 11 is widely used as a circuit configuring an induction heating device such as an IH cooker (see Patent Document 1). ). The inverter circuit for driving the motor also has a configuration in which two switching elements are connected in series in each phase, and the three switching elements are connected in parallel in three phases, and basically have the same configuration.

  These inverter circuits are usually controlled using a PWM (Pulse Width Modulation) signal to which a time (dead time) during which they are not simultaneously turned on is added. An example of this signal is shown in FIG. One of the roles of the dead time is to prevent the through current from flowing and the inverter control circuit from being destroyed when the two switching elements are simultaneously turned on, as shown in FIG. It is. In general, as shown in FIG. 13, an optimal switching timing is set in accordance with the on / off characteristics of two different switching elements, and is set for the purpose of minimizing the power loss of the switching elements. . The power loss is determined by the product of the current and the voltage at the time of on / off switching.

  Conventionally, as a method of setting the dead time, 1) a method of using a normal PWM output and adding a dead time on a control circuit, 2) a method of using a PWM output with a fixed dead time from a semiconductor device, 3 (1) A method combining 1) and 2) is known.

  The method 1) is disclosed in, for example, Patent Document 1, and the dead time can be set by adding a control circuit to an inverter drive circuit that controls the induction heating cooker. FIG. 11 shows the basic circuit configuration. The dead time setting circuit 7 generates a signal from the drive control circuit 6 to turn off the two switching elements 51 and 52 simultaneously. As shown in FIG. 13, the dead time td1 is set to a period from the time when Vge2 becomes 0V and the switching element 52 is turned off to the time when the remaining voltage of Vce1 becomes the minimum, and the dead time td2 is set when Vge1 becomes 0V. Thus, the period is set to a period from when the switching element 51 is turned off to when the minus current of ic2 (the free-wheel diode current incorporated in the switching element 1) is almost halved. Both are determined by circuit constants.

  Other than this, a method of realizing the combination of a PWM output and a delay circuit is known. For example, as shown in FIG. 14, each of the PWM signals is delayed by CR circuits 53 and 54 that are arbitrarily set. Add dead time. This makes it possible to generate two types of output signals with dead time as shown in FIG.

  Further, a microcomputer having a function of generating a PWM output to which a dead time is added from a microcomputer so as not to add a control circuit is realized. In the dead time setting in this case, one dead time register for setting the dead time is used, and the same dead time is added at the ON timing and the OFF timing of the PWM signal.

Many of such microcomputers for controlling an inverter include a counter, a comparator, and the like. The counter counts up from 0 to the frequency set value, during which the count value and the duty set value are compared, and when they match, the output signal is inverted to generate a reference PWM signal. At this time, the dead time is inserted by comparing the counter with the dead time set value and delaying the ON timing from the output inversion timing until the values match. In this case, a fixed time can be set for the dead time regardless of the characteristics of the switching element.
JP-A-10-149876

  However, in the above-described Patent Document 1 and the method using the CR circuit, the set dead time is determined by the hardware setting on the substrate, and therefore, only a fixed value can be set for the switching element. For this reason, it is difficult to change / set the optimum value of the dead time, and there is a restriction that a control circuit unit for changing the CR component in hardware is required in order to perform more advanced control. Was. Furthermore, it has been difficult to perform highly accurate control because the PWM signal has a waveform having a time constant and component variations.

  Furthermore, the method of realizing PWM output with dead time as an inverter control microcomputer has only one dead time register, and thus has only a function of adding a common dead time to rising and falling. For this reason, there is no particular problem when controlling an inverter circuit in which the characteristics of a pair of switching elements are symmetric, but when controlling inverter circuits having different switching characteristics, an optimum dead time is set individually. In this case, there is a problem that application is difficult.

  In view of the above-described problem, an object of the present invention is to make it possible to add a dead time flexibly and with a simple configuration in a semiconductor device that generates a complementary PWM signal for inverter control, for example. .

  In order to solve the above-mentioned problem, a solution taken by the invention of claim 1 is that a semiconductor device includes a first PWM signal and a second PWM signal which is an inverted signal of the first PWM signal. A complementary PWM generation unit that generates the first PWM signal; and a dead time addition unit that adds a second dead time to the rising edge of the second PWM signal while adding a first dead time when the first PWM signal rises. The dead time adding unit is configured to be able to individually set the first dead time and the second dead time.

  According to the first aspect of the present invention, the first dead time added at the rise of the first PWM signal and the second dead time added at the rise of the second PWM signal are determined by the dead time adding unit. , Can be set individually. For this reason, more advanced control can be realized more flexibly than in the past.

  According to a second aspect of the present invention, the dead time adding unit according to the first aspect includes a dead time timer and first and second dead time setting registers, and a value of the dead time timer is set to the first dead time. The time until the value of the dead time setting register is reached is set as the first dead time, and the time until the value of the dead time timer reaches the value set in the second dead time setting register is It is set as the second dead time.

  Further, in the invention according to claim 3, the first and second dead time setting registers according to claim 2 are arranged in series.

  In the invention of claim 4, the first and second dead time setting registers in claim 2 are arranged in parallel.

  Further, in the invention according to claim 5, the dead time adding unit according to claim 1 includes first and second dead time timers, and first and second dead time setting registers, The time until the value of the time timer reaches the set value of the first dead time setting register is set as the first dead time, and the value of the second dead time timer is set to the second dead time. The time until the value reaches the setting value of the setting register is set as the second dead time.

  Further, in the invention according to claim 6, the dead time adding unit according to claim 1 includes a first and second dead time setting register and a counter value of a periodic timer included in the complementary PWM generation unit, the first and second dead time setting registers. And a comparator for comparing the setting value of the second dead time setting register with the setting value of the first dead time setting register. In addition, the second dead time is set based on a comparison between the comparator and a set value of the second dead time setting register.

  In the invention of claim 7, the dead time adding unit in claim 1 stores the first and second dead time setting registers in claim 1 and a counter value of a periodic timer of the complementary PWM generation unit. A first comparator for comparing a set value of the first dead time setting register with a set value of the second dead time setting register; and a second comparator for comparing a counter value of the period timer with a set value of the second dead time setting register. Setting the first dead time based on the comparison result by the first comparator, and setting the second dead time based on the comparison result by the second comparator And

  Further, according to the invention of claim 8, the semiconductor device of claim 1 is configured such that at least one of the first and second dead times can be set and changed in response to a dead time switching input. It is assumed that

  In a ninth aspect of the present invention, there is provided an inverter circuit for performing a heating operation by a coil, and the inverter circuit is controlled by giving the first and second PWM signals to which a dead time is added. As a control method in the induction heating device including the semiconductor device according to item 8, the inverter circuit provides a signal as the dead time switching input to the semiconductor device, and according to the dead time switching input received by the semiconductor device, The setting of at least one of the first and second dead times is changed.

  According to a tenth aspect of the present invention, in the control method of the ninth aspect, the inverter circuit outputs an abnormal signal indicating abnormal heating as the dead time switching input, and the semiconductor device receives the abnormal signal. At this time, the setting change is executed.

  In the invention according to claim 11, in the control method according to claim 9, the inverter circuit outputs an analog signal indicating a current value of a heating coil current as the dead time switching input, and the semiconductor device receives the analog signal. The analog signal is AD-converted, and the setting change is executed when the converted value is out of a predetermined range.

  According to the present invention, it is possible to set different dead times for the PWM signal and its inverted signal. Therefore, it is not necessary to change and set the optimum dead time on the circuit, and it is also possible to individually set the optimum dead time, and to perform more advanced control with reduced power loss Becomes possible.

(1st Embodiment)
FIG. 1 is a block diagram showing the configuration of the semiconductor device according to the first embodiment of the present invention. The semiconductor device shown in FIG. 1 generates a PWM signal for controlling an inverter, and is typically realized by a microcomputer.

  In FIG. 1, a complementary PWM generation unit 1 generates a complementary PWM signal before a dead time is added, that is, a first PWM signal PWM1 and a second PWM signal PWM2 which is an inverted signal of the first PWM signal PWM1. The circuit includes registers 11, 17, a cycle setting register 12, comparators 13, 15, a cycle timer 14, a duty setting register 16, and a T flip-flop 18. The cycle timer 14 is restarted by overflow or by comparison with the set value of the cycle setting register 12, and sets the cycle of the original PWM signal PWM0. Further, the on-period of the original PWM signal PWM0 is set by comparing and matching the counter value of the cycle timer 14 with the set value of the duty setting register 16.

  The dead time adding section 2 adds a dead time to the first and second PWM signals PWM1 and PWM2 generated by the complementary PWM generating section 1, and includes an edge detecting section 21, a dead time timer 22, and a buffer register 23. , First and second dead time setting registers 24a and 24b, and first and second dead time insertion units 25a and 25b. The dead time timer 22 restarts in synchronization with the activation timing of the cycle timer 14 and the comparison match between the cycle timer 14 and the duty setting register 16. Then, the time until the value of the dead time timer 22 reaches the set value of the first dead time setting register 24a is added as the first dead time when the first PWM signal PWM1 rises. Is added as a second dead time when the second PWM signal PWM2 rises, until the value of the second PWM signal reaches the value set in the second dead time setting register 24b. Thus, the upper phase signal SU and the lower phase signal SL are generated.

  An interrupt process is used to set data in the buffer register 23 for setting the dead time. In the case of a comparison match interrupt between the cycle timer 14 and the duty setting register 16, the set value of the second dead time is set. In the case of a comparison match interrupt between the cycle timer 14 and the cycle setting register 12, the set value of the first dead time is set. Further, at each interrupt timing, transfer from the second dead time setting register 24b to the first dead time register 24a and transfer from the buffer register 23 to the second dead time setting register 24b are performed. Accordingly, the first dead time setting value is set in the first dead time setting register 24a at the timing of the comparison coincidence interrupt between the period timer 14 and the period setting register 12, while the period timer 14 and the duty At the timing of the comparison match interrupt with the setting register 16, the set value of the second dead time is set.

  FIG. 2 is a timing chart showing the operation of the semiconductor device of FIG. As shown in FIG. 2, at the same time when the period timer 14 starts counting, the original PWM signal PWM0 rises, and the dead time timer 22 starts counting. When the count value of the dead time timer 22 reaches the set value of the first dead time setting register 24a (the set value of the first dead time), the upper-phase signal SU rises, and the first dead time t1 is increased. Is set. Thereafter, when the count value of the cycle timer 14 reaches the value set in the duty setting register 16, the original PWM signal PWM0 falls and the upper phase signal SU falls.

  At this time, the dead time timer 22 starts counting again, and when the count value reaches the set value of the first dead time setting register 24a (the set value of the second dead time), the lower phase signal SL rises. , A second dead time t2 is set. Thereafter, when the count value of the cycle timer 14 reaches the value set in the cycle setting register 12, the lower phase signal SL falls.

  As described above, according to the present embodiment, the first dead time added at the rise of the first PWM signal and the second dead time added at the rise of the second PWM signal are individually set. Can be.

  Further, when this embodiment is compared with a configuration in which the dead time setting is switched using a dead time period register (comparative example), there are the following advantages. That is, in the case of the comparative example, since the buffer register for setting the dead time is not provided, the updating of the register value cannot be performed at the optimum timing. In order to prevent the magnitude relationship from reversing, the only option is to stop the PWM output and then switch it.

  However, according to the present embodiment, although it is necessary to switch the setting of the dead time in the interrupt processing, since the transfer between the two dead time setting registers is performed at the optimal timing by hardware, it is necessary to stop the PWM output. And can be easily realized.

(Second embodiment)
FIG. 3 is a block diagram showing a configuration of a semiconductor device according to the second embodiment of the present invention. Components common to FIG. 1 are denoted by the same reference numerals as in FIG. The difference from FIG. 1 is that first and second dead time setting registers 24a and 24b are arranged in parallel in the dead time adding unit 2A, and buffer registers 23a and 23b are provided respectively. .

  FIG. 4 is a timing chart showing the operation of the semiconductor device of FIG. 3, and the basic operation is the same as that of the first embodiment. However, the update of the set values of the first and second dead time setting registers 24a and 24b is executed at the comparison coincidence timing between the cycle timer 14 and the cycle setting register 12.

  That is, the present embodiment has a configuration in which one buffer register is added as compared with the first embodiment. However, as in the first embodiment, dead time is set in the processing of the PWM cycle setting interrupt and the duty setting interrupt. There is no need to switch the time setting. Further, the buffer register simply transfers data to the dead time setting register at a certain timing (per cycle). Therefore, it can be realized without putting a burden on the CPU.

(Third embodiment)
FIG. 5 is a block diagram showing a configuration of a semiconductor device according to the third embodiment of the present invention. Components common to FIG. 3 are denoted by the same reference numerals as in FIG. The difference from FIG. 3 is that the dead time adding section 2B is provided with first and second dead time timers 22a and 22b for the first dead time and the second dead time, respectively. . The first dead time timer 22a starts in synchronization with the start timing of the cycle timer 14, and the second dead time timer 22b starts in synchronization with the comparison match between the cycle timer 14 and the duty setting register 16.

  FIG. 6 is a timing chart showing the operation of the semiconductor device of FIG. As shown in FIG. 6, at the same time when the period timer 14 starts counting, the original PWM signal PWM0 rises, and the first dead time timer 22a starts counting. Then, when the count value of the dead time timer 22a reaches the set value of the first dead time setting register 24a, the upper phase signal SU rises, and the first dead time t1 is set. Thereafter, when the count value of the cycle timer 14 reaches the value set in the duty setting register 16, the original PWM signal PWM0 falls and the upper phase signal SU falls.

  At this time, the second dead time timer 22b starts counting again, and when the count value reaches the set value of the second dead time setting register 24b, the lower phase signal SL rises and the second dead time t2 Is set. Thereafter, when the count value of the cycle timer 14 reaches the value set in the cycle setting register 12, the lower phase signal SL falls.

  As described above, in the present embodiment as well, the first dead time added at the rise of the first PWM signal and the second dead time added at the rise of the second PWM signal can be individually set. it can. Further, in comparison with the first and second embodiments, the configuration is such that one dead time timer is added. However, according to the present embodiment, it is not necessary to switch the dead time time setting in the interrupt processing, so that the CPU This can be realized without imposing a burden.

  Further, since the timer added in the present embodiment simply measures the set time, the timer conventionally mounted on the microcomputer can be diverted and can be easily realized. .

(Fourth embodiment)
FIG. 7 is a block diagram showing a configuration of a semiconductor device according to the fourth embodiment of the present invention. Components common to FIG. 3 are denoted by the same reference numerals as in FIG. The difference from FIG. 3 is that a dead time timer and an edge detecting unit are omitted in the dead time adding unit 2C, and a comparator 26 and an additional phase discriminator 27 are provided instead.

  The comparator 26 compares the count value of the cycle timer 14 with the first and second dead time setting registers 24a and 24b. The additional phase discriminator 27 inserts the first dead time into the first dead time insertion unit 25a when the comparator 26 detects the comparison coincidence and when the comparison coincides with the first dead time setting register 24a. On the other hand, when the comparison is made with the second dead time setting register 24b, the second dead time insertion unit 25b is instructed to insert the second dead time.

  FIG. 8 is a timing chart showing the operation of the semiconductor device of FIG. As shown in FIG. 8, the original PWM signal PWM0 rises at the same time when the period timer 14 starts counting. When the comparator 26 detects that the count value of the cycle timer 14 has reached the set value of the first dead time setting register 24a, the upper phase signal SU rises, and the first dead time t1 is set. You. Thereafter, when the count value of the cycle timer 14 reaches the value set in the duty setting register 16, the original PWM signal PWM0 falls and the upper phase signal SU falls. At this time, the comparison reference of the comparator 26 is switched from the set value of the first dead time setting register 24a to the set value of the second dead time setting register 24b.

  Further, when the count value of the cycle timer 14 reaches the value set in the second dead time setting register 24b, the lower phase signal SL rises, and the second dead time t2 is set. Thereafter, when the count value of the cycle timer 14 reaches the value set in the cycle setting register 12, the lower phase signal SL falls. At this time, data is transferred from the first and second buffer registers 23a and 23b to the first and second dead time setting registers 24a and 24b, and the comparison reference of the comparator 26 is determined by the second dead time setting register. The setting value of the first dead time setting register 24b is switched from the setting value of the first dead time setting register 24b.

  As described above, in the present embodiment as well, the first dead time added at the rise of the first PWM signal and the second dead time added at the rise of the second PWM signal can be individually set. it can. Further, by using the periodic timer, the dead time timer can be omitted, and the configuration is simplified. Further, the circuit of the comparator can be easily realized by diverting a circuit mounted in a general microcomputer.

(Fifth embodiment)
FIG. 9 is a block diagram showing a configuration of a semiconductor device according to the fifth embodiment of the present invention. Components common to FIG. 7 are denoted by the same reference numerals as in FIG. The difference from FIG. 7 is that the dead time adding unit 2D is provided with first and second comparators 26a and 26b corresponding to the first and second dead time setting registers 24a and 24b, respectively. Is a point.

  FIG. 10 is a timing chart showing the operation of the semiconductor device of FIG. 9, and the basic operation is the same as that of the fourth embodiment. However, there is no need to switch the comparison reference of the comparator, and the operation is simpler.

  That is, in the present embodiment, one comparator is added as compared with the fourth embodiment, but there is no need to switch the comparison reference as in the fourth embodiment. Moreover, it can be realized with a simple configuration in which two identical circuits are arranged. Also, the circuit of the comparator may be a circuit mounted on a general microcomputer, and can be easily realized.

  In the motor drive inverter circuit, since the switching circuits are configured in three phases in parallel, the dead time addition function described in each of the above embodiments can be applied, and the same effects can be obtained.

(Sixth embodiment)
FIG. 16 is a diagram illustrating a configuration of an induction heating device according to a sixth embodiment of the present invention. In FIG. 16, a semiconductor device 31 has the same configuration as that shown in each of the above embodiments, and controls an inverter circuit 32 that performs a heating operation by a coil by supplying an upper phase signal SU and a lower phase signal SL. I do. The semiconductor device 31 is further configured such that at least one of the first and second dead times can be changed in accordance with a dead time switching input. The dead time setting can be changed, for example, by changing the set values of the first and second dead time setting registers 24a and 24b by software control in response to an external interrupt.

  The control for changing the dead time in the present embodiment will be described with reference to FIG. FIG. 17 is a timing chart showing an output change when heating is started in a state where the dead time setting is inappropriate in the induction heating device of FIG. First, once the output increases in accordance with the normal heating sequence, but if the dead time is not properly set, the inverter circuit 32 outputs an abnormal signal SA indicating abnormal heating (factor generation). When the semiconductor device 31 receives this abnormal signal as a dead time switching input, the semiconductor device 31 changes the dead time setting. That is, after the heating is immediately stopped by using the dead time switching input as an external interrupt input, the dead time setting is immediately changed, and heating with an appropriate dead time set value is started. Thereby, it operates normally thereafter.

  Here, the abnormal signal is output as a result of detecting an overcurrent or an overvoltage. For example, the output of the heating sensor is compared with a numerical value set in a normal range by a comparator or the like, and is output when the sensor output is out of the normal range. Since the output mechanism of such an abnormal signal is conventionally provided in the inverter circuit, a detailed description is omitted.

(Seventh embodiment)
FIG. 18 is a diagram illustrating a configuration of an induction heating device according to a seventh embodiment of the present invention. In FIG. 18, a semiconductor device 41 has the same configuration as that shown in each of the above embodiments, and controls an inverter circuit 42 that performs a heating operation by a coil by supplying an upper phase signal SU and a lower phase signal SL. I do. The semiconductor device 41 is further configured such that at least one of the first and second dead times can be changed in accordance with a dead time switching input.

  The control for changing the dead time in the present embodiment is also executed as shown in FIG. 17, similarly to the sixth embodiment. The inverter circuit 42 outputs an analog signal SB indicating the current value of the heating coil current as a dead time switching input. The semiconductor device 41 has an A / D converter 43, and the received analog signal SB is AD-converted by the A / D converter 43. When the converted value is out of the predetermined range in the normal state, the heating is immediately stopped, and then the dead time setting is immediately changed to start heating with an appropriate dead time set value.

  This embodiment has an advantage that the determination value for detecting abnormal heating in the inverter circuit 42 can be easily changed on the semiconductor device 41 side by, for example, software, as compared with the above-described sixth embodiment.

  In the above-described sixth and seventh embodiments, regarding the set value of the dead time, the initial value at the time of starting the heating is set to a value for a heating target having a specific characteristic, In addition to this, it is only necessary to prepare several types of other assumed values for the heating target having different characteristics as change candidates. Then, for example, by sequentially switching the set value of the dead time by software or the like, it is possible to realize an optimal heating characteristic according to the object. For example, in an IH cooker, which is an example of an induction heating device, dead time setting values are prepared for a pan for aluminum or the like and a conventional pan for iron or the like which could not be heated conventionally, and these two types are used. By switching the set values, optimal control can be realized for each.

  As described above, in the present invention, since the dead time can be set individually in the complementary PWM signal, for example, inverter control in an induction heating device such as an IH cooker can be realized more flexibly than in the past. it can.

FIG. 1 is a block diagram illustrating a configuration of a semiconductor device according to a first embodiment of the present invention. 2 is a timing chart illustrating an operation of the semiconductor device of FIG. 1. FIG. 6 is a block diagram illustrating a configuration of a semiconductor device according to a second embodiment of the present invention. 4 is a timing chart showing the operation of the semiconductor device of FIG. FIG. 9 is a block diagram illustrating a configuration of a semiconductor device according to a third embodiment of the present invention. 6 is a timing chart showing the operation of the semiconductor device of FIG. FIG. 14 is a block diagram illustrating a configuration of a semiconductor device according to a fourth embodiment of the present invention. 8 is a timing chart showing the operation of the semiconductor device of FIG. FIG. 15 is a block diagram illustrating a configuration of a semiconductor device according to a fifth embodiment of the present invention. 10 is a timing chart showing the operation of the semiconductor device of FIG. It is an example of a circuit configuration provided with a dead time setting function. It is a figure for explaining dead time and its role. 12 is a timing chart showing the operation of the circuit configuration of FIG. 9 is another example of a circuit configuration having a dead time setting function. 15 is a timing chart showing the operation of the circuit configuration of FIG. It is a figure showing the composition of the induction heating device concerning a 6th embodiment of the present invention. It is a timing chart which shows change control of dead time in a 6th and a 7th embodiment of the present invention. It is a figure showing composition of an induction heating device concerning a 7th embodiment of the present invention.

Explanation of reference numerals

1 Complementary PWM generation units 2, 2A, 2B, 2C, 2D Dead time addition unit 22 Dead time timer 22a First dead time timer 22b Second dead time timer 24a First dead time setting register 24b Second dead time Setting register 26 comparator 26a first comparator 26b second comparator 31, 41 semiconductor device 32, 42 inverter circuit PWM1 first PWM signal PWM2 second PWM signal SA abnormal signal SB analog signal

Claims (11)

A complementary PWM generator that generates a first PWM signal and a second PWM signal that is an inverted signal of the first PWM signal;
A dead time adding unit that adds a first dead time when the first PWM signal rises and adds a second dead time when the second PWM signal rises;
The dead time adding unit,
The semiconductor device according to claim 1, wherein the first dead time and the second dead time can be individually set. In claim 1,
The dead time adding unit,
A dead time timer,
A first and a second dead time setting register,
The time until the value of the dead time timer reaches the value set in the first dead time setting register is set as the first dead time, and the value of the dead time timer is set in the second dead time setting. A semiconductor device, wherein a time until a set value of a register is reached is set as the second dead time. In claim 2,
The semiconductor device, wherein the first and second dead time setting registers are arranged in series. In claim 2,
The semiconductor device according to claim 1, wherein the first and second dead time setting registers are arranged in parallel. In claim 1,
The dead time adding unit,
First and second dead time timers;
A first and a second dead time setting register,
The time until the value of the first dead time timer reaches the set value of the first dead time setting register is set as the first dead time, and the value of the second dead time timer is A semiconductor device, wherein a time until a set value of a second dead time setting register is reached is set as the second dead time. In claim 1,
The dead time adding unit,
First and second dead time setting registers;
A comparator for comparing a counter value of a periodic timer of the complementary PWM generation unit with a set value of the first and second dead time setting registers;
The first dead time is set based on a result of comparison with the set value of the first dead time setting register by the comparator, and the set value of the second dead time setting register by the comparator is set. Wherein the second dead time is set based on a comparison with the above. In claim 1,
The dead time adding unit,
First and second dead time setting registers;
A first comparator for comparing a counter value of a periodic timer of the complementary PWM generation unit with a set value of the first dead time setting register;
A second comparator for comparing a counter value of the period timer with a set value of the second dead time setting register,
Setting the first dead time based on the comparison result by the first comparator and setting the second dead time based on the comparison result by the second comparator. Characteristic semiconductor device. In claim 1,
A semiconductor device, wherein at least one of the first and second dead times is configured to be changeable in response to a dead time switching input. 9. An induction heating device comprising: an inverter circuit for performing a heating operation by a coil; and the semiconductor device according to claim 8, wherein the inverter circuit is controlled by applying the first and second PWM signals to which a dead time is added. ,
The inverter circuit provides a signal to the semiconductor device as the dead time switching input,
A control method, wherein the semiconductor device changes setting of at least one of the first and second dead times according to the received dead time switching input. In claim 9,
The inverter circuit outputs an abnormal signal indicating abnormal heating as the dead time switching input,
The control method, wherein the semiconductor device executes the setting change when receiving the abnormal signal. In claim 9,
The inverter circuit outputs an analog signal indicating a current value of a heating coil current as the dead time switching input,
The control method, wherein the semiconductor device performs A / D conversion on the received analog signal and executes the setting change when the converted value is outside a predetermined range.

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