WO2021014948A1 - Motor control device and motor system - Google Patents

Motor control device and motor system Download PDF

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Publication number
WO2021014948A1
WO2021014948A1 PCT/JP2020/026342 JP2020026342W WO2021014948A1 WO 2021014948 A1 WO2021014948 A1 WO 2021014948A1 JP 2020026342 W JP2020026342 W JP 2020026342W WO 2021014948 A1 WO2021014948 A1 WO 2021014948A1
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Prior art keywords
phase
period
motor
pwm
signal
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PCT/JP2020/026342
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French (fr)
Japanese (ja)
Inventor
隆志 大場
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ミネベアミツミ株式会社
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Publication of WO2021014948A1 publication Critical patent/WO2021014948A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P23/00—Arrangements or methods for the control of AC motors characterised by a control method other than vector control
    • H02P23/04—Arrangements or methods for the control of AC motors characterised by a control method other than vector control specially adapted for damping motor oscillations, e.g. for reducing hunting
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P27/00—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage
    • H02P27/04—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage
    • H02P27/06—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters
    • H02P27/08—Arrangements or methods for the control of AC motors characterised by the kind of supply voltage using variable-frequency supply voltage, e.g. inverter or converter supply voltage using dc to ac converters or inverters with pulse width modulation

Definitions

  • the present invention relates to a motor control device and a motor system.
  • a motor control device for a three-phase motor drives a motor by energizing a coil of each phase using a PWM (Pulse Width Modulation, pulse width modulation) signal corresponding to each of the U, V, and W phases. It is controlled (see Patent Document 1).
  • PWM Pulse Width Modulation, pulse width modulation
  • FIG. 7 shows a waveform of one cycle of PWM signals U, V, W corresponding to the U phase, V phase, and W phase generated by a conventional motor control device, and a PWM carrier that determines the PWM cycle (simply, “carrier”. An example of the waveform of the current of the motor is shown.
  • the PWM signals of the U phase, the V phase, and the W phase all become high levels, and when shifting to the zero vector section Tz, the current I of the motor decreases toward zero.
  • the U-phase PWM signal becomes low level at time t1
  • the current I rapidly increases and a large current ripple occurs.
  • This current ripple increases as the ratio of the zero vector interval (energization stop period) Tz to one cycle of the PWM signal increases due to the optimization of the zero vector in the motor control. Periodic changes in such large current ripples cause noise.
  • the present invention has been made in view of the above, and an object of the present invention is to provide a motor control device capable of suppressing noise.
  • the motor control device includes a control unit that generates a PWM signal corresponding to each phase of a motor having a plurality of phases of coils, and a control unit for each phase based on the PWM signal.
  • the control unit includes an inverter circuit for driving a coil, and when a zero vector section in which the signal levels of the PWM signals of each phase match occurs, the control unit energizes the coil of each phase in the zero vector section. It is characterized in that an energized section is generated.
  • the motor control device (100) is applied to each phase (U, V, W) of the motor (4) having a multi-phase coil (Lu, Lv, Lw).
  • a control unit (20) that generates PWM signals (U, V, W, UH, UL, VH, VL, WH, WL) corresponding to each, and an inverter that drives the coil of each phase based on the PWM signal.
  • the control unit includes the circuit (23), and when a zero vector section (Tz) in which the signal levels of the PWM signals of each phase match is generated, the control unit sets the coil of each phase in the zero vector section. It is characterized in that an energization section (Te) to be energized is generated.
  • control unit may invert the PWM signals of each phase in the zero vector section for the same time (Te) at different timings.
  • the control unit is set by a duty ratio setting unit (39) for setting the duty ratio of the PWM signal of each phase and the duty ratio setting unit. It has a PWM signal generation unit (32) that generates the PWM signal of each phase based on the duty ratio, and one cycle of the PWM signal of each phase is the first period (A) and the remaining thirst. Including the two periods (B), the PWM signal generation unit inverts the PWM signals of each phase at different timings for a certain period of time in the first period, and is based on the duty ratio in the second period. The PWM signal may be inverted.
  • the control unit has a sawtooth-shaped first carrier (C1) having a period corresponding to the first period and a period corresponding to the second period. It further has a carrier generation unit (37) that generates a saw-like second carrier (C2), and the PWM signal generation unit has a fixed first threshold value (Udu1, Vdu1, Wdu1) and a second threshold value. Based on the result of comparison between (Udu2, Vdu2, Wdu2) and the level of the first carrier, the timing at which the PWM signal of each phase in the first period is inverted was determined and set based on the duty ratio.
  • the PWM signal of each phase in the second period is inverted.
  • the timing may be determined.
  • the motor system (1) includes the motor control device (100) and the motor (4) according to any one of [1] to [4]. It is characterized by being prepared.
  • FIG. 1 is a diagram showing a configuration example of a motor system according to an embodiment.
  • the motor system 1 shown in FIG. 1 controls the rotational operation of the motor 4.
  • the equipment on which the motor system 1 is mounted is, for example, a copier, a personal computer, a refrigerator, and the like, but the equipment is not limited thereto.
  • the motor system 1 includes at least a motor 4 and a motor control device 100.
  • the motor 4 has a plurality of coils.
  • the motor 4 has, for example, a three-phase coil including a U-phase coil Lu, a V-phase coil Lv, and a W-phase coil Lw.
  • Specific examples of the motor 4 include a three-phase brushless motor.
  • the U-phase coil Lu, the V-phase coil Lv, and the W-phase coil Lw are connected to each other by, for example, a star connection.
  • the motor control device 100 converts DC into three-phase AC by controlling ON / OFF of a plurality of switching elements connected by a three-phase bridge according to an energization pattern including a three-phase PWM signal. To drive.
  • the motor control device 100 includes an inverter circuit 23, a control unit 20, and a current detector 24.
  • the inverter circuit 23 converts the DC power supplied from the DC power supply 21 into three-phase AC by switching a plurality of switching elements, and causes the motor 4 to rotate the rotor of the motor 4 by passing the drive current of the three-phase AC to the motor 4. It is a circuit.
  • the inverter circuit 23 is applied to a plurality of energization patterns generated by the energization pattern generation unit 35 described later (more specifically, a three-phase PWM signal generated by the PWM signal generation unit 32 in the energization pattern generation unit 35). Based on this, the motor 4 is driven.
  • the inverter circuit 23 has a plurality of switching elements 25U +, 25V +, 25W +, 25U ⁇ , 25V ⁇ , 25W ⁇ connected by a three-phase bridge.
  • the switching elements 25U +, 25V +, and 25W + are high-side switching elements (upper arms) connected to the positive electrode side of the DC power supply 21 via the positive bus 22a, respectively.
  • the switching elements 25U-, 25V-, and 25W- are low-side switching elements (lower arms) connected to the negative electrode side (specifically, the ground side) of the DC power supply 21, respectively.
  • the plurality of switching elements 25U +, 25V +, 25W +, 25U-, 25V-, and 25W- correspond to each of the plurality of drive signals supplied from the drive circuit 33 based on the PWM signals included in the above-mentioned energization pattern. It turns on or off according to the drive signal.
  • a plurality of switching elements 25U +, 25V +, 25W +, 25U ⁇ , 25V ⁇ , 25W ⁇ may be simply referred to as switching elements unless otherwise specified.
  • connection point between the switching element 25U + and the switching element 25U- is connected to one end of the U-phase coil of the motor 4.
  • the connection point between the switching element 25V + and the switching element 25V- is connected to one end of the V-phase coil of the motor 4.
  • the connection point between the switching element 25W + and the switching element 25W ⁇ is connected to one end of the W-phase coil of the motor 4.
  • the other ends of the U-phase coil, the V-phase coil, and the W-phase coil are connected to each other.
  • the switching element include an N-channel MOSFET (Metal Oxide Semiconductor Field Transistor) and an IGBT (Insulated Gate Bipolar Transistor).
  • the switching element is not limited to these.
  • the current detector 24 outputs a detection signal Sd corresponding to the current value of the current flowing on the DC side of the inverter circuit 23.
  • the current detector 24 shown in FIG. 1 generates a detection signal Sd corresponding to the current value of the current flowing through the negative bus 22b.
  • the current detector 24 is, for example, a current detection element arranged on the negative bus 22b, and more specifically, a resistor (shunt resistance) inserted into the negative bus 22b.
  • a current detection element such as a shunt resistor generates a voltage signal corresponding to the current value of the current flowing through it as a detection signal Sd.
  • the current detector 24 may be a sensor such as a CT (Current Transformer) as long as it outputs a detection signal corresponding to the current value of the current flowing through the negative bus 22b.
  • the control unit 20 generates a plurality of PWM signals corresponding to each phase of the motor 4.
  • the control unit 20 includes, for example, a processor such as a CPU, various storage devices such as RAM and ROM, and peripherals such as a counter (timer), an A / D conversion circuit, a D / A conversion circuit, and an input / output I / F circuit. It is a program processing device (for example, a microcontroller) having a configuration in which circuits are connected to each other via a bus.
  • the control unit 20 is packaged as an IC (integrated circuit), but the present invention is not limited to this.
  • the control unit 20 is based on, for example, the rotation speed command ⁇ ref of the motor 4 input from the host device (not shown) and the phase current of each phase of the motor 4 based on the detection signal Sd of the current detector 24.
  • a PWM signal is generated so that the motor 4 operates properly.
  • the current flow section from the zero vector section (energization stop section) where the PWM signals of the U, V, and W phases are high level or low bell to the coil of each phase.
  • the zero vector section encode stop section
  • the PWM signals of the U, V, and W phases are high level or low bell to the coil of each phase.
  • an energized section for energizing the coils of each phase is generated in the zero vector section.
  • a PWM signal is generated so as to be performed.
  • FIG. 2 is a diagram for explaining an outline of a method for generating a PWM signal according to the present embodiment.
  • FIG. 2 shows a waveform of one cycle of PWM signals U, V, W corresponding to the U phase, V phase, and W phase generated by the motor control device 100 according to the present embodiment, and a waveform of the motor current. Is shown.
  • the PWM cycle is set by the motor based on the first period A for generating the energized section in the zero vector section and the command (rotational speed command ⁇ ref) from the host device. It is divided into a second period B for adjusting the duty ratio so that the motor rotates.
  • the first period A and the second period B are defined by two types of carriers C1 and C2.
  • Carrier C1 is a saw-like carrier whose level increases or decreases in a cycle corresponding to the first period A in the PWM cycle.
  • the carrier C2 is a saw-like carrier whose level increases or decreases in a cycle corresponding to the second period B in the PWM cycle.
  • carriers C1 and C2 are alternately generated, and one continuous set of carriers C1 and C2 determines one cycle (PWM cycle) of PWM signals U, L, and W.
  • the PWM signal U is a PWM signal for driving two switching elements constituting the upper and lower arms of the U phase.
  • the switching element of the lower arm of U phase is on (the switching element of the upper arm of U phase is off), and when the PWM signal U is at high level, the switching element of the lower arm of U phase is on. Is off (the switching element of the upper arm of the U phase is on).
  • the two switching elements constituting the upper and lower arms of the U phase complementarily operate on and off in response to a change in the level of the PWM signal U.
  • the PWM signal V is a PWM signal for driving two switching elements constituting the upper and lower arms of the V phase.
  • the switching element of the lower arm of V phase is on (the switching element of the upper arm of V phase is off), and when the PWM signal V is high level, the switching element of the lower arm of V phase is on. Is off (the switching element of the upper arm of the V phase is on).
  • the two switching elements constituting the upper and lower arms of the V phase complementarily operate on and off in response to a change in the level of the PWM signal V.
  • the PWM signal W is a PWM signal for driving two switching elements constituting the upper and lower arms of the W phase.
  • the switching element of the lower arm of W phase is on (the switching element of the upper arm of W phase is off), and when the PWM signal W is high level, the switching element of the lower arm of W phase is on. Is off (the switching element of the upper arm of the W phase is on).
  • the two switching elements constituting the upper and lower arms of the W phase complementarily operate on and off in response to a change in the level of the PWM signal W.
  • the control unit 20 inverts the signal level of the PWM signal at a predetermined timing to generate an energized section in the zero vector section, and in the second period B, the rotation speed command ⁇ ref and the phase current of each phase.
  • the signal level of the PWM signal of each phase is inverted based on the duty ratio calculated by the vector control based on.
  • the control unit 20 provides an energization period by inverting the PWM signals of each phase at different timings for a certain period of time.
  • the section Te in which the signal level of each PWM signal is inverted has the same length, and the section Te of each PWM signal is shifted from each other.
  • the control unit 20 includes a current detection unit 27, a current detection timing adjustment unit 34, a drive circuit 33, an energization pattern generation unit 35, and a clock generation as functional blocks for generating PWM signals for each phase. It has a unit 36 and a carrier generation unit 37.
  • the current detection unit 27 acquires the detection signal Sd based on a plurality of energization patterns (more specifically, three-phase PWM signals) generated by the energization pattern generation unit 35, so that the U flows through the motor 4. , V, W Phase currents Iu, Iv, Iw of each phase are detected.
  • the current detection unit 27 acquires the detection signal Sd at the acquisition timing synchronized with the plurality of energization patterns (more specifically, the three-phase PWM signals), so that the U, V flowing through the motor 4 , W The phase currents Iu, Iv, and Iw of each phase are detected.
  • the acquisition timing of the detection signal Sd is set by the current detection timing adjusting unit 34.
  • the current detection unit 27 takes in the detection signal Sd of the analog voltage generated by the current detector 24 into the A / D (Analog to Digital) converter at the acquisition timing set by the current detection timing adjustment unit 34.
  • the A / D converter is provided in the current detection unit 27.
  • the current detection unit 27 AD-converts the captured analog detection signal Sd into a digital detection signal Sd, and digitally processes the digital detection signal Sd after the AD conversion, thereby U, V, W of the motor 4.
  • the phase currents Iu, Iv, and Iw of each phase are measured.
  • the measured values of the phase currents Iu, Iv, and Iw of each phase measured by the current detection unit 27 are supplied to the energization pattern generation unit 35.
  • the clock generation unit 36 generates a clock having a predetermined frequency by the built-in oscillation circuit, and outputs the generated clock to the carrier generation unit 37.
  • the clock generation unit 36 starts operation at the same time when the power of the motor control device 100 is turned on, for example.
  • the energization pattern generation unit 35 determines the rotor position of the motor 4 based on the measured values of the phase currents Iu, Iv, and Iw of the motor 4 measured by the current detection unit 27, and the motor 4 is placed at the determined rotor position.
  • a signal for designating a pattern for energizing the inverter circuit 23 is generated so that the rotor follows.
  • the energization pattern of the inverter circuit 23 may be rephrased as a pattern for energizing the motor 4 (energization pattern of the motor 4).
  • the signal that specifies the energization pattern of the inverter circuit 23 includes, for example, a three-phase PWM signal that energizes the inverter circuit 23 so that the motor 4 rotates.
  • the energization pattern generation unit 35 generates the energization pattern of the inverter circuit 23 by vector control.
  • the method of generating the energization pattern of the inverter is not limited to vector control, and may be a method of obtaining the phase voltage of each phase by using vf control or the like.
  • the energization pattern generation unit 35 includes a duty ratio setting unit 39 and a PWM signal generation unit 32.
  • the duty ratio setting unit 39 is a functional unit for generating a PWM signal as a signal for designating the energization pattern of the inverter circuit 23.
  • the duty ratio setting unit 39 sets the duty ratio of the three-phase PWM signal based on the current detection result by the current detection unit 27.
  • the duty ratio setting unit 39 includes, for example, a vector control unit 30 and a duty ratio calculation unit 31.
  • the vector control unit 30 sets the torque current command Iqref and the exciting current based on the difference between the measured value or the estimated value of the rotation speed of the motor 4 and the rotation speed command ⁇ ref. Generate the command Idref.
  • the vector control unit 30 calculates the torque current Iq and the exciting current Id by the vector control calculation using the rotor position ⁇ based on the measured values of the phase currents Iu, Iv, and Iw by the current detection unit 27.
  • the vector control unit 30 performs, for example, a PI control calculation on the difference between the torque current command Iqref and the torque current Iq, and generates the voltage command Vq.
  • the vector control unit 30 performs, for example, a PI control calculation on the difference between the exciting current command Idref and the exciting current Id, and generates the voltage command Vd.
  • the vector control unit 30 converts the voltage commands Vq and Vd into phase voltage commands Vu *, Vv * and Vw * for each of the U, V and W phases using the rotor position ⁇ .
  • the phase voltage commands Vu *, Vv *, and Vw * of each phase are supplied to the duty ratio setting unit 39.
  • the duty ratio calculation unit 31 is a duty ratio (set value of the duty ratio of each phase) for generating a three-phase PWM signal based on the input phase voltage commands Vu *, Vv *, Vw * of each phase. Calculate Udu, Vdu, and Wdu.
  • the duty ratios Udu, Vdu, and Wdu of each phase are calculated based on the modulation factors modU, modV, and modW as shown in the following equations (1) to (3).
  • the duty ratios Udu, Vdu, and Wdu of each phase obtained based on the following equations (1) to (3) are, for example, sinusoidal waveforms having different phases by 120 degrees.
  • An example of waveforms of duty ratios Udu, Vdu, and Wud of each phase will be described later.
  • Udu modU ⁇ (carrier upper limit) ⁇ ⁇ ⁇ (1)
  • Vdu modV ⁇ (carrier upper limit) ⁇ ⁇ ⁇ (2)
  • Wdu modW ⁇ (carrier upper limit) ⁇ ⁇ ⁇ (3)
  • the PWM signal generation unit 32 is a three-phase PWM signal U, V as an energization pattern signal based on the duty ratios Udu, Vdu, Wdu of each phase set by the duty ratio setting unit 39 and the carriers C1 and C2. , W is generated.
  • carriers C1 and C2 are carrier signals whose levels increase and decrease periodically.
  • the PWM signal generation unit 32 generates three-phase PWM signals U, V, W based on the comparison result between the threshold values based on the duty ratios Udu, Vdu, and Wdu of each phase and the carriers C1 and C2.
  • the PWM signal U includes a PWM signal UH for driving the switching element of the U-phase upper arm and a PWM signal UL for driving the switching element of the U-phase lower arm.
  • the PWM signal V includes a PWM signal VH for driving the switching element of the V-phase upper arm and a PWM signal VL for driving the switching element of the V-phase lower arm.
  • the PWM signal W includes a PWM signal WH for driving the switching element of the W phase upper arm and a PWM signal WL for driving the switching element of the w phase lower arm.
  • the drive circuit 33 outputs a drive signal for switching the six switching elements 25U +, 25V +, 25W +, 25U ⁇ , 25V ⁇ , 25W ⁇ included in the inverter circuit 23 according to the energization pattern including the given PWM signal.
  • a three-phase alternating current drive current is supplied to the motor 4, and the rotor of the motor 4 rotates. Since each drive signal output from the drive circuit 33 is a signal having a logic level corresponding to the above-mentioned PWM signals UH, UL, PWM signals VH, VL, and PWM signals WH, WL, it is shown in FIG.
  • Each drive signal output from the drive circuit 33 has the same reference code as the PWM signal.
  • the current detection timing adjusting unit 34 determines the acquisition timing for the current detecting unit 27 to detect the phase currents of two of the three phases within one cycle of the PWM signal.
  • a processor for example, a CPU (Central Processing Unit) performs various calculations according to a program readable and stored in a storage device (not shown). It is realized by doing. For example, each of these functions is realized by the collaboration of hardware and software in a microcomputer including a CPU.
  • a processor for example, a CPU (Central Processing Unit)
  • FIG. 3 is a diagram showing a configuration example of a carrier generation unit 37 and a PWM signal generation unit 32 in the motor control device 100 according to the first embodiment.
  • the carrier generation unit 37 and the PWM signal generation unit 32 perform various calculations according to a program stored in a storage device such as a RAM or ROM in the MCU constituting the control unit 20 described above, and a timer (counter). It is realized by controlling peripheral circuits such as an A / D conversion circuit and an input / output I / F circuit.
  • the carrier generation unit 37 generates the above-mentioned two types of carriers C1 and C2 as the carrier C of the PWM signal of each phase.
  • the carrier generation unit 37 has a saw-like wavy carrier C1 whose level increases or decreases in a cycle corresponding to the first period A in the PWM cycle based on the clock CLK generated by the clock generation unit 36 shown in FIG.
  • a saw-like carrier C2 whose level increases or decreases in a cycle corresponding to the second period B is generated.
  • the carrier generation unit 37 includes a count unit 12, an upper limit value switching unit 13, a comparator 14, a switching control unit 15, and an upper limit value storage unit 16.
  • the counting unit 12 is realized by, for example, a counter (up counter) built in the microcontroller.
  • the clock CLK, the counting start signal, and the counting initial value signal are input to the counting unit 12.
  • the counting unit 12 starts counting the clock CLK, and by accumulating the counting values (adding 1 each time the clock CLK is input), the carriers C1 and C2 which are sawtooth carriers. Is output.
  • an initial value of counting is set in the counting unit 12, and this initial value is set by the above-mentioned initial counting value signal.
  • the comparator 14 compares the count value of the count unit 12 with the upper limit value Tx, and outputs a binary detection signal Cp indicating the comparison result. For example, when the counting value (C1 or C2) of the counting unit 12 is lower than the upper limit value Tx, the comparator 14 outputs a low-level detection signal Cp, and the counting value (C1 or C2) of the counting unit 12 is the upper limit. When the value is higher than the value Tx, the high level detection signal Cp is output.
  • the switching control unit 15 outputs a binary control signal Sc according to the detection signal Cp output from the comparator 14.
  • the switching control unit 15 is, for example, a flip-flop.
  • the switching control unit 15 switches the logic level of the control signal Sc according to the rising edge of the detection signal Cp from the comparator 14.
  • the counting unit 12 resets the clock counting value according to the detection signal Cp output from the comparator 14, and accumulates the clock counting value from the initial value specified by the counting initial value signal. For example, the counting unit 12 resets the clock count value according to the rising edge of the detection signal Cp, and accumulates the clock count value from the initial value.
  • the upper limit value storage unit 16 stores information for designating the cycles of carriers C1 and C2, that is, the lengths of the first period A and the second period B in one cycle of the PWM signal described above. Specifically, the upper limit value storage unit 16 stores the first upper limit value T1 and the second upper limit value T2.
  • the first upper limit value T1 is a value that specifies the period of the carrier C1, that is, the length of the first period A in the PWM cycle.
  • the second upper limit value T2 is a value that specifies the period of the carrier C2, that is, the length of the second period B in the PWM cycle.
  • T T1 + T2 and T1 ⁇ T2.
  • the upper limit value switching unit 13 switches the upper limit value Tx to be input to the comparator 14. Specifically, the upper limit value switching unit 13 sets the first upper limit value T1 and the second upper limit value T2 stored in the upper limit value storage unit 16 as upper limit values according to the control signal Sc output from the switching control unit 15. It is output alternately as Tx. For example, when the control signal Sc is at a low level, the upper limit value switching unit 13 gives the first upper limit value T1 to the comparator 14 as the upper limit value Tx. On the other hand, when the control signal Sc is at a high level, the upper limit value switching unit 13 gives the second upper limit value T2 to the comparator 14 as the upper limit value Tx.
  • FIG. 4 is a diagram for explaining the generation principle of carriers C1 and C2.
  • the counting unit 12 starts counting the clock CLK and accumulates the counting values.
  • the switching control unit 15 outputs, for example, a low-level control signal Sc.
  • the upper limit value switching unit 13 gives the first upper limit value T1 to the comparator 14 as the upper limit value Tx according to the low level control signal Sc.
  • the comparator 14 detects that the count value has reached the upper limit value Tx, and detects a high level. Output the signal Cp.
  • the counting unit 12 resets the counting value according to the high-level detection signal Cp, and starts the cumulative addition of the counting value of the clock CLK from zero again. As a result, the generation of the carrier C1 is completed, and the detection signal Cp of the comparator 14 is switched to the low level.
  • the switching control unit 15 inverts the logic level of the control signal Sc according to the rising edge of the detection signal Cp at time t1. That is, the logic level of the control signal Sc is switched from the low level to the high level.
  • the upper limit value switching unit 13 gives the second upper limit value T2 as the upper limit value Tx to the comparator 14 according to the high level control signal Sc.
  • the detection signal Cp is output.
  • the counting unit 12 resets the counting value according to the high-level detection signal Cp, and starts the cumulative addition of the counting value of the clock CLK from zero again. As a result, the generation of the carrier C2 is completed, and the detection signal Cp of the comparator 14 is switched to the low level.
  • the switching control unit 15 inverts the logic level of the control signal Sc according to the rising edge of the detection signal Cp at time t2. That is, the logic level of the control signal Sc is switched from the high level to the low level.
  • the upper limit value switching unit 13 again gives the first upper limit value T1 to the comparator 14 as the upper limit value Tx according to the low level control signal Sc. After that, the process is repeated in the same manner as the process from time t0 to time t2.
  • the PWM signal generation unit 32 includes a fixed threshold storage unit 40, a variable threshold calculation unit 41, a threshold switching unit 42U, 42V, 42W, a comparator 43U, 43V, 43W, a PWM circuit 44, and an interrupt controller. Has 45.
  • the fixed threshold storage unit 40 contains threshold information for providing an energization section in the zero vector section of the PWM signals U, V, W generated based on the duty ratios Udu, Vdu, Wdu calculated by the duty ratio calculation unit 31. It will be remembered. Specifically, the fixed threshold storage unit 40 corresponds to each of the U phase, the V phase, and the W phase as information for designating the timing at which the signal level of the PWM signal of each phase is switched in the second period B of the PWM cycle.
  • the fixed threshold values Udu1 and Udu2, the fixed threshold values Vdu1 and Vdu2, and the fixed threshold values Wdu1 and Wdu2 are stored.
  • the fixed threshold values Udu1 and Udu2 are values that specify the switching timing of the signal level of the U-phase PWM signal in the first period A of the PWM cycle.
  • the fixed threshold values Vdu1 and Vdu2 are values that specify the switching timing of the signal level of the V-phase PWM signal in the first period A of the PWM cycle.
  • the fixed threshold values Wdu1 and Wdu2 are values that specify the switching timing of the signal level of the W-phase PWM signal in the first period A of the PWM cycle.
  • Udu1 ⁇ Vdu1 ⁇ Wdu1 Udu2 ⁇ Vdu2 ⁇ Udu3 ⁇ Wdu2.
  • variable threshold value calculation unit 41 generates variable threshold value Udu3, Vdu3, Wdu3 so that PWM signals of U-phase, V-phase, and W-phase duty ratios Udu, Vdu, and Wdu set by the duty ratio setting unit 39 are generated. , Udu4, Vdu4, Wdu4 are calculated.
  • variable threshold values Udu3 and Udu4 are values that specify the switching timing of the signal level of the U-phase PWM signal in the second period B of the PWM cycle.
  • the variable threshold values Vdu3 and Vdu4 are values that specify the signal level switching timing of the U-phase PWM signal in the second period B of the PWM cycle.
  • the variable threshold values Wdu3 and Wdu4 are values that specify the switching timing of the signal level of the U-phase PWM signal in the second period B of the PWM cycle.
  • the variable threshold value calculation unit 41 calculates the variable threshold values Udu3 and Udu4 based on the duty ratio Udu of the U phase set by the duty ratio setting unit 39. Similarly, the variable threshold value calculation unit 41 calculates the variable threshold values Vdu3 and Vdu4 based on the duty ratio Vdu of the V phase set by the duty ratio setting unit 39, and of the W phase set by the duty ratio setting unit 39. The variable thresholds Wdu3 and Wdu4 are calculated based on the duty ratio Wdu.
  • the threshold switching units 42U, 42V, 42W switch the thresholds Udux, Vdux, Wdux to be input to the comparators 43U, 43V, 43W. Specifically, the threshold value switching units 42U, 42V, 42W set the threshold value of the output target to the fixed threshold values Udu1, Udu2, Vdu1, Vdu2, Wdu1, Wdu2 according to the switching between the first period A and the second period B. The variable threshold is switched between Udu3, Udu4, Vdu3, Vdu4, Wdu3, and Wdu4.
  • the threshold switching units 42U, 42V, 42W set the fixed thresholds Udu1, Vdu1, Wdu1 and the fixed thresholds Udu2, Vdu2, Wdu2 based on the output signals Cpu, Cpv, Cpw of the corresponding comparators 43U, 43V, 43W. It is switched alternately and output as threshold values Udux, Vdux, and Wdux.
  • the threshold value switching unit 42U sets the fixed threshold value Udu1 and the fixed threshold value Udu2 as the threshold values to be output.
  • the threshold switching unit 42 gives the fixed threshold value Udu1 as the initial value to the comparator 43U as the threshold value Udux.
  • the threshold value switching unit 42 gives the fixed threshold value Udu2 to the comparator 43U as the threshold value Udux when the signal level of the output signal Cpu of the comparator 43U is inverted.
  • the threshold switching unit 42U sets the variable threshold value Udu3 and the variable threshold value Udu4 as the threshold values to be output.
  • the threshold switching unit 42 gives the variable threshold value Udu3 as the initial value to the comparator 43U as the threshold value Udux.
  • the threshold value switching unit 42 gives the variable threshold value Udu4 to the comparator 43U as the threshold value Udux when the signal level of the output signal Cpu of the comparator 43U is inverted.
  • the threshold switching unit 42U again sets the fixed threshold value Udu1 and the fixed threshold value Udu2 as the threshold values to be output. After that, the above-mentioned process is repeated.
  • the PWM circuit 44 outputs PWM signals U, V, W having an on / off section according to a change in the voltage command of each phase based on the output signals Cpu, Cpv, Cpw from the comparators 43U, 43V, 43W.
  • the PWM signals U, V, W include six types of PWM signals, the PWM signals UH, UL, VH, VL, WH, and WL.
  • the above six types of PWM signals are given to the gate of each switching element of the inverter circuit 23. Each switching element is turned on / off by the six types of PWM signals. As a result, the U-phase, V-phase, and W-phase voltages are output from the inverter circuit 23 and applied to the motor 4.
  • the triangular wave comparison method is used in the first embodiment, but the voltage of each phase is output by using other methods such as the space vector method, not limited to the triangular wave comparison method. You may.
  • the PWM circuit 44 generates an interrupt signal Si at a predetermined timing in the second period B of the PWM cycle and gives it to the interrupt controller 45.
  • the PWM circuit 44 inputs the interrupt signal Si to the interrupt controller 45 at the timing when the PWM signal U rises, and inputs the interrupt signal Si to the interrupt controller 45 at the timing when the PWM signal V rises.
  • the interrupt controller 45 receives the interrupt signal Si from the PWM circuit 44 and gives an A / D conversion command to the current detection unit 27. For example, each time the interrupt signal Si is input, the interrupt controller 45 gives an A / D conversion command to the current detection unit 27 after a predetermined time has elapsed after receiving the interrupt signal Si. As a result, the current detection unit 27 performs A / D conversion of the detection signal Sd according to the switching of the signal level of the PWM signal of the specific phase in the second period B.
  • FIG. 5 is a diagram for explaining the principle of generating a PWM signal by the motor control device 100 according to the present embodiment.
  • the threshold switching units 42U, 42V, 42W select fixed thresholds Udu1, Vdu1, Wdu1 as initial values, and the comparator 43U is set as the thresholds Udux, Vdux, Wdux. , 43V, 43W, respectively.
  • the comparators 43U, 43V, 43W compare the carrier C1 with the fixed threshold values Udu1, Vdu1, Wdu1.
  • the comparator 43U inverts the logical level of the output signal Cpu (for example, switching from the low level to the high level).
  • the PWM circuit 44 switches the U-phase PWM signal U from the high level to the low level, and the threshold switching unit 42U selects the fixed threshold value Udu2 and gives it to the comparator 43U as the threshold value Udux.
  • the comparator 43V inverts the logical level of the output signal Cpv (for example, switching from the low level to the high level).
  • the PWM circuit 44 switches the U-phase PWM signal V from the high level to the low level, and the threshold switching unit 42V selects the fixed threshold Vdu2 and gives it to the comparator 43V as the threshold Vdux.
  • the comparator 43W inverts the logical level of the output signal Cpw (for example, switching from the low level to the high level).
  • the PWM circuit 44 switches the W-phase PWM signal W from the high level to the low level, and the threshold switching unit 42W selects the fixed threshold value Wdu2 and gives it to the comparator 43W as the threshold value Wdux.
  • the comparator 43V inverts the logical level of the output signal Cpv (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the V-phase PWM signal V from the low level to the high level.
  • the comparator 43W inverts the logical level of the output signal Cpw (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the W-phase PWM signal W from the low level to the high level.
  • the switching control unit 15 switches the control signal Sc from the low level to the high level.
  • the threshold switching units 42U, 42V, and 42W select variable thresholds Udu3, Vdu3, and Wdu3 according to the high-level control signal Sc, and give them to the comparators 43U, 43V, and 43W as thresholds Udux, Vdux, and Wdux, respectively.
  • the comparators 43U, 43V, 43W compare the carrier C2 with the variable threshold values Udu3, Vdu3, Wdu3.
  • the comparator 43U inverts the logical level of the output signal Cpu (for example, switching from a high level to a low level).
  • the PWM circuit 44 switches the U-phase PWM signal U from the high level to the low level, and the threshold switching unit 42U selects the variable threshold value Udu4 and gives it to the comparator 43U as the threshold value Udux.
  • the comparator 43V inverts the logical level of the output signal Cpv (for example, switching from the low level to the high level).
  • the PWM circuit 44 switches the V-phase PWM signal V from the high level to the low level, and the threshold switching unit 42V selects the variable threshold Vdu4 and gives it to the comparator 43V as the threshold Vdux.
  • the comparator 43W inverts the logical level of the output signal Cpw (for example, switching from the low level to the high level).
  • the PWM circuit 44 switches the W-phase PWM signal W from the high level to the low level, and the threshold switching unit 42W selects the variable threshold value Wdu4 and gives it to the comparator 43W as the threshold value Wdux.
  • the comparator 43U inverts the logical level of the output signal Cpu (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the U-phase PWM signal U from low level to high level.
  • the comparator 43V inverts the logical level of the output signal Cpv (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the V-phase PWM signal W from the low level to the high level.
  • the comparator 43W inverts the logical level of the output signal Cpw (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the W-phase PWM signal W from the low level to the high level.
  • the switching control unit 15 switches the control signal Sc from the high level to the low level.
  • the threshold switching units 42U, 42V, and 42W select fixed thresholds Udu1, Vdu1, and Wdu1 according to the low-level control signal Sc, and output them as thresholds Udux, Vdux, and Wdux, respectively.
  • the PWM signals of each phase are repeatedly generated by the same processing as from time t0 to t12.
  • the PWM signals of each phase are generated, so that the energized sections T12, T23, T34, and T45 are generated in the zero vector section Tz.
  • reference numeral 501 indicates the current of the motor 4 when the energized sections T12, T23, T34, and T45 are generated in the zero vector section Tz of the PWM signal generated by the motor control device 100 according to the present embodiment.
  • the waveform is shown, and reference numeral 502 shows the waveform of the current of the motor 4 when the energization period does not occur in the zero vector section.
  • the motor is provided in the period from time t1 to time t5 as shown by reference numeral 501.
  • the current increases.
  • the current of the motor 4 at the end of the zero vector section Tz at time t7 becomes larger than that in the case where the energization section is not provided in the zero vector section Tz of the PWM signals U, V, W.
  • the amount of change in the current from the start time to the end time of the zero vector section Tz is smaller than that when the energization section is not provided in the zero vector section Tz of the PWM signals U, V, W, so that a large current It is possible to prevent the occurrence of ripple.
  • the energized sections T12, T23, T34, and T45 are generated in the zero vector section Tz of the PWM signals U, V, W, and a plurality of small current ripples are generated in the zero vector section to generate a large current ripple. Can be suppressed.
  • FIG. 6 is a flowchart showing the flow of the motor drive control process by the motor control device 100 according to the embodiment.
  • the motor control device 100 starts the drive control of the motor 4.
  • the motor control device 100 starts a process of generating an energization pattern for driving the motor 4 (step S10).
  • the duty ratio setting unit 39 sets the initial values of the U-phase, V-phase, and W-phase duty ratios Udu, Vdu, and Wdu
  • the carrier generation unit 37 generates carriers C1 and C2, and PWM.
  • the signal generation unit 32 generates 6 types of PWM signals that specify the energization pattern of the motor 4 by the above-mentioned method based on the carriers C1 and C2 and the duty ratios Udu, Vdu, and Wdu set as initial values. , Give to the motor 4.
  • the motor control device 100 measures the phase currents Iu, Iv, and Iw of each of the U, V, and W phases (step S11).
  • the vector control unit 30 performs current control such as PI control based on the current calculation values of the three-phase currents Iu, Iv, and Iw detected by the current detection unit 27 in step S11 (step S12).
  • the phase voltage commands Vu *, Vv *, and Vw * (control amount) of the phase are calculated (step S13).
  • the duty ratio setting unit 39 updates the duty ratio of each phase based on the phase voltage commands Vu *, Vv *, Vw * of each phase calculated in step S13 (step S14). Specifically, the duty ratio setting unit 39 calculates the duty ratios Udu, Vdu, Wdu based on the phase voltage commands Vu *, Vv *, Vw *, and the variable threshold value calculation unit 41 calculates the calculated duty ratio Udu. , Vdu, Wdu, and the variable thresholds Udu3, Udu4, Vdu3, Vdu4, Wdu3, Wdu4 are updated by the above-mentioned method.
  • the PWM signal generation unit 32 has a fixed threshold value Udu1, Udu2, Vdu1, Vdu2, Wdu1, Wdu2 and a variable threshold value Udu3, Udu4, Vdu3, Vdu4, Wdu3, Wdu4 corresponding to the updated duty ratio by the method described above. Based on the above, PWM signals U, V, and W are generated by the above-mentioned method (see FIG. 5) (step S15).
  • the motor control device 100 determines whether or not a motor stop command has been input from the host device (step S16). When the motor stop command is input, the motor control device 100 stops the generation of the PWM signal and stops the driving of the motor 4.
  • step S11 the motor control device 100 proceeds to step S11 and repeatedly executes the above processes (S11 to S16) until the motor stop command is input.
  • the motor control device 100 is a motor within the zero vector section when a zero vector section in which the signal levels of the PWM signals U, V, and W corresponding to each phase of the motor 4 match is generated.
  • the energization section of 4 is provided. According to this, as described above, it is possible to generate a plurality of small current ripples in the zero vector interval and suppress the generation of large current ripples, so that the operation of the motor due to the periodic change of large current ripples. It is possible to suppress the noise of time.
  • the motor control device 100 generates an energized section of the motor 4 by inverting the PWM signals U, V, W of each phase at different timings for the same time in the zero vector section (see FIG. 5). .. According to this, by generating an energized section in the zero vector section, it is possible to prevent each voltage of the U phase, the V phase, and the W phase from becoming a voltage different from the voltage command, and it is input from the host device. It is possible to prevent the generation of noise due to a large current ripple while realizing appropriate control of the motor 4 based on the rotation speed command ⁇ ref.
  • the motor control device 100 inverts the PWM signals U, V, and W of each phase at different timings for a certain period of time in the first period A of the PWM cycle, and sets them in the remaining second period B of the PWM cycle.
  • the PWM signals U, V, and W are inverted based on the calculated duty ratio.
  • the duty ratio is set so that the PWM cycle rotates the motor based on the first period A for generating the energized section in the zero vector section and the command (rotation speed command ⁇ ref) from the host device. Since it is divided into the second period B for adjustment, while adjusting the duty ratio of the PWM signals U, V, W of each phase so that the motor 4 rotates at the rotation speed according to the rotation speed command ⁇ ref. ,
  • the PWM signal can be easily generated so that the energized section of the motor 4 is provided in the zero vector section.
  • the motor control device 100 generates a saw-like carrier C1 having a period corresponding to the first period A and a saw-like carrier C2 having a period corresponding to the second period B, and has fixed threshold values Udu1 and Udu2.
  • Vdu1, Vdu2, Wdu1, Wdu2 and the carrier C1 level are compared with each other to determine the timing at which the PWM signals U, V, W of each phase in the first period A are inverted, and the calculated duty ratio is calculated. Timing at which the PWM signals U, V, W of each phase in the second period B are inverted based on the comparison result between the variable threshold values Udu3, Udu4, Vdu3, Vdu4, Wdu3, Wdu4 and the carrier C2 level set based on the above. To determine.
  • the threshold value of the comparison target is changed for each carrier, and the signal level of the PWM signal is inverted at an appropriate timing in each of the first period A and the second period B to obtain a desired PWM signal. It can be easily generated.
  • the first period A is provided in the first half and the second period B is provided in the second half of the PWM cycle is illustrated, but the present invention is not limited to this, and the second period B is provided in the first half of the PWM cycle.
  • the first period A may be provided in the latter half of the PWM cycle.
  • the above-mentioned flowchart shows an example for explaining the operation, and is not limited to this. That is, the steps shown in each figure of the flowchart are specific examples, and are not limited to this flow. For example, the order of some processes may be changed, other processes may be inserted between each process, and some processes may be performed in parallel.
  • Carrier generation Unit 39 ... duty ratio setting unit, 40 ... fixed threshold storage unit, 41 ... variable threshold calculation unit, 42U, 42V, 42W ... threshold switching unit, 43U, 43V, 43W ... comparer, 44 ... PWM circuit, 45 ... interrupt Controller, 100 ... Motor control device, A ... 1st period, B ... 2nd period, C, C1, C2 ... Carrier, CLK ... Clock, Cp ... Detection signal, Lu ... U phase coil, Lv ... V phase coil, Lw ... W phase coil, Sc ... control signal, Sd ... detection signal, Si ... interrupt signal, Cpu, Cpv, Cpw ... output signal, T1 ... first upper limit value, T2 ...
  • Udu, Vdu, Wdu duty Ratio, Udu1, Vdu1, Wdu1, Udu2, Vdu2, Wdu2 ... Fixed threshold, Udu3, Vdu3, Wdu3, Udu4, Vdu4, Wdu4 ... Variable threshold, UH, UL, VH, VL, WH, WL, U, V, W ... PWM signal.

Abstract

A motor control device capable of reducing noise is provided. A motor control device (100) is characterized by comprising: a control unit (20) that generates a respective PWM signal (U, V, W) for each phase (U, V, W) of a motor (4) having coils (Lu, Lv, Lw) in a plurality of phases; and an inverter circuit (23) that drives the coils in the phases on the basis of the PWM signals. The motor control device is also characterized in that, if there arises a zero-vector interval (Tz) in which the PWM signals of the phases are at the same signal level, the control unit produces within the zero-vector interval an energizing interval (Te) in which the coils in the phases are energized.

Description

モータ制御装置およびモータシステムMotor controller and motor system
　本発明は、モータ制御装置およびモータシステムに関する。 The present invention relates to a motor control device and a motor system.
　従来、３相モータ用のモータ制御装置は、Ｕ，Ｖ，Ｗ各相に対応するＰＷＭ（Ｐｕｌｓｅ　Ｗｉｄｔｈ　Ｍｏｄｕｌａｔｉｏｎ，パルス幅変調）信号を用いて各相のコイルを通電させることにより、モータの駆動を制御している（特許文献１参照）。 Conventionally, a motor control device for a three-phase motor drives a motor by energizing a coil of each phase using a PWM (Pulse Width Modulation, pulse width modulation) signal corresponding to each of the U, V, and W phases. It is controlled (see Patent Document 1).
特開２０１５－８４６３２号公報JP-A-2015-84632
　上述した３相モータの制御において、Ｕ，Ｖ，Ｗ相のそれぞれのＰＷＭ信号がハイレベルまたはローベルとなるゼロベクトル区間では、各相のコイルに電流が流れない。 In the control of the three-phase motor described above, no current flows through the coils of each phase in the zero vector section where the PWM signals of the U, V, and W phases are high level or low bell.
　３相モータの制御中に、ゼロベクトル区間から、各相のコイルに電流が流れる通電区間へと切り替わったとき、モータの電流が急激に変化（上昇）するため、使用アプリケーションによっては電流リップルが大きくなる。その電流リップルの周期的な変化は、モータの動作時の騒音となり、モータを適用するアプリケーションによっては、ユーザに不快感を与えるという課題がある。以下、この課題について、図を用いて詳細に説明する。 When switching from the zero vector section to the energized section where current flows through the coils of each phase during control of the three-phase motor, the motor current changes (rises) rapidly, so the current ripple is large depending on the application used. Become. The periodic change of the current ripple causes noise during the operation of the motor, and there is a problem that the user is uncomfortable depending on the application to which the motor is applied. Hereinafter, this problem will be described in detail with reference to figures.
　図７は、従来のモータ制御装置によって生成されるＵ相、Ｖ相、およびＷ相に対応するＰＷＭ信号Ｕ，Ｖ，Ｗの１周期の波形と、ＰＷＭ周期を定めるＰＷＭキャリア（単に、「キャリア」とも称する。）と、モータの電流の波形の一例が示されている。 FIG. 7 shows a waveform of one cycle of PWM signals U, V, W corresponding to the U phase, V phase, and W phase generated by a conventional motor control device, and a PWM carrier that determines the PWM cycle (simply, “carrier”. An example of the waveform of the current of the motor is shown.
　図７に示すように、例えば、時刻ｔ０においてＵ相、Ｖ相、Ｗ相のＰＷＭ信号が全てハイレベルとなり、ゼロベクトル区間Ｔｚに移行すると、モータの電流Ｉがゼロに向かって減少する。その後、時刻ｔ１において、Ｕ相のＰＷＭ信号がローレベルになると、電流Ｉが急激に増加し、大きな電流リップルが発生する。この電流リップルは、モータ制御におけるゼロベクトルの最適化により、ＰＷＭ信号の１周期に対するゼロベクトル区間（通電停止期間）Ｔｚの割合が大きくなるほど、大きくなる。このような大きな電流リップルの周期的変化は、騒音の原因となる。 As shown in FIG. 7, for example, at time t0, the PWM signals of the U phase, the V phase, and the W phase all become high levels, and when shifting to the zero vector section Tz, the current I of the motor decreases toward zero. After that, when the U-phase PWM signal becomes low level at time t1, the current I rapidly increases and a large current ripple occurs. This current ripple increases as the ratio of the zero vector interval (energization stop period) Tz to one cycle of the PWM signal increases due to the optimization of the zero vector in the motor control. Periodic changes in such large current ripples cause noise.
　本発明は、上記に鑑みてなされたものであり、騒音を抑制可能なモータ制御装置を提供することを目的とする。 The present invention has been made in view of the above, and an object of the present invention is to provide a motor control device capable of suppressing noise.
　本発明の代表的な実施の形態に係るモータ制御装置は、複数相のコイルを有するモータの各相にそれぞれ対応するＰＷＭ信号を生成する制御部と、前記ＰＷＭ信号に基づいて、各相の前記コイルを駆動するインバータ回路と、を備え、前記制御部は、各相の前記ＰＷＭ信号の信号レベルが一致するゼロベクトル区間が発生する場合に、前記ゼロベクトル区間内に各相の前記コイルを通電させる通電区間を発生させることを特徴とする。 The motor control device according to a typical embodiment of the present invention includes a control unit that generates a PWM signal corresponding to each phase of a motor having a plurality of phases of coils, and a control unit for each phase based on the PWM signal. The control unit includes an inverter circuit for driving a coil, and when a zero vector section in which the signal levels of the PWM signals of each phase match occurs, the control unit energizes the coil of each phase in the zero vector section. It is characterized in that an energized section is generated.
　本発明に係るモータ制御装置によれば、騒音を抑制することが可能となる。 According to the motor control device according to the present invention, it is possible to suppress noise.
実施の形態に係るモータシステムの構成例を示す図である。It is a figure which shows the structural example of the motor system which concerns on embodiment. 本実施の形態に係るＰＷＭ信号の生成方法の概要を説明するための図である。It is a figure for demonstrating the outline of the PWM signal generation method which concerns on this Embodiment. 実施の形態に係るモータ制御装置におけるキャリア発生部及びＰＷＭ信号生成部の構成例を示す図である。It is a figure which shows the structural example of the carrier generation part and the PWM signal generation part in the motor control device which concerns on embodiment. キャリアＣ１，Ｃ２の生成原理を説明するための図である。It is a figure for demonstrating the generation principle of carriers C1 and C2. ＰＷＭ信号の生成原理を説明するための図である。It is a figure for demonstrating the generation principle of a PWM signal. 実施の形態に係るモータ制御装置によるモータ駆動制御処理の流れを示すフローチャートである。It is a flowchart which shows the flow of the motor drive control processing by the motor control device which concerns on embodiment. 従来のモータ制御装置によって生成されるＵ相、Ｖ相、およびＷ相に対応するＰＷＭ信号の１周期の波形と、ＰＷＭ周期を定めるＰＷＭキャリアと、モータの電流の波形の一例を示す図である。It is a figure which shows an example of the waveform of one cycle of the PWM signal corresponding to U phase, V phase, and W phase generated by the conventional motor control device, the PWM carrier which determines the PWM cycle, and the waveform of the current of a motor. ..
１．実施の形態の概要
　先ず、本願において開示される発明の代表的な実施の形態について概要を説明する。なお、以下の説明では、一例として、発明の構成要素に対応する図面上の参照符号を、括弧を付して記載している。 1. 1. Outline of Embodiment First, an outline of a typical embodiment of the invention disclosed in the present application will be described. In the following description, as an example, reference numerals on drawings corresponding to the components of the invention are described in parentheses.
　〔１〕本発明の代表的な実施の形態に係るモータ制御装置（１００）は、複数相のコイル（Ｌｕ，Ｌｖ，Ｌｗ）を有するモータ（４）の各相（Ｕ，Ｖ，Ｗ）にそれぞれ対応するＰＷＭ信号（Ｕ，Ｖ，Ｗ，ＵＨ，ＵＬ，ＶＨ，ＶＬ，ＷＨ，ＷＬ）を生成する制御部（２０）と、前記ＰＷＭ信号に基づいて、各相の前記コイルを駆動するインバータ回路（２３）と、を備え、前記制御部は、各相の前記ＰＷＭ信号の信号レベルが一致するゼロベクトル区間（Ｔｚ）が発生する場合に、前記ゼロベクトル区間内に各相の前記コイルを通電させる通電区間（Ｔｅ）を発生させることを特徴とする。 [1] The motor control device (100) according to a typical embodiment of the present invention is applied to each phase (U, V, W) of the motor (4) having a multi-phase coil (Lu, Lv, Lw). A control unit (20) that generates PWM signals (U, V, W, UH, UL, VH, VL, WH, WL) corresponding to each, and an inverter that drives the coil of each phase based on the PWM signal. The control unit includes the circuit (23), and when a zero vector section (Tz) in which the signal levels of the PWM signals of each phase match is generated, the control unit sets the coil of each phase in the zero vector section. It is characterized in that an energization section (Te) to be energized is generated.
　〔２〕上記〔１〕に記載のモータ制御装置において、前記制御部は、前記ゼロベクトル区間において各相の前記ＰＷＭ信号を同じ時間（Ｔｅ）だけ、互いに異なるタイミングで反転させてもよい。 [2] In the motor control device according to the above [1], the control unit may invert the PWM signals of each phase in the zero vector section for the same time (Te) at different timings.
　〔３〕上記〔２〕に記載のモータ制御装置において、前記制御部は、各相の前記ＰＷＭ信号のデューティ比を設定するデューティ比設定部（３９）と、前記デューティ比設定部によって設定された前記デューティ比に基づいて、各相の前記ＰＷＭ信号を生成するＰＷＭ信号生成部（３２）と、を有し、各相の前記ＰＷＭ信号の１周期は、第１期間（Ａ）と残りの第２期間（Ｂ）とを含み、前記ＰＷＭ信号生成部は、前記第１期間において、各相の前記ＰＷＭ信号を一定時間、互いに異なるタイミングで反転させ、前記第２期間において、前記デューティ比に基づいて前記ＰＷＭ信号を反転させてもよい。 [3] In the motor control device according to the above [2], the control unit is set by a duty ratio setting unit (39) for setting the duty ratio of the PWM signal of each phase and the duty ratio setting unit. It has a PWM signal generation unit (32) that generates the PWM signal of each phase based on the duty ratio, and one cycle of the PWM signal of each phase is the first period (A) and the remaining thirst. Including the two periods (B), the PWM signal generation unit inverts the PWM signals of each phase at different timings for a certain period of time in the first period, and is based on the duty ratio in the second period. The PWM signal may be inverted.
　〔４〕上記〔３〕に記載のモータ制御装置において、前記制御部は、前記第１期間に対応する周期を有するのこぎり波状の第１キャリア（Ｃ１）と、前記第２期間に対応する周期を有するのこぎり波状の第２キャリア（Ｃ２）とを生成するキャリア発生部（３７）を更に有し、前記ＰＷＭ信号生成部は、固定値である第１閾値（Ｕｄｕ１，Ｖｄｕ１，Ｗｄｕ１）および第２閾値（Ｕｄｕ２，Ｖｄｕ２，Ｗｄｕ２）と前記第１キャリアのレベルとの比較結果に基づいて、前記第１期間における各相の前記ＰＷＭ信号が反転するタイミングを決定し、前記デューティ比に基づいて設定された第３閾値（Ｕｄｕ３，Ｖｄｕ３，Ｗｄｕ３）および第４閾値（Ｕｄｕ４，Ｖｄｕ４，Ｗｄｕ４）と前記第２キャリアのレベルとの比較結果に基づいて、前記第２期間における各相の前記ＰＷＭ信号が反転するタイミングを決定してもよい。 [4] In the motor control device according to the above [3], the control unit has a sawtooth-shaped first carrier (C1) having a period corresponding to the first period and a period corresponding to the second period. It further has a carrier generation unit (37) that generates a saw-like second carrier (C2), and the PWM signal generation unit has a fixed first threshold value (Udu1, Vdu1, Wdu1) and a second threshold value. Based on the result of comparison between (Udu2, Vdu2, Wdu2) and the level of the first carrier, the timing at which the PWM signal of each phase in the first period is inverted was determined and set based on the duty ratio. Based on the comparison result between the third threshold value (Udu3, Vdu3, Wdu3) and the fourth threshold value (Udu4, Vdu4, Wdu4) and the level of the second carrier, the PWM signal of each phase in the second period is inverted. The timing may be determined.
　〔５〕本発明の代表的な実施の形態に係るモータシステム（１）は、〔１〕乃至〔４〕の何れか一つに記載のモータ制御装置（１００）と、モータ（４）とを備えることを特徴とする。 [5] The motor system (1) according to a typical embodiment of the present invention includes the motor control device (100) and the motor (4) according to any one of [1] to [4]. It is characterized by being prepared.
２．実施の形態の具体例
　以下、本発明の実施の形態の具体例について図を参照して説明する。なお、以下の説明において、各実施の形態において共通する構成要素には同一の参照符号を付し、繰り返しの説明を省略する。 2. 2. Specific Examples of Embodiments Hereinafter, specific examples of embodiments of the present invention will be described with reference to the drawings. In the following description, the same reference numerals will be given to the components common to each embodiment, and repeated description will be omitted.
　図１は、一実施の形態に係るモータシステムの構成例を示す図である。
　図１に示されるモータシステム１は、モータ４の回転動作を制御する。モータシステム１が搭載される機器は、例えば、コピー機、パーソナルコンピュータ、冷蔵庫等であるが、当該機器は、これらに限られない。モータシステム１は、モータ４と、モータ制御装置１００とを少なくとも備える。 FIG. 1 is a diagram showing a configuration example of a motor system according to an embodiment.
The motor system 1 shown in FIG. 1 controls the rotational operation of the motor 4. The equipment on which the motor system 1 is mounted is, for example, a copier, a personal computer, a refrigerator, and the like, but the equipment is not limited thereto. The motor system 1 includes at least a motor 4 and a motor control device 100.
　モータ４は、複数のコイルを有する。モータ４は、例えば、Ｕ相コイルＬｕと、Ｖ相コイルＬｖと、Ｗ相コイルＬｗとを含む３相コイルを有する。モータ４の具体例として、３相のブラシレスモータなどが挙げられる。Ｕ相コイルＬｕと、Ｖ相コイルＬｖと、Ｗ相コイルＬｗとは、例えば、スター結線により互いに接続されている。 The motor 4 has a plurality of coils. The motor 4 has, for example, a three-phase coil including a U-phase coil Lu, a V-phase coil Lv, and a W-phase coil Lw. Specific examples of the motor 4 include a three-phase brushless motor. The U-phase coil Lu, the V-phase coil Lv, and the W-phase coil Lw are connected to each other by, for example, a star connection.
　モータ制御装置１００は、３相ブリッジ接続された複数のスイッチング素子を３相のＰＷＭ信号を含む通電パターンに従いオン／オフ（ＯＮ／ＯＦＦ）制御することで、直流を３相交流に変換してモータを駆動する。 The motor control device 100 converts DC into three-phase AC by controlling ON / OFF of a plurality of switching elements connected by a three-phase bridge according to an energization pattern including a three-phase PWM signal. To drive.
　具体的に、モータ制御装置１００は、インバータ回路２３、制御部２０、および電流検出器２４を備える。 Specifically, the motor control device 100 includes an inverter circuit 23, a control unit 20, and a current detector 24.
　インバータ回路２３は、直流電源２１から供給される直流電力を複数のスイッチング素子のスイッチングによって３相交流に変換し、３相交流の駆動電流をモータ４に流すことによって、モータ４のロータを回転させる回路である。インバータ回路２３は、後述する通電パターン生成部３５によって生成される複数の通電パターン（より具体的には、通電パターン生成部３５内のＰＷＭ信号生成部３２によって生成される３相のＰＷＭ信号）に基づいて、モータ４を駆動する。 The inverter circuit 23 converts the DC power supplied from the DC power supply 21 into three-phase AC by switching a plurality of switching elements, and causes the motor 4 to rotate the rotor of the motor 4 by passing the drive current of the three-phase AC to the motor 4. It is a circuit. The inverter circuit 23 is applied to a plurality of energization patterns generated by the energization pattern generation unit 35 described later (more specifically, a three-phase PWM signal generated by the PWM signal generation unit 32 in the energization pattern generation unit 35). Based on this, the motor 4 is driven.
　インバータ回路２３は、３相ブリッジ接続された複数のスイッチング素子２５Ｕ＋，２５Ｖ＋，２５Ｗ＋，２５Ｕ－，２５Ｖ－，２５Ｗ－を有する。スイッチング素子２５Ｕ＋，２５Ｖ＋，２５Ｗ＋は、それぞれ、直流電源２１の正極側に正側母線２２ａを介して接続されるハイサイドスイッチング素子（上アーム）である。スイッチング素子２５Ｕ－，２５Ｖ－，２５Ｗ－は、それぞれ、直流電源２１の負極側（具体的には、グランド側）に接続されるローサイドスイッチング素子（下アーム）である。複数のスイッチング素子２５Ｕ＋，２５Ｖ＋，２５Ｗ＋，２５Ｕ－，２５Ｖ－，２５Ｗ－は、それぞれ、上述の通電パターンに含まれるＰＷＭ信号に基づいて駆動回路３３から供給される複数の駆動信号のうち、対応する駆動信号に従って、オン又はオフとなる。以下では、複数のスイッチング素子２５Ｕ＋，２５Ｖ＋，２５Ｗ＋，２５Ｕ－，２５Ｖ－，２５Ｗ－を、特に区別しない場合には、単にスイッチング素子と称する場合がある。 The inverter circuit 23 has a plurality of switching elements 25U +, 25V +, 25W +, 25U−, 25V−, 25W− connected by a three-phase bridge. The switching elements 25U +, 25V +, and 25W + are high-side switching elements (upper arms) connected to the positive electrode side of the DC power supply 21 via the positive bus 22a, respectively. The switching elements 25U-, 25V-, and 25W- are low-side switching elements (lower arms) connected to the negative electrode side (specifically, the ground side) of the DC power supply 21, respectively. The plurality of switching elements 25U +, 25V +, 25W +, 25U-, 25V-, and 25W- correspond to each of the plurality of drive signals supplied from the drive circuit 33 based on the PWM signals included in the above-mentioned energization pattern. It turns on or off according to the drive signal. Hereinafter, a plurality of switching elements 25U +, 25V +, 25W +, 25U−, 25V−, 25W− may be simply referred to as switching elements unless otherwise specified.
　スイッチング素子２５Ｕ＋とスイッチング素子２５Ｕ－との接続点は、モータ４のＵ相コイルの一端に接続される。スイッチング素子２５Ｖ＋とスイッチング素子２５Ｖ－との接続点は、モータ４のＶ相コイルの一端に接続される。スイッチング素子２５Ｗ＋とスイッチング素子２５Ｗ－との接続点は、モータ４のＷ相コイルの一端に接続される。Ｕ相コイルとＶ相コイルとＷ相コイルとのそれぞれの他端は、互いに接続されている。 The connection point between the switching element 25U + and the switching element 25U- is connected to one end of the U-phase coil of the motor 4. The connection point between the switching element 25V + and the switching element 25V- is connected to one end of the V-phase coil of the motor 4. The connection point between the switching element 25W + and the switching element 25W− is connected to one end of the W-phase coil of the motor 4. The other ends of the U-phase coil, the V-phase coil, and the W-phase coil are connected to each other.
　スイッチング素子の具体例として、Ｎチャネル型のＭＯＳＦＥＴ（Ｍｅｔａｌ　Ｏｘｉｄｅ　Ｓｅｍｉｃｏｎｄｕｃｔｏｒ　Ｆｉｅｌｄ　Ｅｆｆｅｃｔ　Ｔｒａｎｓｉｓｔｏｒ）やＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ　Ｇａｔｅ　Ｂｉｐｏｌａｒ　Ｔｒａｎｓｉｓｔｏｒ）などが挙げられる。しかしながら、スイッチング素子は、これらに限られない。 Specific examples of the switching element include an N-channel MOSFET (Metal Oxide Semiconductor Field Transistor) and an IGBT (Insulated Gate Bipolar Transistor). However, the switching element is not limited to these.
　電流検出器２４は、インバータ回路２３の直流側に流れる電流の電流値に対応する検出信号Ｓｄを出力する。図１に示される電流検出器２４は、負側母線２２ｂに流れる電流の電流値に対応する検出信号Ｓｄを発生させる。電流検出器２４は、例えば、負側母線２２ｂに配置される電流検出素子であり、より具体的には、負側母線２２ｂに挿入される抵抗（シャント抵抗）である。シャント抵抗等の電流検出素子は、自身に流れる電流の電流値に対応する電圧信号を検出信号Ｓｄとして発生する。なお、電流検出器２４は、負側母線２２ｂに流れる電流の電流値に対応する検出信号を出力するものであればよく、ＣＴ（Ｃｕｒｒｅｎｔ　Ｔｒａｎｓｆｏｒｍｅｒ）等のセンサでもよい。 The current detector 24 outputs a detection signal Sd corresponding to the current value of the current flowing on the DC side of the inverter circuit 23. The current detector 24 shown in FIG. 1 generates a detection signal Sd corresponding to the current value of the current flowing through the negative bus 22b. The current detector 24 is, for example, a current detection element arranged on the negative bus 22b, and more specifically, a resistor (shunt resistance) inserted into the negative bus 22b. A current detection element such as a shunt resistor generates a voltage signal corresponding to the current value of the current flowing through it as a detection signal Sd. The current detector 24 may be a sensor such as a CT (Current Transformer) as long as it outputs a detection signal corresponding to the current value of the current flowing through the negative bus 22b.
　制御部２０は、モータ４の各相に対応する複数のＰＷＭ信号を生成する。
　制御部２０は、例えば、ＣＰＵ等のプロセッサと、ＲＡＭ，ＲＯＭ等の各種記憶装置と、カウンタ（タイマ）、Ａ／Ｄ変換回路、Ｄ／Ａ変換回路、および入出力Ｉ／Ｆ回路等の周辺回路とがバスを介して互いに接続された構成を有するプログラム処理装置（例えば、マイクロコントローラ）である。本実施の形態において、制御部２０は、ＩＣ（集積回路）としてパッケージ化されているが、これに限られない。 The control unit 20 generates a plurality of PWM signals corresponding to each phase of the motor 4.
The control unit 20 includes, for example, a processor such as a CPU, various storage devices such as RAM and ROM, and peripherals such as a counter (timer), an A / D conversion circuit, a D / A conversion circuit, and an input / output I / F circuit. It is a program processing device (for example, a microcontroller) having a configuration in which circuits are connected to each other via a bus. In the present embodiment, the control unit 20 is packaged as an IC (integrated circuit), but the present invention is not limited to this.
　制御部２０は、例えば、上位装置（図示せず）から入力されたモータ４の回転速度指令ωｒｅｆと、電流検出器２４の検出信号Ｓｄに基づくモータ４の各相の相電流とに基づいて、モータ４が適切に動作するように、ＰＷＭ信号を生成する。 The control unit 20 is based on, for example, the rotation speed command ωref of the motor 4 input from the host device (not shown) and the phase current of each phase of the motor 4 based on the detection signal Sd of the current detector 24. A PWM signal is generated so that the motor 4 operates properly.
　上述したように、３相モータの制御中に、Ｕ，Ｖ，Ｗ相のそれぞれのＰＷＭ信号がハイレベルまたはローベルとなるゼロベクトル区間（通電停止区間）から各相のコイルに電流が流れる通電区間へと切り替わったとき、大きな電流リップルが発生し、モータの動作時の騒音の原因となる（図７参照）。 As described above, during the control of the three-phase motor, the current flow section from the zero vector section (energization stop section) where the PWM signals of the U, V, and W phases are high level or low bell to the coil of each phase. When switching to, a large current ripple is generated, which causes noise during motor operation (see FIG. 7).
　そこで、本実施の形態に係るモータ制御装置１００は、ゼロベクトル区間から通電区間へ切り替わるときの大きな電流リップルの発生を防止するために、ゼロベクトル区間に各相のコイルを通電させる通電区間が発生するようにＰＷＭ信号を生成する。 Therefore, in the motor control device 100 according to the present embodiment, in order to prevent the generation of a large current ripple when switching from the zero vector section to the energized section, an energized section for energizing the coils of each phase is generated in the zero vector section. A PWM signal is generated so as to be performed.
　図２は、本実施の形態に係るＰＷＭ信号の生成方法の概要を説明するための図である。
　図２には、本実施の形態に係るモータ制御装置１００によって生成されるＵ相、Ｖ相、およびＷ相に対応するＰＷＭ信号Ｕ，Ｖ，Ｗの１周期の波形と、モータの電流の波形とが示されている。 FIG. 2 is a diagram for explaining an outline of a method for generating a PWM signal according to the present embodiment.
FIG. 2 shows a waveform of one cycle of PWM signals U, V, W corresponding to the U phase, V phase, and W phase generated by the motor control device 100 according to the present embodiment, and a waveform of the motor current. Is shown.
　図２に示すように、モータ制御装置１００では、ＰＷＭ周期を、ゼロベクトル区間内に通電区間を発生させるための第１期間Ａと、上位装置からの指令（回転速度指令ωｒｅｆ）に基づいてモータが回転するようにデューティ比を調整するための第２期間Ｂとに分ける。
　同図に示すように、第１期間Ａと第２期間Ｂとは、２種類のキャリアＣ１，Ｃ２によって定められる。 As shown in FIG. 2, in the motor control device 100, the PWM cycle is set by the motor based on the first period A for generating the energized section in the zero vector section and the command (rotational speed command ωref) from the host device. It is divided into a second period B for adjusting the duty ratio so that the motor rotates.
As shown in the figure, the first period A and the second period B are defined by two types of carriers C1 and C2.
　キャリアＣ１は、ＰＷＭ周期における第１期間Ａに対応する周期でレベルが増減する、のこぎり波状のキャリアである。キャリアＣ２は、ＰＷＭ周期における第２期間Ｂに対応する周期でレベルが増減する、のこぎり波状のキャリアである。 Carrier C1 is a saw-like carrier whose level increases or decreases in a cycle corresponding to the first period A in the PWM cycle. The carrier C2 is a saw-like carrier whose level increases or decreases in a cycle corresponding to the second period B in the PWM cycle.
　図２に示すように、キャリアＣ１とキャリアＣ２とは、交互に生成され、連続する一組のキャリアＣ１，Ｃ２によってＰＷＭ信号Ｕ，Ｌ，Ｗの１周期（ＰＷＭ周期）が定められる。 As shown in FIG. 2, carriers C1 and C2 are alternately generated, and one continuous set of carriers C1 and C2 determines one cycle (PWM cycle) of PWM signals U, L, and W.
　ＰＷＭ信号Ｕは、Ｕ相の上下アームを構成する２つのスイッチング素子を駆動するためのＰＷＭ信号である。ＰＷＭ信号Ｕがローレベルのとき、Ｕ相の下アームのスイッチング素子がオン（Ｕ相の上アームのスイッチング素子がオフ）となり、ＰＷＭ信号Ｕがハイレベルのとき、Ｕ相の下アームのスイッチング素子がオフ（Ｕ相の上アームのスイッチング素子がオン）となる。ＰＷＭ信号Ｕのレベルの変化に対して、Ｕ相の上下アームを構成する２つのスイッチング素子は相補的にオンオフ動作する。 The PWM signal U is a PWM signal for driving two switching elements constituting the upper and lower arms of the U phase. When the PWM signal U is at low level, the switching element of the lower arm of U phase is on (the switching element of the upper arm of U phase is off), and when the PWM signal U is at high level, the switching element of the lower arm of U phase is on. Is off (the switching element of the upper arm of the U phase is on). The two switching elements constituting the upper and lower arms of the U phase complementarily operate on and off in response to a change in the level of the PWM signal U.
　ＰＷＭ信号Ｖは、Ｖ相の上下アームを構成する２つのスイッチング素子を駆動するためのＰＷＭ信号である。ＰＷＭ信号Ｖがローレベルのとき、Ｖ相の下アームのスイッチング素子がオン（Ｖ相の上アームのスイッチング素子がオフ）となり、ＰＷＭ信号Ｖがハイレベルのとき、Ｖ相の下アームのスイッチング素子がオフ（Ｖ相の上アームのスイッチング素子がオン）となる。ＰＷＭ信号Ｖのレベルの変化に対して、Ｖ相の上下アームを構成する２つのスイッチング素子は相補的にオンオフ動作する。 The PWM signal V is a PWM signal for driving two switching elements constituting the upper and lower arms of the V phase. When the PWM signal V is low level, the switching element of the lower arm of V phase is on (the switching element of the upper arm of V phase is off), and when the PWM signal V is high level, the switching element of the lower arm of V phase is on. Is off (the switching element of the upper arm of the V phase is on). The two switching elements constituting the upper and lower arms of the V phase complementarily operate on and off in response to a change in the level of the PWM signal V.
　ＰＷＭ信号Ｗは、Ｗ相の上下アームを構成する２つのスイッチング素子を駆動するためのＰＷＭ信号である。ＰＷＭ信号Ｗがローレベルのとき、Ｗ相の下アームのスイッチング素子がオン（Ｗ相の上アームのスイッチング素子がオフ）となり、ＰＷＭ信号Ｗがハイレベルのとき、Ｗ相の下アームのスイッチング素子がオフ（Ｗ相の上アームのスイッチング素子がオン）となる。ＰＷＭ信号Ｗのレベルの変化に対して、Ｗ相の上下アームを構成する２つのスイッチング素子は相補的にオンオフ動作する。 The PWM signal W is a PWM signal for driving two switching elements constituting the upper and lower arms of the W phase. When the PWM signal W is low level, the switching element of the lower arm of W phase is on (the switching element of the upper arm of W phase is off), and when the PWM signal W is high level, the switching element of the lower arm of W phase is on. Is off (the switching element of the upper arm of the W phase is on). The two switching elements constituting the upper and lower arms of the W phase complementarily operate on and off in response to a change in the level of the PWM signal W.
　制御部２０は、第１期間Ａにおいて、所定のタイミングでＰＷＭ信号の信号レベルを反転させてゼロベクトル区間に通電区間を発生させ、第２期間Ｂにおいて、回転速度指令ωｒｅｆと各相の相電流とに基づくベクトル制御によって算出したデューティ比に基づいて各相のＰＷＭ信号の信号レベルを反転させる。 In the first period A, the control unit 20 inverts the signal level of the PWM signal at a predetermined timing to generate an energized section in the zero vector section, and in the second period B, the rotation speed command ωref and the phase current of each phase. The signal level of the PWM signal of each phase is inverted based on the duty ratio calculated by the vector control based on.
　ここで、ゼロベクトル区間に通電区間を設けるためには、少なくとも一つの相のＰＷＭ信号の信号レベルを他の相のＰＷＭ信号の信号レベルと相違させる必要がある。また、ゼロベクトル区間に通電区間を設けることによってＵ相、Ｖ相、Ｗ相の各電圧が電圧指令と異なる電圧になることを防止する必要がある。 Here, in order to provide the energization section in the zero vector section, it is necessary to make the signal level of the PWM signal of at least one phase different from the signal level of the PWM signal of the other phase. Further, it is necessary to prevent the U-phase, V-phase, and W-phase voltages from becoming different from the voltage command by providing the energization section in the zero vector section.
　そこで、制御部２０は、第１期間Ａにおいて、各相のＰＷＭ信号を、一定期間互いに異なるタイミングで反転させることで、通電期間を設ける。具体的には、図２に示すように、ゼロベクトル区間Ｔｚにおいて、各ＰＷＭ信号の信号レベルが反転する区間Ｔｅを同一の長さとし、且つ各ＰＷＭ信号の区間Ｔｅを互いにシフトさせる。例えば、各ＰＷＭ信号Ｕの区間Ｔｅをｔｓ＝Ｔｅ／２ずつシフトさせる。その結果、ゼロベクトル区間Ｔｚでは、モータの電流が低下する期間とモータの電流が増加する期間が混在することになり、小さな電流リップルが複数発生する。これにより、大きな電流リップルの発生を抑制することが可能となる。 Therefore, in the first period A, the control unit 20 provides an energization period by inverting the PWM signals of each phase at different timings for a certain period of time. Specifically, as shown in FIG. 2, in the zero vector section Tz, the section Te in which the signal level of each PWM signal is inverted has the same length, and the section Te of each PWM signal is shifted from each other. For example, the section Te of each PWM signal U is shifted by ts = Te / 2. As a result, in the zero vector section Tz, the period in which the motor current decreases and the period in which the motor current increases are mixed, and a plurality of small current ripples occur. This makes it possible to suppress the occurrence of a large current ripple.
　以下、制御部２０によるＰＷＭ信号を生成するための具体的な構成について説明する。
　図１に示すように、制御部２０は、各相のＰＷＭ信号を生成するための機能ブロックとして、電流検出部２７、電流検出タイミング調整部３４、駆動回路３３、通電パターン生成部３５、クロック発生部３６、およびキャリア発生部３７を有している。 Hereinafter, a specific configuration for generating a PWM signal by the control unit 20 will be described.
As shown in FIG. 1, the control unit 20 includes a current detection unit 27, a current detection timing adjustment unit 34, a drive circuit 33, an energization pattern generation unit 35, and a clock generation as functional blocks for generating PWM signals for each phase. It has a unit 36 and a carrier generation unit 37.
　電流検出部２７は、通電パターン生成部３５によって生成される複数の通電パターン（より具体的には、３相のＰＷＭ信号）に基づいて、検出信号Ｓｄを取得することによって、モータ４に流れるＵ，Ｖ，Ｗ各相の相電流Ｉｕ，Ｉｖ，Ｉｗを検出する。 The current detection unit 27 acquires the detection signal Sd based on a plurality of energization patterns (more specifically, three-phase PWM signals) generated by the energization pattern generation unit 35, so that the U flows through the motor 4. , V, W Phase currents Iu, Iv, Iw of each phase are detected.
　より詳細には、電流検出部２７は、複数の通電パターン（より具体的には、３相のＰＷＭ信号）に同期する取得タイミングで検出信号Ｓｄを取得することによって、モータ４に流れるＵ，Ｖ，Ｗ各相の相電流Ｉｕ，Ｉｖ，Ｉｗを検出する。検出信号Ｓｄの取得タイミングは、電流検出タイミング調整部３４により設定される。 More specifically, the current detection unit 27 acquires the detection signal Sd at the acquisition timing synchronized with the plurality of energization patterns (more specifically, the three-phase PWM signals), so that the U, V flowing through the motor 4 , W The phase currents Iu, Iv, and Iw of each phase are detected. The acquisition timing of the detection signal Sd is set by the current detection timing adjusting unit 34.
　例えば、電流検出部２７は、電流検出器２４で発生するアナログ電圧の検出信号Ｓｄを、電流検出タイミング調整部３４により設定される取得タイミングでＡ／Ｄ（Ａｎａｌｏｇ　ｔｏ　Ｄｉｇｉｔａｌ）変換器に取り込む。当該Ａ／Ｄ変換器は、電流検出部２７に設けられている。そして、電流検出部２７は、取り込んだアナログの検出信号Ｓｄをデジタルの検出信号ＳｄにＡＤ変換し、ＡＤ変換後のデジタルの検出信号Ｓｄをデジタル処理することによって、モータ４のＵ，Ｖ，Ｗ各相の相電流Ｉｕ，Ｉｖ，Ｉｗを計測する。 For example, the current detection unit 27 takes in the detection signal Sd of the analog voltage generated by the current detector 24 into the A / D (Analog to Digital) converter at the acquisition timing set by the current detection timing adjustment unit 34. The A / D converter is provided in the current detection unit 27. Then, the current detection unit 27 AD-converts the captured analog detection signal Sd into a digital detection signal Sd, and digitally processes the digital detection signal Sd after the AD conversion, thereby U, V, W of the motor 4. The phase currents Iu, Iv, and Iw of each phase are measured.
　電流検出部２７により計測された各相の相電流Ｉｕ，Ｉｖ，Ｉｗの計測値は、通電パターン生成部３５に供給される。クロック発生部３６は、内蔵する発振回路により所定周波数のクロックを生成し、生成したクロックをキャリア発生部３７へ出力する。なお、クロック発生部３６は、例えば、モータ制御装置１００の電源が投入されると同時に、動作を開始する。 The measured values of the phase currents Iu, Iv, and Iw of each phase measured by the current detection unit 27 are supplied to the energization pattern generation unit 35. The clock generation unit 36 generates a clock having a predetermined frequency by the built-in oscillation circuit, and outputs the generated clock to the carrier generation unit 37. The clock generation unit 36 starts operation at the same time when the power of the motor control device 100 is turned on, for example.
　通電パターン生成部３５は、電流検出部２７により計測されるモータ４の相電流Ｉｕ，Ｉｖ，Ｉｗの計測値に基づいて、モータ４のロータ位置を決定し、その決定したロータ位置にモータ４のロータが追従するように、インバータ回路２３を通電させるパターン（インバータ回路２３の通電パターン）を指定する信号を生成する。 The energization pattern generation unit 35 determines the rotor position of the motor 4 based on the measured values of the phase currents Iu, Iv, and Iw of the motor 4 measured by the current detection unit 27, and the motor 4 is placed at the determined rotor position. A signal for designating a pattern for energizing the inverter circuit 23 (energization pattern for the inverter circuit 23) is generated so that the rotor follows.
　ここで、インバータ回路２３の通電パターンは、モータ４を通電させるパターン（モータ４の通電パターン）と言い換えてもよい。インバータ回路２３の通電パターンを指定する信号は、例えば、モータ４が回転するようにインバータ回路２３を通電させる３相のＰＷＭ信号を含む。 Here, the energization pattern of the inverter circuit 23 may be rephrased as a pattern for energizing the motor 4 (energization pattern of the motor 4). The signal that specifies the energization pattern of the inverter circuit 23 includes, for example, a three-phase PWM signal that energizes the inverter circuit 23 so that the motor 4 rotates.
　本実施の形態において、通電パターン生成部３５は、インバータ回路２３の通電パターンを、ベクトル制御により生成する。なお、インバータの通電パターンを生成する方法は、ベクトル制御に限らず、ｖｆ制御等を用いて各相の相電圧を求める方法であってもよい。 In the present embodiment, the energization pattern generation unit 35 generates the energization pattern of the inverter circuit 23 by vector control. The method of generating the energization pattern of the inverter is not limited to vector control, and may be a method of obtaining the phase voltage of each phase by using vf control or the like.
　具体的に、通電パターン生成部３５は、デューティ比設定部３９およびＰＷＭ信号生成部３２を有する。
　デューティ比設定部３９は、インバータ回路２３の通電パターンを指定する信号としてのＰＷＭ信号を生成するための機能部である。デューティ比設定部３９は、電流検出部２７による電流の検出結果に基づいて、３相のＰＷＭ信号のデューティ比を設定する。デューティ比設定部３９は、例えば、ベクトル制御部３０およびデューティ比算出部３１を含む。 Specifically, the energization pattern generation unit 35 includes a duty ratio setting unit 39 and a PWM signal generation unit 32.
The duty ratio setting unit 39 is a functional unit for generating a PWM signal as a signal for designating the energization pattern of the inverter circuit 23. The duty ratio setting unit 39 sets the duty ratio of the three-phase PWM signal based on the current detection result by the current detection unit 27. The duty ratio setting unit 39 includes, for example, a vector control unit 30 and a duty ratio calculation unit 31.
　ベクトル制御部３０は、外部からモータ４の回転速度指令ωｒｅｆが与えられると、モータ４の回転速度の計測値又は推定値と回転速度指令ωｒｅｆとの差分に基づいて、トルク電流指令Ｉｑｒｅｆと励磁電流指令Ｉｄｒｅｆを生成する。ベクトル制御部３０は、電流検出部２７による相電流Ｉｕ，Ｉｖ，Ｉｗの計測値に基づいて、ロータ位置θを用いたベクトル制御演算により、トルク電流Ｉｑ及び励磁電流Ｉｄを算出する。 When the rotation speed command ωref of the motor 4 is given from the outside, the vector control unit 30 sets the torque current command Iqref and the exciting current based on the difference between the measured value or the estimated value of the rotation speed of the motor 4 and the rotation speed command ωref. Generate the command Idref. The vector control unit 30 calculates the torque current Iq and the exciting current Id by the vector control calculation using the rotor position θ based on the measured values of the phase currents Iu, Iv, and Iw by the current detection unit 27.
　ベクトル制御部３０は、トルク電流指令Ｉｑｒｅｆとトルク電流Ｉｑとの差分に対して例えばＰＩ制御演算を行い、電圧指令Ｖｑを生成する。ベクトル制御部３０は、励磁電流指令Ｉｄｒｅｆと励磁電流Ｉｄとの差分に対して例えばＰＩ制御演算を行い、電圧指令Ｖｄを生成する。 The vector control unit 30 performs, for example, a PI control calculation on the difference between the torque current command Iqref and the torque current Iq, and generates the voltage command Vq. The vector control unit 30 performs, for example, a PI control calculation on the difference between the exciting current command Idref and the exciting current Id, and generates the voltage command Vd.
　ベクトル制御部３０は、電圧指令Ｖｑ，Ｖｄを上記のロータ位置θを用いてＵ，Ｖ，Ｗ各相の相電圧指令Ｖｕ＊，Ｖｖ＊，Ｖｗ＊に変換する。各相の相電圧指令Ｖｕ＊，Ｖｖ＊，Ｖｗ＊は、デューティ比設定部３９に供給される。 The vector control unit 30 converts the voltage commands Vq and Vd into phase voltage commands Vu *, Vv * and Vw * for each of the U, V and W phases using the rotor position θ. The phase voltage commands Vu *, Vv *, and Vw * of each phase are supplied to the duty ratio setting unit 39.
　デューティ比算出部３１は、入力される各相の相電圧指令Ｖｕ＊，Ｖｖ＊，Ｖｗ＊に基づいて、３相のＰＷＭ信号を生成するためのデューティ比（各相のデューティ比の設定値）Ｕｄｕ，Ｖｄｕ，Ｗｄｕを算出する。 The duty ratio calculation unit 31 is a duty ratio (set value of the duty ratio of each phase) for generating a three-phase PWM signal based on the input phase voltage commands Vu *, Vv *, Vw * of each phase. Calculate Udu, Vdu, and Wdu.
　ここで、各相のデューティ比Ｕｄｕ，Ｖｄｕ，Ｗｄｕの算出方法の具体例を説明する。
　各相のデューティ比Ｕｄｕ，Ｖｄｕ，Ｗｄｕは、下記（１）～（３）式に示すように、変調率ｍｏｄＵ，ｍｏｄＶ及びｍｏｄＷに基づき算出される。 Here, a specific example of a method of calculating the duty ratios Udu, Vdu, and Wdu of each phase will be described.
The duty ratios Udu, Vdu, and Wdu of each phase are calculated based on the modulation factors modU, modV, and modW as shown in the following equations (1) to (3).
　下記（１）～（３）式に基づいて得られる各相のデューティ比Ｕｄｕ，Ｖｄｕ，Ｗｄｕは、例えば１２０度ずつ位相が異なる正弦波状の波形となる。なお、各相のデューティ比Ｕｄｕ，Ｖｄｕ，Ｗｕｄの波形の例については後述する。 The duty ratios Udu, Vdu, and Wdu of each phase obtained based on the following equations (1) to (3) are, for example, sinusoidal waveforms having different phases by 120 degrees. An example of waveforms of duty ratios Udu, Vdu, and Wud of each phase will be described later.
　Ｕｄｕ＝ｍｏｄＵ×（キャリア上限値）・・・（１）
　Ｖｄｕ＝ｍｏｄＶ×（キャリア上限値）・・・（２）
　Ｗｄｕ＝ｍｏｄＷ×（キャリア上限値）・・・（３） Udu = modU × (carrier upper limit) ・ ・ ・ (1)
Vdu = modV × (carrier upper limit) ・ ・ ・ (2)
Wdu = modW × (carrier upper limit) ・ ・ ・ (3)
　ＰＷＭ信号生成部３２は、デューティ比設定部３９により設定される各相のデューティ比Ｕｄｕ，Ｖｄｕ，Ｗｄｕと、キャリアＣ１，Ｃ２とに基づいて、通電パターン信号としての３相のＰＷＭ信号Ｕ，Ｖ，Ｗを生成する。 The PWM signal generation unit 32 is a three-phase PWM signal U, V as an energization pattern signal based on the duty ratios Udu, Vdu, Wdu of each phase set by the duty ratio setting unit 39 and the carriers C1 and C2. , W is generated.
　上述したように、キャリアＣ１，Ｃ２は、レベルが周期的に増減する搬送波信号である。ＰＷＭ信号生成部３２は、各相のデューティ比Ｕｄｕ，Ｖｄｕ，Ｗｄｕに基づく閾値とキャリアＣ１，Ｃ２との比較結果に基づいて、３相のＰＷＭ信号Ｕ，Ｖ，Ｗを生成する。 As described above, carriers C1 and C2 are carrier signals whose levels increase and decrease periodically. The PWM signal generation unit 32 generates three-phase PWM signals U, V, W based on the comparison result between the threshold values based on the duty ratios Udu, Vdu, and Wdu of each phase and the carriers C1 and C2.
　ＰＷＭ信号Ｕは、Ｕ相上アームのスイッチング素子を駆動するためのＰＷＭ信号ＵＨとＵ相下アームのスイッチング素子を駆動するためのＰＷＭ信号ＵＬを含む。ＰＷＭ信号Ｖは、Ｖ相上アームのスイッチング素子を駆動するためのＰＷＭ信号ＶＨとＶ相下アームのスイッチング素子を駆動するためのＰＷＭ信号ＶＬとを含む。ＰＷＭ信号Ｗは、Ｗ相上アームのスイッチング素子を駆動するためのＰＷＭ信号ＷＨとｗ相下アームのスイッチング素子を駆動するためのＰＷＭ信号ＷＬとを含む。 The PWM signal U includes a PWM signal UH for driving the switching element of the U-phase upper arm and a PWM signal UL for driving the switching element of the U-phase lower arm. The PWM signal V includes a PWM signal VH for driving the switching element of the V-phase upper arm and a PWM signal VL for driving the switching element of the V-phase lower arm. The PWM signal W includes a PWM signal WH for driving the switching element of the W phase upper arm and a PWM signal WL for driving the switching element of the w phase lower arm.
　駆動回路３３は、与えられたＰＷＭ信号を含む通電パターンに従い、インバータ回路２３に含まれる６つのスイッチング素子２５Ｕ＋，２５Ｖ＋，２５Ｗ＋，２５Ｕ－，２５Ｖ－，２５Ｗ－をスイッチングさせる駆動信号を出力する。これにより、３相交流の駆動電流がモータ４に供給され、モータ４のロータが回転する。
　なお、駆動回路３３から出力される各駆動信号は、上述したＰＷＭ信号ＵＨ，ＵＬ、ＰＷＭ信号ＶＨ，ＶＬ、およびＰＷＭ信号ＷＨ，ＷＬに対応する論理レベルを有する信号であるため、図１では、駆動回路３３から出力される各駆動信号にＰＷＭ信号と同一の参照符号を付している。 The drive circuit 33 outputs a drive signal for switching the six switching elements 25U +, 25V +, 25W +, 25U−, 25V−, 25W− included in the inverter circuit 23 according to the energization pattern including the given PWM signal. As a result, a three-phase alternating current drive current is supplied to the motor 4, and the rotor of the motor 4 rotates.
Since each drive signal output from the drive circuit 33 is a signal having a logic level corresponding to the above-mentioned PWM signals UH, UL, PWM signals VH, VL, and PWM signals WH, WL, it is shown in FIG. Each drive signal output from the drive circuit 33 has the same reference code as the PWM signal.
　電流検出タイミング調整部３４は、電流検出部２７がＰＷＭ信号の１周期内で３つの相の内、２つの相の相電流を検出するための取得タイミングを決定する。 The current detection timing adjusting unit 34 determines the acquisition timing for the current detecting unit 27 to detect the phase currents of two of the three phases within one cycle of the PWM signal.
　なお、電流検出部２７、通電パターン生成部３５及び電流検出タイミング調整部３４は、不図示の記憶装置に読み出し可能に記憶されるプログラムに従ってプロセッサ（例えば、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ））が各種の演算を行うことによって実現される。例えば、これらの各機能は、ＣＰＵを含むマイクロコンピュータにおけるハードウェアとソフトウェアとの協働により実現される。 In the current detection unit 27, the energization pattern generation unit 35, and the current detection timing adjustment unit 34, a processor (for example, a CPU (Central Processing Unit)) performs various calculations according to a program readable and stored in a storage device (not shown). It is realized by doing. For example, each of these functions is realized by the collaboration of hardware and software in a microcomputer including a CPU.
　次に、キャリア発生部３７及びＰＷＭ信号生成部３２の詳細を説明する。
　図３は、実施の形態１に係るモータ制御装置１００におけるキャリア発生部３７及びＰＷＭ信号生成部３２の構成例を示す図である。例えば、キャリア発生部３７及びＰＷＭ信号生成部３２は、上述した制御部２０を構成するＭＣＵにおいて、プロセッサがＲＡＭやＲＯＭ等の記憶装置に記憶されたプログラムに従って各種演算を行うとともにタイマ（カウンタ）、Ａ／Ｄ変換回路、および入出力Ｉ／Ｆ回路等の周辺回路を制御することによって、実現される。 Next, the details of the carrier generation unit 37 and the PWM signal generation unit 32 will be described.
FIG. 3 is a diagram showing a configuration example of a carrier generation unit 37 and a PWM signal generation unit 32 in the motor control device 100 according to the first embodiment. For example, the carrier generation unit 37 and the PWM signal generation unit 32 perform various calculations according to a program stored in a storage device such as a RAM or ROM in the MCU constituting the control unit 20 described above, and a timer (counter). It is realized by controlling peripheral circuits such as an A / D conversion circuit and an input / output I / F circuit.
　キャリア発生部３７は、各相のＰＷＭ信号のキャリアＣとして、上述した２種類のキャリアＣ１，Ｃ２を生成する。キャリア発生部３７は、図１に示すクロック発生部３６によって生成されたクロックＣＬＫに基づいて、ＰＷＭ周期における第１期間Ａに対応する周期でレベルが増減するのこぎり波状のキャリアＣ１と、ＰＷＭ周期における第２期間Ｂに対応する周期でレベルが増減するのこぎり波状のキャリアＣ２とを生成する。 The carrier generation unit 37 generates the above-mentioned two types of carriers C1 and C2 as the carrier C of the PWM signal of each phase. The carrier generation unit 37 has a saw-like wavy carrier C1 whose level increases or decreases in a cycle corresponding to the first period A in the PWM cycle based on the clock CLK generated by the clock generation unit 36 shown in FIG. A saw-like carrier C2 whose level increases or decreases in a cycle corresponding to the second period B is generated.
　具体的に、キャリア発生部３７は、カウント部１２、上限値切替部１３、比較器１４、切替制御部１５、および上限値記憶部１６を備える。 Specifically, the carrier generation unit 37 includes a count unit 12, an upper limit value switching unit 13, a comparator 14, a switching control unit 15, and an upper limit value storage unit 16.
　カウント部１２は、例えば、マイクロコントローラに内蔵されているカウンタ（アップカウンタ）によって実現される。カウント部１２には、クロックＣＬＫと、計数開始信号及び計数初期値信号とが入力される。 The counting unit 12 is realized by, for example, a counter (up counter) built in the microcontroller. The clock CLK, the counting start signal, and the counting initial value signal are input to the counting unit 12.
　カウント部１２は、計数開始信号が与えられると、クロックＣＬＫの計数を開始し、計数値の累加算（クロックＣＬＫが入力されるたびに１を加算）により、のこぎり波キャリアであるキャリアＣ１，Ｃ２を出力する。 When the counting start signal is given, the counting unit 12 starts counting the clock CLK, and by accumulating the counting values (adding 1 each time the clock CLK is input), the carriers C1 and C2 which are sawtooth carriers. Is output.
　また、カウント部１２には、計数の初期値が設定されており、この初期値は、前述した計数初期値信号により設定される。 Further, an initial value of counting is set in the counting unit 12, and this initial value is set by the above-mentioned initial counting value signal.
　比較器１４は、カウント部１２の計数値と、上限値Ｔｘとを比較し、比較結果を示す２値の検出信号Ｃｐを出力する。例えば、比較器１４は、カウント部１２の計数値（Ｃ１またはＣ２）が上限値Ｔｘより低い場合に、ローレベルの検出信号Ｃｐを出力し、カウント部１２の計数値（Ｃ１またはＣ２）が上限値Ｔｘより高い場合に、ハイレベルの検出信号Ｃｐを出力する。 The comparator 14 compares the count value of the count unit 12 with the upper limit value Tx, and outputs a binary detection signal Cp indicating the comparison result. For example, when the counting value (C1 or C2) of the counting unit 12 is lower than the upper limit value Tx, the comparator 14 outputs a low-level detection signal Cp, and the counting value (C1 or C2) of the counting unit 12 is the upper limit. When the value is higher than the value Tx, the high level detection signal Cp is output.
　切替制御部１５は、比較器１４からの出力された検出信号Ｃｐに応じて、２値の制御信号Ｓｃを出力する。切替制御部１５は、例えば、フリップフロップである。切替制御部１５は、比較器１４からの検出信号Ｃｐの立ち上がりエッジに応じて、制御信号Ｓｃの論理レベルを切り替える。 The switching control unit 15 outputs a binary control signal Sc according to the detection signal Cp output from the comparator 14. The switching control unit 15 is, for example, a flip-flop. The switching control unit 15 switches the logic level of the control signal Sc according to the rising edge of the detection signal Cp from the comparator 14.
　カウント部１２は、比較器１４からの出力された検出信号Ｃｐに応じて、クロックの計数値をリセットして、計数初期値信号によって指定された初期値からクロックの計数値を累加算する。例えば、カウント部１２は、検出信号Ｃｐの立ち上がりエッジに応じて、クロックの計数値をリセットして、初期値からクロックの計数値を累加算する。 The counting unit 12 resets the clock counting value according to the detection signal Cp output from the comparator 14, and accumulates the clock counting value from the initial value specified by the counting initial value signal. For example, the counting unit 12 resets the clock count value according to the rising edge of the detection signal Cp, and accumulates the clock count value from the initial value.
　上限値記憶部１６は、キャリアＣ１，Ｃ２の周期、すなわち、上述したＰＷＭ信号の１周期における第１期間Ａと第２期間Ｂの長さを指定するための情報を記憶する。具体的に、上限値記憶部１６は、第１上限値Ｔ１と第２上限値Ｔ２を記憶する。 The upper limit value storage unit 16 stores information for designating the cycles of carriers C1 and C2, that is, the lengths of the first period A and the second period B in one cycle of the PWM signal described above. Specifically, the upper limit value storage unit 16 stores the first upper limit value T1 and the second upper limit value T2.
　第１上限値Ｔ１は、キャリアＣ１の周期、すなわち、ＰＷＭ周期における第１期間Ａの長さを指定する値である。第２上限値Ｔ２は、キャリアＣ２の周期、すなわち、ＰＷＭ周期における第２期間Ｂの長さを指定する値である。 The first upper limit value T1 is a value that specifies the period of the carrier C1, that is, the length of the first period A in the PWM cycle. The second upper limit value T2 is a value that specifies the period of the carrier C2, that is, the length of the second period B in the PWM cycle.
　ここで、ＰＷＭ周期をＴとしたとき、Ｔ＝Ｔ１＋Ｔ２であり、Ｔ１＜Ｔ２である。 Here, when the PWM cycle is T, T = T1 + T2 and T1 <T2.
　上限値切替部１３は、比較器１４に入力すべき上限値Ｔｘを切り替える。具体的に、上限値切替部１３は、切替制御部１５から出力された制御信号Ｓｃに応じて、上限値記憶部１６に記憶されている第１上限値Ｔ１および第２上限値Ｔ２を上限値Ｔｘとして交互に出力する。例えば、制御信号Ｓｃがローレベルである場合には、上限値切替部１３は、第１上限値Ｔ１を上限値Ｔｘとして比較器１４に与える。一方、制御信号Ｓｃがハイレベルである場合には、上限値切替部１３は、第２上限値Ｔ２を上限値Ｔｘとして比較器１４に与える。 The upper limit value switching unit 13 switches the upper limit value Tx to be input to the comparator 14. Specifically, the upper limit value switching unit 13 sets the first upper limit value T1 and the second upper limit value T2 stored in the upper limit value storage unit 16 as upper limit values according to the control signal Sc output from the switching control unit 15. It is output alternately as Tx. For example, when the control signal Sc is at a low level, the upper limit value switching unit 13 gives the first upper limit value T1 to the comparator 14 as the upper limit value Tx. On the other hand, when the control signal Sc is at a high level, the upper limit value switching unit 13 gives the second upper limit value T2 to the comparator 14 as the upper limit value Tx.
　図４は、キャリアＣ１，Ｃ２の生成原理を説明するための図である。
　時刻ｔ０において、計数開始信号がカウント部１２に与えられると、カウント部１２がクロックＣＬＫの計数を開始し、計数値の累加算を行う。このとき、切替制御部１５は、例えばローレベルの制御信号Ｓｃを出力する。上限値切替部１３は、ローレベルの制御信号Ｓｃに応じて、第１上限値Ｔ１を上限値Ｔｘとして比較器１４に与える。 FIG. 4 is a diagram for explaining the generation principle of carriers C1 and C2.
When the counting start signal is given to the counting unit 12 at time t0, the counting unit 12 starts counting the clock CLK and accumulates the counting values. At this time, the switching control unit 15 outputs, for example, a low-level control signal Sc. The upper limit value switching unit 13 gives the first upper limit value T1 to the comparator 14 as the upper limit value Tx according to the low level control signal Sc.
　その後、計数値が増加し、時刻ｔ１において計数値が上限値Ｔｘ（＝Ｔ１）と一致したとき、比較器１４は、計数値が上限値Ｔｘに達したことを検出して、ハイレベルの検出信号Ｃｐを出力する。 After that, when the count value increases and the count value matches the upper limit value Tx (= T1) at time t1, the comparator 14 detects that the count value has reached the upper limit value Tx, and detects a high level. Output the signal Cp.
　カウント部１２は、ハイレベルの検出信号Ｃｐに応じて、計数値をリセットし、再び、ゼロからクロックＣＬＫの計数値の累加算を開始する。これにより、キャリアＣ１の生成が終了し、比較器１４の検出信号Ｃｐがローレベルに切り替わる。 The counting unit 12 resets the counting value according to the high-level detection signal Cp, and starts the cumulative addition of the counting value of the clock CLK from zero again. As a result, the generation of the carrier C1 is completed, and the detection signal Cp of the comparator 14 is switched to the low level.
　また、切替制御部１５は、時刻ｔ１における検出信号Ｃｐの立ち上がりエッジに応じて、制御信号Ｓｃの論理レベルを反転させる。すなわち、制御信号Ｓｃの論理レベルをローレベルからハイレベルに切り替える。上限値切替部１３は、ハイレベルの制御信号Ｓｃに応じて、第２上限値Ｔ２を上限値Ｔｘとして比較器１４に与える。 Further, the switching control unit 15 inverts the logic level of the control signal Sc according to the rising edge of the detection signal Cp at time t1. That is, the logic level of the control signal Sc is switched from the low level to the high level. The upper limit value switching unit 13 gives the second upper limit value T2 as the upper limit value Tx to the comparator 14 according to the high level control signal Sc.
　その後、計数値が増加し、時刻ｔ２において計数値が第２上限値Ｔ２と一致したとき、比較器１４は、計数値が上限値Ｔｘ（＝Ｔ２）に達したことを検出してハイレベルの検出信号Ｃｐを出力する。 After that, when the count value increases and the count value coincides with the second upper limit value T2 at time t2, the comparator 14 detects that the count value has reached the upper limit value Tx (= T2) and is at a high level. The detection signal Cp is output.
　カウント部１２は、ハイレベルの検出信号Ｃｐに応じて、計数値をリセットし、再び、ゼロからクロックＣＬＫの計数値の累加算を開始する。これにより、キャリアＣ２の生成が終了し、比較器１４の検出信号Ｃｐがローレベルに切り替わる。 The counting unit 12 resets the counting value according to the high-level detection signal Cp, and starts the cumulative addition of the counting value of the clock CLK from zero again. As a result, the generation of the carrier C2 is completed, and the detection signal Cp of the comparator 14 is switched to the low level.
　また、切替制御部１５は、時刻ｔ２における検出信号Ｃｐの立ち上がりエッジに応じて、制御信号Ｓｃの論理レベルを反転させる。すなわち、制御信号Ｓｃの論理レベルをハイレベルからローレベルに切り替える。上限値切替部１３は、ローレベルの制御信号Ｓｃに応じて、再び、第１上限値Ｔ１を上限値Ｔｘとして比較器１４に与える。その後は、時刻ｔ０から時刻ｔ２までの処理と同様に処理が繰り返し行われる。 Further, the switching control unit 15 inverts the logic level of the control signal Sc according to the rising edge of the detection signal Cp at time t2. That is, the logic level of the control signal Sc is switched from the high level to the low level. The upper limit value switching unit 13 again gives the first upper limit value T1 to the comparator 14 as the upper limit value Tx according to the low level control signal Sc. After that, the process is repeated in the same manner as the process from time t0 to time t2.
　これによれば、ＰＷＭ周期内に、２つののこぎり波のキャリアＣ１，Ｃ２を生成することができる。 According to this, it is possible to generate carriers C1 and C2 of two sawtooth waves within the PWM cycle.
　次に、ＰＷＭ信号生成部３２について、説明する。
　図３に示すように、ＰＷＭ信号生成部３２は、固定閾値記憶部４０、可変閾値算出部４１、閾値切替部４２Ｕ，４２Ｖ，４２Ｗ、比較器４３Ｕ，４３Ｖ，４３Ｗ、ＰＷＭ回路４４、および割り込みコントローラ４５を有する。 Next, the PWM signal generation unit 32 will be described.
As shown in FIG. 3, the PWM signal generation unit 32 includes a fixed threshold storage unit 40, a variable threshold calculation unit 41, a threshold switching unit 42U, 42V, 42W, a comparator 43U, 43V, 43W, a PWM circuit 44, and an interrupt controller. Has 45.
　固定閾値記憶部４０は、デューティ比算出部３１によって算出されたデューティ比Ｕｄｕ，Ｖｄｕ，Ｗｄｕに基づいて生成したＰＷＭ信号Ｕ，Ｖ，Ｗのゼロベクトル区間に通電区間を設けるための閾値の情報が記憶される。具体的に、固定閾値記憶部４０は、ＰＷＭ周期の第２期間Ｂにおける各相のＰＷＭ信号の信号レベルが切り替わるタイミングを指定する情報として、Ｕ相、Ｖ相、およびＷ相の各々に対応する固定閾値Ｕｄｕ１，Ｕｄｕ２、固定閾値Ｖｄｕ１，Ｖｄｕ２、および固定閾値Ｗｄｕ１，Ｗｄｕ２を記憶する。 The fixed threshold storage unit 40 contains threshold information for providing an energization section in the zero vector section of the PWM signals U, V, W generated based on the duty ratios Udu, Vdu, Wdu calculated by the duty ratio calculation unit 31. It will be remembered. Specifically, the fixed threshold storage unit 40 corresponds to each of the U phase, the V phase, and the W phase as information for designating the timing at which the signal level of the PWM signal of each phase is switched in the second period B of the PWM cycle. The fixed threshold values Udu1 and Udu2, the fixed threshold values Vdu1 and Vdu2, and the fixed threshold values Wdu1 and Wdu2 are stored.
　固定閾値Ｕｄｕ１，Ｕｄｕ２（Ｕｄｕ１＜Ｕｄｕ２）は、ＰＷＭ周期の第１期間ＡにおけるＵ相のＰＷＭ信号の信号レベルの切り替りタイミングを指定する値である。固定閾値Ｖｄｕ１，Ｖｄｕ２（Ｖｄｕ１＜Ｖｄｕ２）は、ＰＷＭ周期の第１期間ＡにおけるＶ相のＰＷＭ信号の信号レベルの切り替りタイミングを指定する値である。固定閾値Ｗｄｕ１，Ｗｄｕ２は、ＰＷＭ周期の第１期間ＡにおけるＷ相のＰＷＭ信号の信号レベルの切り替りタイミングを指定する値である。例えば、Ｕｄｕ１＜Ｖｄｕ１＜Ｗｄｕ１＝Ｕｄｕ２＜Ｖｄｕ２＜Ｕｄｕ３＜Ｗｄｕ２である。 The fixed threshold values Udu1 and Udu2 (Udu1 <Udu2) are values that specify the switching timing of the signal level of the U-phase PWM signal in the first period A of the PWM cycle. The fixed threshold values Vdu1 and Vdu2 (Vdu1 <Vdu2) are values that specify the switching timing of the signal level of the V-phase PWM signal in the first period A of the PWM cycle. The fixed threshold values Wdu1 and Wdu2 are values that specify the switching timing of the signal level of the W-phase PWM signal in the first period A of the PWM cycle. For example, Udu1 <Vdu1 <Wdu1 = Udu2 <Vdu2 <Udu3 <Wdu2.
　可変閾値算出部４１は、デューティ比設定部３９によって設定されたＵ相、Ｖ相、Ｗ相の各デューティ比Ｕｄｕ，Ｖｄｕ，ＷｄｕのＰＷＭ信号が生成されるように、可変閾値Ｕｄｕ３，Ｖｄｕ３，Ｗｄｕ３，Ｕｄｕ４，Ｖｄｕ４，Ｗｄｕ４を算出する。 The variable threshold value calculation unit 41 generates variable threshold value Udu3, Vdu3, Wdu3 so that PWM signals of U-phase, V-phase, and W-phase duty ratios Udu, Vdu, and Wdu set by the duty ratio setting unit 39 are generated. , Udu4, Vdu4, Wdu4 are calculated.
　可変閾値Ｕｄｕ３，Ｕｄｕ４（Ｕｄｕ３＜Ｕｄｕ４）は、ＰＷＭ周期の第２期間ＢにおけるＵ相のＰＷＭ信号の信号レベルの切り替りタイミングを指定する値である。可変閾値Ｖｄｕ３，Ｖｄｕ４（Ｖｄｕ３＜Ｖｄｕ４）は、ＰＷＭ周期の第２期間ＢにおけるＵ相のＰＷＭ信号の信号レベルの切り替りタイミングを指定する値である。可変閾値Ｗｄｕ３，Ｗｄｕ４（Ｗｄｕ３＜Ｗｄｕ４）は、ＰＷＭ周期の第２期間ＢにおけるＵ相のＰＷＭ信号の信号レベルの切り替りタイミングを指定する値である。 The variable threshold values Udu3 and Udu4 (Udu3 <Udu4) are values that specify the switching timing of the signal level of the U-phase PWM signal in the second period B of the PWM cycle. The variable threshold values Vdu3 and Vdu4 (Vdu3 <Vdu4) are values that specify the signal level switching timing of the U-phase PWM signal in the second period B of the PWM cycle. The variable threshold values Wdu3 and Wdu4 (Wdu3 <Wdu4) are values that specify the switching timing of the signal level of the U-phase PWM signal in the second period B of the PWM cycle.
　可変閾値算出部４１は、デューティ比設定部３９によって設定されたＵ相のデューティ比Ｕｄｕに基づいて、可変閾値Ｕｄｕ３，Ｕｄｕ４を算出する。同様に、可変閾値算出部４１は、デューティ比設定部３９によって設定されたＶ相のデューティ比Ｖｄｕに基づいて、可変閾値Ｖｄｕ３，Ｖｄｕ４を算出し、デューティ比設定部３９によって設定されたＷ相のデューティ比Ｗｄｕに基づいて、可変閾値Ｗｄｕ３，Ｗｄｕ４を算出する。 The variable threshold value calculation unit 41 calculates the variable threshold values Udu3 and Udu4 based on the duty ratio Udu of the U phase set by the duty ratio setting unit 39. Similarly, the variable threshold value calculation unit 41 calculates the variable threshold values Vdu3 and Vdu4 based on the duty ratio Vdu of the V phase set by the duty ratio setting unit 39, and of the W phase set by the duty ratio setting unit 39. The variable thresholds Wdu3 and Wdu4 are calculated based on the duty ratio Wdu.
　閾値切替部４２Ｕ，４２Ｖ，４２Ｗは、比較器４３Ｕ，４３Ｖ，４３Ｗに入力すべき閾値Ｕｄｕｘ，Ｖｄｕｘ，Ｗｄｕｘを切り替える。具体的に、閾値切替部４２Ｕ，４２Ｖ，４２Ｗは、第１期間Ａと第２期間Ｂの切り替わりに応じて、出力対象の閾値を、固定閾値Ｕｄｕ１，Ｕｄｕ２，Ｖｄｕ１，Ｖｄｕ２，Ｗｄｕ１，Ｗｄｕ２と、可変閾値Ｕｄｕ３，Ｕｄｕ４，Ｖｄｕ３，Ｖｄｕ４，Ｗｄｕ３，Ｗｄｕ４との間で切り替える。 The threshold switching units 42U, 42V, 42W switch the thresholds Udux, Vdux, Wdux to be input to the comparators 43U, 43V, 43W. Specifically, the threshold value switching units 42U, 42V, 42W set the threshold value of the output target to the fixed threshold values Udu1, Udu2, Vdu1, Vdu2, Wdu1, Wdu2 according to the switching between the first period A and the second period B. The variable threshold is switched between Udu3, Udu4, Vdu3, Vdu4, Wdu3, and Wdu4.
　また、閾値切替部４２Ｕ，４２Ｖ，４２Ｗは、対応する比較器４３Ｕ，４３Ｖ，４３Ｗの出力信号Ｃｐｕ，Ｃｐｖ，Ｃｐｗに基づいて、固定閾値Ｕｄｕ１，Ｖｄｕ１，Ｗｄｕ１と固定閾値Ｕｄｕ２，Ｖｄｕ２，Ｗｄｕ２とを交互に切り替えて、閾値Ｕｄｕｘ，Ｖｄｕｘ，Ｗｄｕｘとして出力する。 Further, the threshold switching units 42U, 42V, 42W set the fixed thresholds Udu1, Vdu1, Wdu1 and the fixed thresholds Udu2, Vdu2, Wdu2 based on the output signals Cpu, Cpv, Cpw of the corresponding comparators 43U, 43V, 43W. It is switched alternately and output as threshold values Udux, Vdux, and Wdux.
　例えば、切替制御部１５からの制御信号Ｓｃがハイレベルからローレベルに切り替わったとき、閾値切替部４２Ｕは、固定閾値Ｕｄｕ１および固定閾値Ｕｄｕ２を出力対象の閾値とする。この場合に、閾値切替部４２は、初期値として固定閾値Ｕｄｕ１を閾値Ｕｄｕｘとして比較器４３Ｕに与える。次に、閾値切替部４２は、比較器４３Ｕの出力信号Ｃｐｕの信号レベルが反転した場合に、固定閾値Ｕｄｕ２を閾値Ｕｄｕｘとして比較器４３Ｕに与える。 For example, when the control signal Sc from the switching control unit 15 is switched from the high level to the low level, the threshold value switching unit 42U sets the fixed threshold value Udu1 and the fixed threshold value Udu2 as the threshold values to be output. In this case, the threshold switching unit 42 gives the fixed threshold value Udu1 as the initial value to the comparator 43U as the threshold value Udux. Next, the threshold value switching unit 42 gives the fixed threshold value Udu2 to the comparator 43U as the threshold value Udux when the signal level of the output signal Cpu of the comparator 43U is inverted.
　その後、制御信号Ｓｃがローレベルからハイレベルに切り替わったとき、閾値切替部４２Ｕは、可変閾値Ｕｄｕ３および可変閾値Ｕｄｕ４を出力対象の閾値とする。この場合に、閾値切替部４２は、初期値として可変閾値Ｕｄｕ３を閾値Ｕｄｕｘとして比較器４３Ｕに与える。次に、閾値切替部４２は、比較器４３Ｕの出力信号Ｃｐｕの信号レベルが反転した場合に、可変閾値Ｕｄｕ４を閾値Ｕｄｕｘとして比較器４３Ｕに与える。 After that, when the control signal Sc is switched from the low level to the high level, the threshold switching unit 42U sets the variable threshold value Udu3 and the variable threshold value Udu4 as the threshold values to be output. In this case, the threshold switching unit 42 gives the variable threshold value Udu3 as the initial value to the comparator 43U as the threshold value Udux. Next, the threshold value switching unit 42 gives the variable threshold value Udu4 to the comparator 43U as the threshold value Udux when the signal level of the output signal Cpu of the comparator 43U is inverted.
　その後、再び、制御信号Ｓｃがハイレベルからローレベルに切り替わったとき、閾値切替部４２Ｕは、再び、固定閾値Ｕｄｕ１および固定閾値Ｕｄｕ２を出力対象の閾値とする。その後は、上述の処理が繰り返し行われる。 After that, when the control signal Sc is switched from the high level to the low level again, the threshold switching unit 42U again sets the fixed threshold value Udu1 and the fixed threshold value Udu2 as the threshold values to be output. After that, the above-mentioned process is repeated.
　比較器４３Ｕは、Ｕ相の閾値ＵｄｕｘとキャリアＣ１，Ｃ２との比較を行い、２値の出力信号Ｃｐｕを生成する。具体的に、比較器４３Ｕは、第１期間Ａにおいて、閾値ＵｄｕｘとキャリアＣ１とを比較し、キャリアＣ１のレベルが閾値Ｕｄｕｘ（＝Ｕｄｕ１、Ｕｄｕ２）と一致した場合に、出力信号Ｃｐｕの信号レベルを反転し、第２期間Ｂにおいて、閾値ＵｄｕｘとキャリアＣ２とを比較し、キャリアＣ２のレベルが閾値Ｕｄｕｘ（＝Ｕｄｕ３，Ｕｄｕ４）と一致した場合に、出力信号Ｃｐｕの信号レベルを反転する。 The comparator 43U compares the U-phase threshold value Udux with the carriers C1 and C2, and generates a binary output signal Cpu. Specifically, the comparator 43U compares the threshold value Udux and the carrier C1 in the first period A, and when the level of the carrier C1 matches the threshold value Udux (= Udu1, Udu2), the signal level of the output signal Cpu. Is inverted, and in the second period B, the threshold value Udux and the carrier C2 are compared, and when the level of the carrier C2 matches the threshold value Udux (= Udu3, Udu4), the signal level of the output signal Cpu is inverted.
　比較器４３Ｖは、Ｖ相の閾値ＶｄｕｘとキャリアＣ１，Ｃ２との比較を行い、２値の出力信号Ｃｐｖを生成する。具体的に、比較器４３Ｖは、第１期間Ａにおいて、閾値ＶｄｕｘとキャリアＣ１とを比較し、キャリアＣ１のレベルが閾値Ｖｄｕｘ（＝Ｖｄｕ１，Ｖｄｕ２）と一致した場合に、出力信号Ｃｐｖの論理レベルを反転し、第２期間Ｂにおいて、閾値ＶｄｕｘとキャリアＣ２とを比較し、キャリアＣ２のレベルが閾値Ｖｄｕｘ（＝Ｖｄｕ３，Ｖｄｕ４）と一致した場合に、出力信号Ｃｐｖの論理レベルを反転する。 The comparator 43V compares the V-phase threshold value Vdux with the carriers C1 and C2, and generates a binary output signal Cpv. Specifically, the comparator 43V compares the threshold value Vdux and the carrier C1 in the first period A, and when the level of the carrier C1 matches the threshold value Vdux (= Vdu1, Vdu2), the logical level of the output signal Cpv. Is inverted, and in the second period B, the threshold value Vdux and the carrier C2 are compared, and when the level of the carrier C2 matches the threshold value Vdux (= Vdu3, Vdu4), the logical level of the output signal Cpv is inverted.
　比較器４３Ｗは、Ｗ相の閾値ＷｄｕｘとキャリアＣ１，Ｃ２との比較を行い、２値の出力信号Ｃｐｗを生成する。具体的に、比較器４３Ｗは、第１期間Ａにおいて、閾値ＷｗｕｘとキャリアＣ１とを比較し、キャリアＣ１のレベルが閾値Ｗｗｕｘ（＝Ｗｄｕ１，Ｗｄｕ２）と一致した場合に、出力信号Ｃｐｗの論理レベルを反転し、第２期間Ｂにおいて、閾値ＷｄｕｘとキャリアＣ２とを比較し、キャリアＣ２のレベルが閾値Ｗｄｕｘ（＝Ｗｄｕ２，Ｗｄｕ２）と一致した場合に、出力信号Ｃｐｗの論理レベルを反転する。 The comparator 43W compares the threshold value Wdux of the W phase with the carriers C1 and C2, and generates a binary output signal Cpw. Specifically, the comparator 43W compares the threshold value Wwux and the carrier C1 in the first period A, and when the level of the carrier C1 matches the threshold value Wwux (= Wdu1, Wdu2), the logical level of the output signal Cpw. Is inverted, and in the second period B, the threshold value Wdux and the carrier C2 are compared, and when the level of the carrier C2 matches the threshold value Wdux (= Wdu2, Wdu2), the logical level of the output signal Cpw is inverted.
　ＰＷＭ回路４４は、比較器４３Ｕ，４３Ｖ，４３Ｗからの出力信号Ｃｐｕ，Ｃｐｖ，Ｃｐｗに基づいて、各相の電圧指令の変化に応じたオンオフ区間をもつＰＷＭ信号Ｕ，Ｖ，Ｗを出力する。上述したように、ＰＷＭ信号Ｕ，Ｖ，Ｗには、ＰＷＭ信号ＵＨ，ＵＬ，ＶＨ，ＶＬ，ＷＨ，及びＷＬの６種類のＰＷＭ信号が含まれる。 The PWM circuit 44 outputs PWM signals U, V, W having an on / off section according to a change in the voltage command of each phase based on the output signals Cpu, Cpv, Cpw from the comparators 43U, 43V, 43W. As described above, the PWM signals U, V, W include six types of PWM signals, the PWM signals UH, UL, VH, VL, WH, and WL.
　上記６種類のＰＷＭ信号は、インバータ回路２３の各スイッチング素子のゲートへ与えられる。６種類のＰＷＭ信号により、各スイッチング素子のオン／オフ動作が行われる。これによってインバータ回路２３からＵ相、Ｖ相、Ｗ相の各電圧が出力されて、モータ４に印加される。なお、具体的な通電方式については、実施の形態１においては三角波比較法を用いているが、三角波比較法に限らず、空間ベクトル法などのその他の方式を用いて各相の電圧を出力してもよい。 The above six types of PWM signals are given to the gate of each switching element of the inverter circuit 23. Each switching element is turned on / off by the six types of PWM signals. As a result, the U-phase, V-phase, and W-phase voltages are output from the inverter circuit 23 and applied to the motor 4. As for the specific energization method, the triangular wave comparison method is used in the first embodiment, but the voltage of each phase is output by using other methods such as the space vector method, not limited to the triangular wave comparison method. You may.
　また、ＰＷＭ回路４４は、ＰＷＭ周期の第２期間Ｂの所定のタイミングにおいて、割り込み信号Ｓｉを生成し、割り込みコントローラ４５へ与える。例えば、ＰＷＭ回路４４は、ＰＷＭ信号Ｕが立ち上がるタイミングにおいて、割り込み信号Ｓｉを割り込みコントローラ４５へ入力し、ＰＷＭ信号Ｖが立ち上がるタイミングにおいて、割り込み信号Ｓｉを割り込みコントローラ４５へ入力する。 Further, the PWM circuit 44 generates an interrupt signal Si at a predetermined timing in the second period B of the PWM cycle and gives it to the interrupt controller 45. For example, the PWM circuit 44 inputs the interrupt signal Si to the interrupt controller 45 at the timing when the PWM signal U rises, and inputs the interrupt signal Si to the interrupt controller 45 at the timing when the PWM signal V rises.
　割り込みコントローラ４５は、ＰＷＭ回路４４からの割り込み信号Ｓｉを受けて、電流検出部２７に対してＡ／Ｄ変換の指令を与える。例えば、割り込みコントローラ４５は、割り込み信号Ｓｉが入力される度に、割り込み信号Ｓｉを受けてから所定時間の経過後に、電流検出部２７に対してＡ／Ｄ変換の指令を与える。これにより、電流検出部２７は、第２期間Ｂにおける特定の相のＰＷＭ信号の信号レベルの切り替わりに応じて、検出信号ＳｄのＡ／Ｄ変換を行う。 The interrupt controller 45 receives the interrupt signal Si from the PWM circuit 44 and gives an A / D conversion command to the current detection unit 27. For example, each time the interrupt signal Si is input, the interrupt controller 45 gives an A / D conversion command to the current detection unit 27 after a predetermined time has elapsed after receiving the interrupt signal Si. As a result, the current detection unit 27 performs A / D conversion of the detection signal Sd according to the switching of the signal level of the PWM signal of the specific phase in the second period B.
　図５は、本実施の形態に係るモータ制御装置１００によるＰＷＭ信号の生成原理を説明するための図である。 FIG. 5 is a diagram for explaining the principle of generating a PWM signal by the motor control device 100 according to the present embodiment.
　先ず、時刻ｔ０において、キャリアＣ１の生成が開始されるとき、閾値切替部４２Ｕ，４２Ｖ，４２Ｗは、初期値として固定閾値Ｕｄｕ１，Ｖｄｕ１，Ｗｄｕ１を選択し、閾値Ｕｄｕｘ，Ｖｄｕｘ，Ｗｄｕｘとして比較器４３Ｕ，４３Ｖ，４３Ｗにそれぞれ与える。これにより、第１期間Ａ（キャリアＣ１が生成されている期間）において、比較器４３Ｕ，４３Ｖ，４３Ｗは、キャリアＣ１と固定閾値Ｕｄｕ１，Ｖｄｕ１，Ｗｄｕ１とを比較する。 First, at time t0, when the generation of the carrier C1 is started, the threshold switching units 42U, 42V, 42W select fixed thresholds Udu1, Vdu1, Wdu1 as initial values, and the comparator 43U is set as the thresholds Udux, Vdux, Wdux. , 43V, 43W, respectively. As a result, in the first period A (the period during which the carrier C1 is generated), the comparators 43U, 43V, 43W compare the carrier C1 with the fixed threshold values Udu1, Vdu1, Wdu1.
　時刻ｔ１において、キャリアＣ１のレベルと固定閾値Ｕｄｕ１とが一致したとき、比較器４３Ｕは、出力信号Ｃｐｕの論理レベルを反転する（例えば、ローレベルからハイレベルに切り替える）。これにより、ＰＷＭ回路４４は、Ｕ相のＰＷＭ信号Ｕをハイレベルからローレベルに切り替えるとともに、閾値切替部４２Ｕが、固定閾値Ｕｄｕ２を選択し、閾値Ｕｄｕｘとして比較器４３Ｕに与える。 At time t1, when the level of the carrier C1 and the fixed threshold value Udu1 match, the comparator 43U inverts the logical level of the output signal Cpu (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the U-phase PWM signal U from the high level to the low level, and the threshold switching unit 42U selects the fixed threshold value Udu2 and gives it to the comparator 43U as the threshold value Udux.
　次に、時刻ｔ２において、キャリアＣ１のレベルと固定閾値Ｖｄｕ１とが一致したとき、比較器４３Ｖは、出力信号Ｃｐｖの論理レベルを反転する（例えば、ローレベルからハイレベルに切り替える）。これにより、ＰＷＭ回路４４は、Ｕ相のＰＷＭ信号Ｖをハイレベルからローレベルに切り替えるとともに、閾値切替部４２Ｖが、固定閾値Ｖｄｕ２を選択し、閾値Ｖｄｕｘとして比較器４３Ｖに与える。 Next, at time t2, when the level of the carrier C1 and the fixed threshold value Vdu1 match, the comparator 43V inverts the logical level of the output signal Cpv (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the U-phase PWM signal V from the high level to the low level, and the threshold switching unit 42V selects the fixed threshold Vdu2 and gives it to the comparator 43V as the threshold Vdux.
　次に、時刻ｔ３において、キャリアＣ１のレベルと固定閾値Ｗｄｕ１とが一致したとき、比較器４３Ｗは、出力信号Ｃｐｗの論理レベルを反転する（例えば、ローレベルからハイレベルに切り替える）。これにより、ＰＷＭ回路４４は、Ｗ相のＰＷＭ信号Ｗをハイレベルからローレベルに切り替えるとともに、閾値切替部４２Ｗが、固定閾値Ｗｄｕ２を選択し、閾値Ｗｄｕｘとして比較器４３Ｗに与える。また、このとき、キャリアＣ１のレベルが固定閾値Ｕｄｕ２（＝Ｗｄｕ１）とも一致するため、比較器４３Ｕは、出力信号Ｃｐｕの論理レベルを反転する（例えば、ローレベルからハイレベルに切り替える）。これにより、ＰＷＭ回路４４は、Ｗ相のＰＷＭ信号Ｗをローレベルからハイレベルに切り替える。 Next, at time t3, when the level of the carrier C1 and the fixed threshold value Wdu1 match, the comparator 43W inverts the logical level of the output signal Cpw (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the W-phase PWM signal W from the high level to the low level, and the threshold switching unit 42W selects the fixed threshold value Wdu2 and gives it to the comparator 43W as the threshold value Wdux. Further, at this time, since the level of the carrier C1 also matches the fixed threshold value Udu2 (= Wdu1), the comparator 43U inverts the logical level of the output signal Cpu (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the W-phase PWM signal W from the low level to the high level.
　次に、時刻ｔ４において、キャリアＣ１のレベルと固定閾値Ｖｄｕ２とが一致したとき、比較器４３Ｖは、出力信号Ｃｐｖの論理レベルを反転する（例えば、ローレベルからハイレベルに切り替える）。これにより、ＰＷＭ回路４４は、Ｖ相のＰＷＭ信号Ｖをローレベルからハイレベルに切り替える。 Next, at time t4, when the level of the carrier C1 and the fixed threshold value Vdu2 match, the comparator 43V inverts the logical level of the output signal Cpv (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the V-phase PWM signal V from the low level to the high level.
　次に、時刻ｔ５において、キャリアＣ１のレベルと固定閾値Ｗｄｕ２とが一致したとき、比較器４３Ｗは、出力信号Ｃｐｗの論理レベルを反転する（例えば、ローレベルからハイレベルに切り替える）。これにより、ＰＷＭ回路４４は、Ｗ相のＰＷＭ信号Ｗをローレベルからハイレベルに切り替える。 Next, at time t5, when the level of the carrier C1 and the fixed threshold value Wdu2 match, the comparator 43W inverts the logical level of the output signal Cpw (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the W-phase PWM signal W from the low level to the high level.
　その後、時刻ｔ６において、キャリアＣ１の生成が終了し、キャリアＣ２の生成が開始されるとき、切替制御部１５が制御信号Ｓｃをローレベルからハイレベルに切り替える。閾値切替部４２Ｕ，４２Ｖ，４２Ｗは、ハイレベルの制御信号Ｓｃに応じて、可変閾値Ｕｄｕ３，Ｖｄｕ３，Ｗｄｕ３を選択し、閾値Ｕｄｕｘ，Ｖｄｕｘ，Ｗｄｕｘとして比較器４３Ｕ，４３Ｖ，４３Ｗにそれぞれ与える。これにより、第２期間Ｂ（キャリアＣ２が生成されている期間）において、比較器４３Ｕ，４３Ｖ，４３Ｗは、キャリアＣ２と可変閾値Ｕｄｕ３，Ｖｄｕ３，Ｗｄｕ３を比較する。 After that, at time t6, when the generation of the carrier C1 is completed and the generation of the carrier C2 is started, the switching control unit 15 switches the control signal Sc from the low level to the high level. The threshold switching units 42U, 42V, and 42W select variable thresholds Udu3, Vdu3, and Wdu3 according to the high-level control signal Sc, and give them to the comparators 43U, 43V, and 43W as thresholds Udux, Vdux, and Wdux, respectively. As a result, in the second period B (the period during which the carrier C2 is generated), the comparators 43U, 43V, 43W compare the carrier C2 with the variable threshold values Udu3, Vdu3, Wdu3.
　時刻ｔ７において、キャリアＣ２のレベルと可変閾値Ｕｄｕ３とが一致したとき、比較器４３Ｕは、出力信号Ｃｐｕの論理レベルを反転する（例えば、ハイレベルからローレベルに切り替える）。これにより、ＰＷＭ回路４４は、Ｕ相のＰＷＭ信号Ｕをハイレベルからローレベルに切り替えるとともに、閾値切替部４２Ｕが、可変閾値Ｕｄｕ４を選択し、閾値Ｕｄｕｘとして比較器４３Ｕに与える。 At time t7, when the level of the carrier C2 and the variable threshold value Udu3 match, the comparator 43U inverts the logical level of the output signal Cpu (for example, switching from a high level to a low level). As a result, the PWM circuit 44 switches the U-phase PWM signal U from the high level to the low level, and the threshold switching unit 42U selects the variable threshold value Udu4 and gives it to the comparator 43U as the threshold value Udux.
　次に、時刻ｔ８において、キャリアＣ２のレベルと可変閾値Ｖｄｕ３とが一致したとき、比較器４３Ｖは、出力信号Ｃｐｖの論理レベルを反転する（例えば、ローレベルからハイレベルに切り替える）。これにより、ＰＷＭ回路４４は、Ｖ相のＰＷＭ信号Ｖをハイレベルからローレベルに切り替えるとともに、閾値切替部４２Ｖが、可変閾値Ｖｄｕ４を選択し、閾値Ｖｄｕｘとして比較器４３Ｖに与える。 Next, at time t8, when the level of the carrier C2 and the variable threshold value Vdu3 match, the comparator 43V inverts the logical level of the output signal Cpv (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the V-phase PWM signal V from the high level to the low level, and the threshold switching unit 42V selects the variable threshold Vdu4 and gives it to the comparator 43V as the threshold Vdux.
　次に、時刻ｔ９において、キャリアＣ２のレベルと可変閾値Ｗｄｕ３とが一致したとき、比較器４３Ｗは、出力信号Ｃｐｗの論理レベルを反転する（例えば、ローレベルからハイレベルに切り替える）。これにより、ＰＷＭ回路４４は、Ｗ相のＰＷＭ信号Ｗをハイレベルからローレベルに切り替えるとともに、閾値切替部４２Ｗが、可変閾値Ｗｄｕ４を選択し、閾値Ｗｄｕｘとして比較器４３Ｗに与える。 Next, at time t9, when the level of the carrier C2 and the variable threshold value Wdu3 match, the comparator 43W inverts the logical level of the output signal Cpw (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the W-phase PWM signal W from the high level to the low level, and the threshold switching unit 42W selects the variable threshold value Wdu4 and gives it to the comparator 43W as the threshold value Wdux.
　次に、時刻ｔ１０において、キャリアＣ２のレベルと可変閾値Ｕｄｕ４とが一致したとき、比較器４３Ｕは、出力信号Ｃｐｕの論理レベルを反転する（例えば、ローレベルからハイレベルに切り替える）。これにより、ＰＷＭ回路４４は、Ｕ相のＰＷＭ信号Ｕをローレベルからハイレベルに切り替える。 Next, at time t10, when the level of the carrier C2 and the variable threshold value Udu4 match, the comparator 43U inverts the logical level of the output signal Cpu (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the U-phase PWM signal U from low level to high level.
　次に、時刻ｔ１１において、キャリアＣ２のレベルと可変閾値Ｖｄｕ４とが一致したとき、比較器４３Ｖは、出力信号Ｃｐｖの論理レベルを反転する（例えば、ローレベルからハイレベルに切り替える）。これにより、ＰＷＭ回路４４は、Ｖ相のＰＷＭ信号Ｗをローレベルからハイレベルに切り替える。 Next, at time t11, when the level of the carrier C2 and the variable threshold value Vdu4 match, the comparator 43V inverts the logical level of the output signal Cpv (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the V-phase PWM signal W from the low level to the high level.
　次に、時刻ｔ１２において、キャリアＣ２のレベルと可変閾値Ｗｄｕ４とが一致したとき、比較器４３Ｗは、出力信号Ｃｐｗの論理レベルを反転する（例えば、ローレベルからハイレベルに切り替える）。これにより、ＰＷＭ回路４４は、Ｗ相のＰＷＭ信号Ｗをローレベルからハイレベルに切り替える。 Next, at time t12, when the level of the carrier C2 and the variable threshold value Wdu4 match, the comparator 43W inverts the logical level of the output signal Cpw (for example, switching from the low level to the high level). As a result, the PWM circuit 44 switches the W-phase PWM signal W from the low level to the high level.
　その後、時刻ｔ１３において、キャリアＣ２の生成が終了し、キャリアＣ１の生成が開始されるとき、切替制御部１５が制御信号Ｓｃをハイレベルからローレベルに切り替える。閾値切替部４２Ｕ，４２Ｖ，４２Ｗは、ローレベルの制御信号Ｓｃに応じて、固定閾値Ｕｄｕ１，Ｖｄｕ１，Ｗｄｕ１を選択し、閾値Ｕｄｕｘ，Ｖｄｕｘ，Ｗｄｕｘとしてそれぞれ出力する。その後は、時刻ｔ０からｔ１２までと同様の処理により、各相のＰＷＭ信号が繰り返し生成される。 After that, at time t13, when the generation of the carrier C2 is completed and the generation of the carrier C1 is started, the switching control unit 15 switches the control signal Sc from the high level to the low level. The threshold switching units 42U, 42V, and 42W select fixed thresholds Udu1, Vdu1, and Wdu1 according to the low-level control signal Sc, and output them as thresholds Udux, Vdux, and Wdux, respectively. After that, the PWM signals of each phase are repeatedly generated by the same processing as from time t0 to t12.
　図５に示すように、各相のＰＷＭ信号が生成されることにより、ゼロベクトル区間Ｔｚ内に通電区間Ｔ１２，Ｔ２３，Ｔ３４，Ｔ４５が発生する。図５において、参照符号５０１は、本実施の形態に係るモータ制御装置１００によって生成するＰＷＭ信号のゼロベクトル区間Ｔｚ内に通電区間Ｔ１２，Ｔ２３，Ｔ３４，Ｔ４５が発生した場合のモータ４の電流の波形を示し、参照符号５０２は、ゼロベクトル区間に通電期間が発生しなかった場合のモータ４の電流の波形を示している。 As shown in FIG. 5, the PWM signals of each phase are generated, so that the energized sections T12, T23, T34, and T45 are generated in the zero vector section Tz. In FIG. 5, reference numeral 501 indicates the current of the motor 4 when the energized sections T12, T23, T34, and T45 are generated in the zero vector section Tz of the PWM signal generated by the motor control device 100 according to the present embodiment. The waveform is shown, and reference numeral 502 shows the waveform of the current of the motor 4 when the energization period does not occur in the zero vector section.
　図５に示すように、ＰＷＭ信号Ｕ，Ｖ，Ｗのゼロベクトル区間Ｔｚ内に通電区間が発生しなかった場合、参照符号５００に示すように、時刻ｔ０から時刻ｔ７までのゼロベクトル区間Ｔｚにおいて、モータ４の電流が減少する。 As shown in FIG. 5, when the energization section does not occur in the zero vector section Tz of the PWM signals U, V, W, in the zero vector section Tz from time t0 to time t7 as shown by reference numeral 500. , The current of the motor 4 is reduced.
　これに対し、ＰＷＭ信号Ｕ，Ｖ，Ｗのゼロベクトル区間Ｔｚ内に通電区間Ｔ１２，Ｔ２３，Ｔ３４，Ｔ４５を設けた場合、参照符号５０１に示すように、時刻ｔ１から時刻ｔ５までの期間においてモータ電流が増加する。これにより、時刻ｔ７においてゼロベクトル区間Ｔｚが終了した時点でのモータ４の電流は、ＰＷＭ信号Ｕ，Ｖ，Ｗのゼロベクトル区間Ｔｚ内に通電区間を設けなかった場合に比べて、大きくなる。 On the other hand, when the energized sections T12, T23, T34, and T45 are provided in the zero vector section Tz of the PWM signals U, V, W, the motor is provided in the period from time t1 to time t5 as shown by reference numeral 501. The current increases. As a result, the current of the motor 4 at the end of the zero vector section Tz at time t7 becomes larger than that in the case where the energization section is not provided in the zero vector section Tz of the PWM signals U, V, W.
　すなわち、ゼロベクトル区間Ｔｚの開始時点から終了時点までの電流の変化量が、ＰＷＭ信号Ｕ，Ｖ，Ｗのゼロベクトル区間Ｔｚ内に通電区間を設けなかった場合に比べて小さくなるので、大きな電流リップルの発生を防止することができる。換言すれば、ＰＷＭ信号Ｕ，Ｖ，Ｗのゼロベクトル区間Ｔｚ内に通電区間Ｔ１２，Ｔ２３，Ｔ３４，Ｔ４５を発生させて、ゼロベクトル区間中に小さな電流リップルを複数発生させることにより、大きな電流リップルの発生を抑制することができる。 That is, the amount of change in the current from the start time to the end time of the zero vector section Tz is smaller than that when the energization section is not provided in the zero vector section Tz of the PWM signals U, V, W, so that a large current It is possible to prevent the occurrence of ripple. In other words, the energized sections T12, T23, T34, and T45 are generated in the zero vector section Tz of the PWM signals U, V, W, and a plurality of small current ripples are generated in the zero vector section to generate a large current ripple. Can be suppressed.
　次に、本実施の形態に係るモータ制御装置１００によるモータ駆動制御処理の流れについて説明する。 Next, the flow of the motor drive control process by the motor control device 100 according to the present embodiment will be described.
　図６は、実施の形態に係るモータ制御装置１００によるモータ駆動制御処理の流れを示すフローチャートである。 FIG. 6 is a flowchart showing the flow of the motor drive control process by the motor control device 100 according to the embodiment.
　例えば、上位装置（図示せず）からモータ４の回転速度指令ωｒｅｆが入力されたとき、モータ制御装置１００は、モータ４の駆動制御を開始する。先ず、モータ制御装置１００は、モータ４を駆動するための通電パターンの生成処理を開始する（ステップＳ１０）。具体的には、デューティ比設定部３９がＵ相、Ｖ相、Ｗ相の各デューティ比Ｕｄｕ，Ｖｄｕ，Ｗｄｕの初期値を設定するとともに、キャリア発生部３７がキャリアＣ１，Ｃ２を生成し、ＰＷＭ信号生成部３２が、キャリアＣ１，Ｃ２と初期値として設定されたデューティ比Ｕｄｕ，Ｖｄｕ，Ｗｄｕとに基づいて、上述した手法により、モータ４の通電パターンを指定する６種類のＰＷＭ信号を生成し、モータ４に与える。 For example, when the rotation speed command ωref of the motor 4 is input from the host device (not shown), the motor control device 100 starts the drive control of the motor 4. First, the motor control device 100 starts a process of generating an energization pattern for driving the motor 4 (step S10). Specifically, the duty ratio setting unit 39 sets the initial values of the U-phase, V-phase, and W-phase duty ratios Udu, Vdu, and Wdu, and the carrier generation unit 37 generates carriers C1 and C2, and PWM. The signal generation unit 32 generates 6 types of PWM signals that specify the energization pattern of the motor 4 by the above-mentioned method based on the carriers C1 and C2 and the duty ratios Udu, Vdu, and Wdu set as initial values. , Give to the motor 4.
　次に、モータ制御装置１００は、Ｕ，Ｖ，Ｗ各相の相電流Ｉｕ，Ｉｖ，Ｉｗを計測する（ステップＳ１１）。次に、ベクトル制御部３０が、ステップＳ１１において電流検出部２７により検出された３相電流Ｉｕ，Ｉｖ，Ｉｗの電流算出値に基づいて、ＰＩ制御等の電流制御を行い（ステップＳ１２）、各相の相電圧指令Ｖｕ＊，Ｖｖ＊，Ｖｗ＊（制御量）を算出する（ステップＳ１３）。 Next, the motor control device 100 measures the phase currents Iu, Iv, and Iw of each of the U, V, and W phases (step S11). Next, the vector control unit 30 performs current control such as PI control based on the current calculation values of the three-phase currents Iu, Iv, and Iw detected by the current detection unit 27 in step S11 (step S12). The phase voltage commands Vu *, Vv *, and Vw * (control amount) of the phase are calculated (step S13).
　次に、デューティ比設定部３９が、ステップＳ１３で算出された各相の相電圧指令Ｖｕ＊，Ｖｖ＊，Ｖｗ＊に基づいて、各相のデューティ比を更新する（ステップＳ１４）。具体的には、デューティ比設定部３９が相電圧指令Ｖｕ＊，Ｖｖ＊，Ｖｗ＊に基づいて、デューティ比Ｕｄｕ，Ｖｄｕ，Ｗｄｕを算出し、可変閾値算出部４１が、算出されたデューティ比Ｕｄｕ，Ｖｄｕ，Ｗｄｕに基づいて、上述した手法により、可変閾値Ｕｄｕ３，Ｕｄｕ４，Ｖｄｕ３，Ｖｄｕ４，Ｗｄｕ３，Ｗｄｕ４を更新する。 Next, the duty ratio setting unit 39 updates the duty ratio of each phase based on the phase voltage commands Vu *, Vv *, Vw * of each phase calculated in step S13 (step S14). Specifically, the duty ratio setting unit 39 calculates the duty ratios Udu, Vdu, Wdu based on the phase voltage commands Vu *, Vv *, Vw *, and the variable threshold value calculation unit 41 calculates the calculated duty ratio Udu. , Vdu, Wdu, and the variable thresholds Udu3, Udu4, Vdu3, Vdu4, Wdu3, Wdu4 are updated by the above-mentioned method.
　次に、ＰＷＭ信号生成部３２が、上述した手法により、更新されたデューティ比に対応する固定閾値Ｕｄｕ１，Ｕｄｕ２，Ｖｄｕ１，Ｖｄｕ２，Ｗｄｕ１，Ｗｄｕ２と可変閾値Ｕｄｕ３，Ｕｄｕ４，Ｖｄｕ３，Ｖｄｕ４，Ｗｄｕ３，Ｗｄｕ４とに基づいて、上述した手法（図５参照）により、ＰＷＭ信号Ｕ，Ｖ，Ｗを生成する（ステップＳ１５）。 Next, the PWM signal generation unit 32 has a fixed threshold value Udu1, Udu2, Vdu1, Vdu2, Wdu1, Wdu2 and a variable threshold value Udu3, Udu4, Vdu3, Vdu4, Wdu3, Wdu4 corresponding to the updated duty ratio by the method described above. Based on the above, PWM signals U, V, and W are generated by the above-mentioned method (see FIG. 5) (step S15).
　その後、モータ制御装置１００は、上位装置からモータの停止指令が入力されたか否かを判定する（ステップＳ１６）。モータの停止指令が入力された場合には、モータ制御装置１００はＰＷＭ信号の生成を停止して、モータ４の駆動を停止する。 After that, the motor control device 100 determines whether or not a motor stop command has been input from the host device (step S16). When the motor stop command is input, the motor control device 100 stops the generation of the PWM signal and stops the driving of the motor 4.
　一方、モータの停止指示が入力されていない場合には、モータ制御装置１００は、ステップＳ１１に移行し、モータの停止指令が入力されるまで、上述の処理（Ｓ１１～Ｓ１６）を繰り返し実行する。 On the other hand, when the motor stop instruction is not input, the motor control device 100 proceeds to step S11 and repeatedly executes the above processes (S11 to S16) until the motor stop command is input.
　以上、本実施の形態に係るモータ制御装置１００は、モータ４の各相に対応するＰＷＭ信号Ｕ，Ｖ，Ｗの信号レベルが一致するゼロベクトル区間が発生する場合に、ゼロベクトル区間内にモータ４の通電区間を設ける。
　これによれば、上述したように、ゼロベクトル区間中に小さな電流リップルを複数発生させて、大きな電流リップルの発生を抑制することができるので、大きな電流リップルの周期的変化に起因するモータの動作時の騒音を抑制することが可能となる。 As described above, the motor control device 100 according to the present embodiment is a motor within the zero vector section when a zero vector section in which the signal levels of the PWM signals U, V, and W corresponding to each phase of the motor 4 match is generated. The energization section of 4 is provided.
According to this, as described above, it is possible to generate a plurality of small current ripples in the zero vector interval and suppress the generation of large current ripples, so that the operation of the motor due to the periodic change of large current ripples. It is possible to suppress the noise of time.
　また、モータ制御装置１００は、ゼロベクトル区間において、各相のＰＷＭ信号Ｕ，Ｖ，Ｗを同じ時間だけ、互いに異なるタイミングで反転させることにより、モータ４の通電区間を発生させる（図５参照）。
　これによれば、ゼロベクトル区間に通電区間を発生させることによって、Ｕ相、Ｖ相、Ｗ相の各電圧が電圧指令と異なる電圧になることを防止することができ、上位装置から入力された回転速度指令ωｒｅｆに基づいたモータ４の適切な制御を実現しつつ、大きな電流リップルに起因する騒音の発生を防止することが可能となる。 Further, the motor control device 100 generates an energized section of the motor 4 by inverting the PWM signals U, V, W of each phase at different timings for the same time in the zero vector section (see FIG. 5). ..
According to this, by generating an energized section in the zero vector section, it is possible to prevent each voltage of the U phase, the V phase, and the W phase from becoming a voltage different from the voltage command, and it is input from the host device. It is possible to prevent the generation of noise due to a large current ripple while realizing appropriate control of the motor 4 based on the rotation speed command ωref.
　また、モータ制御装置１００は、ＰＷＭ周期の第１期間Ａにおいて、各相のＰＷＭ信号Ｕ，Ｖ，Ｗを一定時間、互いに異なるタイミングで反転させ、ＰＷＭ周期の残りの第２期間Ｂにおいて、設定されたデューティ比に基づいてＰＷＭ信号Ｕ，Ｖ，Ｗを反転させる。
　これによれば、ＰＷＭ周期が、ゼロベクトル区間内に通電区間を発生させるための第１期間Ａと、上位装置からの指令（回転速度指令ωｒｅｆ）に基づいてモータが回転するようにデューティ比を調整するための第２期間Ｂとに分けられているので、モータ４が回転速度指令ωｒｅｆに応じた回転速度で回転するように各相のＰＷＭ信号Ｕ，Ｖ，Ｗのデューティ比を調整しつつ、ゼロベクトル区間内にモータ４の通電区間を設けるように、ＰＷＭ信号を生成することが容易となる。 Further, the motor control device 100 inverts the PWM signals U, V, and W of each phase at different timings for a certain period of time in the first period A of the PWM cycle, and sets them in the remaining second period B of the PWM cycle. The PWM signals U, V, and W are inverted based on the calculated duty ratio.
According to this, the duty ratio is set so that the PWM cycle rotates the motor based on the first period A for generating the energized section in the zero vector section and the command (rotation speed command ωref) from the host device. Since it is divided into the second period B for adjustment, while adjusting the duty ratio of the PWM signals U, V, W of each phase so that the motor 4 rotates at the rotation speed according to the rotation speed command ωref. , The PWM signal can be easily generated so that the energized section of the motor 4 is provided in the zero vector section.
　また、モータ制御装置１００は、第１期間Ａに対応する周期を有するのこぎり波状のキャリアＣ１と、第２期間Ｂに対応する周期を有するのこぎり波状のキャリアＣ２とを生成し、固定閾値Ｕｄｕ１，Ｕｄｕ２，Ｖｄｕ１，Ｖｄｕ２，Ｗｄｕ１，Ｗｄｕ２とキャリアＣ１のレベルとの比較結果に基づいて、第１期間Ａにおける各相のＰＷＭ信号Ｕ，Ｖ，Ｗが反転するタイミングを決定し、算出されたデューティ比に基づいて設定された可変閾値Ｕｄｕ３，Ｕｄｕ４，Ｖｄｕ３，Ｖｄｕ４，Ｗｄｕ３，Ｗｄｕ４とキャリアＣ２のレベルとの比較結果に基づいて、第２期間Ｂにおける各相のＰＷＭ信号Ｕ，Ｖ，Ｗが反転するタイミングを決定する。 Further, the motor control device 100 generates a saw-like carrier C1 having a period corresponding to the first period A and a saw-like carrier C2 having a period corresponding to the second period B, and has fixed threshold values Udu1 and Udu2. , Vdu1, Vdu2, Wdu1, Wdu2 and the carrier C1 level are compared with each other to determine the timing at which the PWM signals U, V, W of each phase in the first period A are inverted, and the calculated duty ratio is calculated. Timing at which the PWM signals U, V, W of each phase in the second period B are inverted based on the comparison result between the variable threshold values Udu3, Udu4, Vdu3, Vdu4, Wdu3, Wdu4 and the carrier C2 level set based on the above. To determine.
　これによれば、キャリア毎に比較対象の閾値を変更し、第１期間Ａと第２期間Ｂのそれぞれの期間において適切なタイミングでＰＷＭ信号の信号レベルを反転させることにより、所望のＰＷＭ信号を容易に生成することができる。 According to this, the threshold value of the comparison target is changed for each carrier, and the signal level of the PWM signal is inverted at an appropriate timing in each of the first period A and the second period B to obtain a desired PWM signal. It can be easily generated.
　≪実施の形態の拡張≫
　以上、本発明者によってなされた発明を実施の形態に基づいて具体的に説明したが、本発明はそれに限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは言うまでもない。 ≪Expansion of embodiment≫
The invention made by the present inventor has been specifically described above based on the embodiments, but it goes without saying that the present invention is not limited thereto and can be variously modified without departing from the gist thereof. ..
　例えば、上記実施の形態では、ＰＷＭ周期において、前半に第１期間Ａを、後半に第２期間Ｂを設ける場合を例示したが、これに限られず、ＰＷＭ周期の前半に第２期間Ｂを、ＰＷＭ周期の後半に第１期間Ａを設けてもよい。 For example, in the above embodiment, the case where the first period A is provided in the first half and the second period B is provided in the second half of the PWM cycle is illustrated, but the present invention is not limited to this, and the second period B is provided in the first half of the PWM cycle. The first period A may be provided in the latter half of the PWM cycle.
　また、上述のフローチャートは、動作を説明するための一例を示すものであって、これに限定されない。すなわち、フローチャートの各図に示したステップは具体例であって、このフローに限定されるものではない。例えば、一部の処理の順番が変更されてもよいし、各処理間に他の処理が挿入されてもよいし、一部の処理が並列に行われてもよい。 Further, the above-mentioned flowchart shows an example for explaining the operation, and is not limited to this. That is, the steps shown in each figure of the flowchart are specific examples, and are not limited to this flow. For example, the order of some processes may be changed, other processes may be inserted between each process, and some processes may be performed in parallel.
　１…モータシステム、４…モータ、１２…カウント部、１３…上限値切替部、１４…比較器、１５…切替制御部、１６…上限値記憶部、２０…制御部、２１…直流電源、２２ａ…正側母線、２２ｂ…負側母線、２３…インバータ回路、２４…電流検出器（シャント抵抗）、２５Ｕ＋，２５Ｕ－，２５Ｖ＋，２５Ｖ－，２５Ｗ＋，２５Ｗ－…スイッチング素子、２７…電流検出部、３０…ベクトル制御部、３１…デューティ比算出部、３２…ＰＷＭ信号生成部、３３…駆動回路、３４…電流検出タイミング調整部、３５…通電パターン生成部、３６…クロック発生部、３７…キャリア発生部、３９…デューティ比設定部、４０…固定閾値記憶部、４１…可変閾値算出部、４２Ｕ，４２Ｖ，４２Ｗ…閾値切替部、４３Ｕ，４３Ｖ，４３Ｗ…比較器、４４…ＰＷＭ回路、４５…割り込みコントローラ、１００…モータ制御装置、Ａ…第１期間、Ｂ…第２期間、Ｃ，Ｃ１，Ｃ２…キャリア、ＣＬＫ…クロック、Ｃｐ…検出信号、Ｌｕ…Ｕ相コイル、Ｌｖ…Ｖ相コイル、Ｌｗ…Ｗ相コイル、Ｓｃ…制御信号、Ｓｄ…検出信号、Ｓｉ…割り込み信号、Ｃｐｕ，Ｃｐｖ，Ｃｐｗ…出力信号、Ｔ１…第１上限値、Ｔ２…第２上限値、Ｕｄｕ，Ｖｄｕ，Ｗｄｕ…デューティ比、Ｕｄｕ１，Ｖｄｕ１，Ｗｄｕ１、Ｕｄｕ２，Ｖｄｕ２，Ｗｄｕ２…固定閾値、Ｕｄｕ３，Ｖｄｕ３，Ｗｄｕ３、Ｕｄｕ４，Ｖｄｕ４，Ｗｄｕ４…可変閾値、ＵＨ，ＵＬ，ＶＨ，ＶＬ，ＷＨ，ＷＬ，Ｕ，Ｖ，Ｗ…ＰＷＭ信号。 1 ... motor system, 4 ... motor, 12 ... count unit, 13 ... upper limit value switching unit, 14 ... comparator, 15 ... switching control unit, 16 ... upper limit value storage unit, 20 ... control unit, 21 ... DC power supply, 22a ... Positive bus, 22b ... Negative bus, 23 ... Inverter circuit, 24 ... Current detector (shunt resistance), 25U +, 25U-, 25V +, 25V-, 25W +, 25W- ... Switching element, 27 ... Current detector, 30 ... Vector control unit, 31 ... Duty ratio calculation unit, 32 ... PWM signal generation unit, 33 ... Drive circuit, 34 ... Current detection timing adjustment unit, 35 ... Energization pattern generation unit, 36 ... Clock generation unit, 37 ... Carrier generation Unit, 39 ... duty ratio setting unit, 40 ... fixed threshold storage unit, 41 ... variable threshold calculation unit, 42U, 42V, 42W ... threshold switching unit, 43U, 43V, 43W ... comparer, 44 ... PWM circuit, 45 ... interrupt Controller, 100 ... Motor control device, A ... 1st period, B ... 2nd period, C, C1, C2 ... Carrier, CLK ... Clock, Cp ... Detection signal, Lu ... U phase coil, Lv ... V phase coil, Lw ... W phase coil, Sc ... control signal, Sd ... detection signal, Si ... interrupt signal, Cpu, Cpv, Cpw ... output signal, T1 ... first upper limit value, T2 ... second upper limit value, Udu, Vdu, Wdu ... duty Ratio, Udu1, Vdu1, Wdu1, Udu2, Vdu2, Wdu2 ... Fixed threshold, Udu3, Vdu3, Wdu3, Udu4, Vdu4, Wdu4 ... Variable threshold, UH, UL, VH, VL, WH, WL, U, V, W ... PWM signal.

Claims (5)

  1. 　複数相のコイルを有するモータの各相にそれぞれ対応するＰＷＭ信号を生成する制御部と、
    　前記ＰＷＭ信号に基づいて、各相の前記コイルを駆動するインバータ回路と、を備え、
    　前記制御部は、各相の前記ＰＷＭ信号の信号レベルが一致する通電停止期間が発生する場合に、前記通電停止期間内に各相の前記コイルを通電させる通電期間を設ける
    　モータ制御装置。     A control unit that generates PWM signals corresponding to each phase of a motor having a multi-phase coil,
    An inverter circuit for driving the coil of each phase based on the PWM signal is provided.
    The control unit is a motor control device that provides an energization period for energizing the coil of each phase within the energization stop period when an energization stop period in which the signal levels of the PWM signals of each phase match occurs.
  2. 　請求項１に記載のモータ制御装置において、
    　前記制御部は、前記通電停止期間において、各相の前記ＰＷＭ信号を同じ時間だけ、互いに異なるタイミングで反転させる
    　モータ制御装置。     In the motor control device according to claim 1,
    The control unit is a motor control device that inverts the PWM signals of each phase at different timings for the same time during the energization stop period.
  3. 　請求項２に記載のモータ制御装置において、
    　前記制御部は、各相の前記ＰＷＭ信号のデューティ比を設定するデューティ比設定部と、前記デューティ比設定部によって設定された前記デューティ比に基づいて、各相の前記ＰＷＭ信号を生成するＰＷＭ信号生成部と、を有し、
    　各相の前記ＰＷＭ信号の１周期は、第１期間と残りの第２期間とを含み、
    　前記ＰＷＭ信号生成部は、前記第１期間において、各相の前記ＰＷＭ信号を一定時間、互いに異なるタイミングで反転させ、前記第２期間において、前記デューティ比に基づいて前記ＰＷＭ信号を反転させる
    　モータ制御装置。     In the motor control device according to claim 2,
    The control unit is a duty ratio setting unit that sets the duty ratio of the PWM signal of each phase, and a PWM signal that generates the PWM signal of each phase based on the duty ratio set by the duty ratio setting unit. Has a generator and
    One cycle of the PWM signal in each phase includes a first period and a remaining second period.
    The PWM signal generation unit inverts the PWM signals of each phase for a certain period of time at different timings in the first period, and inverts the PWM signals based on the duty ratio in the second period. apparatus.
  4. 　請求項３に記載のモータ制御装置において、
    　前記制御部は、前記第１期間に対応する周期を有するのこぎり波状の第１キャリアと、前記第２期間に対応する周期を有するのこぎり波状の第２キャリアとを生成するキャリア発生部を更に有し、
    　前記ＰＷＭ信号生成部は、固定値である第１閾値および第２閾値と前記第１キャリアのレベルとの比較結果に基づいて、前記第１期間における各相の前記ＰＷＭ信号が反転するタイミングを決定し、前記デューティ比に基づいて設定された第３閾値および第４閾値と前記第２キャリアのレベルとの比較結果に基づいて、前記第２期間における各相の前記ＰＷＭ信号が反転するタイミングを決定する
    　ことを特徴とするモータ制御装置。     In the motor control device according to claim 3,
    The control unit further includes a carrier generating unit that generates a saw-like first carrier having a period corresponding to the first period and a saw-like second carrier having a period corresponding to the second period. ,
    The PWM signal generation unit determines the timing at which the PWM signal of each phase in the first period is inverted based on the comparison result between the first threshold value and the second threshold value, which are fixed values, and the level of the first carrier. Then, based on the comparison result between the third threshold value and the fourth threshold value set based on the duty ratio and the level of the second carrier, the timing at which the PWM signal of each phase in the second period is inverted is determined. A motor control device characterized by
  5. 　請求項１乃至４の何れか一項に記載のモータ制御装置と、
    　前記モータと、
    　を備えるモータシステム。     The motor control device according to any one of claims 1 to 4.
    With the motor
    Motor system with.
PCT/JP2020/026342 2019-07-22 2020-07-06 Motor control device and motor system WO2021014948A1 (en)

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JP2010279141A (en) * 2009-05-28 2010-12-09 Omron Automotive Electronics Co Ltd Electric motor control device
JP4671000B1 (en) * 2009-09-28 2011-04-13 ダイキン工業株式会社 Phase current detection device and power conversion device using the same
WO2011064970A1 (en) * 2009-11-26 2011-06-03 パナソニック株式会社 Load drive system, electric motor drive system and vehicle control system
JP2013162536A (en) * 2012-02-01 2013-08-19 Mitsubishi Electric Corp Power conversion device
WO2017154239A1 (en) * 2016-03-11 2017-09-14 日立オートモティブシステムズ株式会社 Motor drive device and method for detecting phase current in motor drive device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010279141A (en) * 2009-05-28 2010-12-09 Omron Automotive Electronics Co Ltd Electric motor control device
JP4671000B1 (en) * 2009-09-28 2011-04-13 ダイキン工業株式会社 Phase current detection device and power conversion device using the same
WO2011064970A1 (en) * 2009-11-26 2011-06-03 パナソニック株式会社 Load drive system, electric motor drive system and vehicle control system
JP2013162536A (en) * 2012-02-01 2013-08-19 Mitsubishi Electric Corp Power conversion device
WO2017154239A1 (en) * 2016-03-11 2017-09-14 日立オートモティブシステムズ株式会社 Motor drive device and method for detecting phase current in motor drive device

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