JP2010279141A - Electric motor control device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electric motor control device that detects the current value of each phase with high accuracy by using a single current detector, and can also speed up its processing, without needing any decision about whether it is possible to detect a current, a calculation of timing for current detection, etc. <P>SOLUTION: The electric motor control device compares the magnitudes of duty set values of each phase, and decides the maximum phase, the middle phase, and the minimum phase, and on the basis of the phase Y of rise of a carrier signal of the middle phase, it advances the phase of rise of the carrier signal of the maximum phase by a certain quantity, and also delays the phase of rise of the carrier signal of the minimum phase by a certain quantity. Based on the carrier signals of each phase with their phases slipped off each other and the duty set values of each phase, it generates PWM signals of each phase, and detects currents in predetermined sections Tu and Tw up to a rise of each of the PWM signal of middle phase and the PWM signal of the minimum phase. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electric motor control device that controls an electric motor such as a three-phase brushless motor, and more particularly to current detection of each phase in PWM (Pulse Width Modulation) control.

  In general, a motor control device using a PWM control system includes a drive circuit in which a plurality of pairs of upper and lower arms each having a switching element are provided on an upper arm and a lower arm, and each switching is performed by a PWM signal of each phase having a predetermined duty. The elements are individually turned on and off to control the electric motor. Further, a current detector for detecting the current value of each phase of the motor is provided, and the PWM signal of each phase is determined based on the target current value of each phase and the current value of each phase detected by the current detector. A duty setting value corresponding to the duty is set. A PWM signal is generated based on the duty setting value and the carrier signal (carrier wave) of each phase having a predetermined frequency. The interval between “H” (High) and “L” (Low) of the PWM signal is determined by whether the level of the carrier signal is greater than or less than the duty setting value. An electric motor control device using PWM control is described in, for example, Patent Documents 1 to 5 described later.

  In such an electric motor control device, when the current detector attempts to measure a current value at a predetermined time, an interval of timing at which the switching element is turned on / off between one phase and the other phase. May be very short. At this time, accurate current measurement cannot be performed due to the fact that the current required for current detection does not flow through the switching element, the presence of dead time (dead zone), and the response delay of the circuit. When an A / D converter is used as a current detector, signals of the same magnitude must be continuously input for a certain period (for example, 2 μs or more) in order for A / D conversion to be performed normally. Unless a stable signal is continuously input, the A / D converter cannot detect an accurate current value of each phase.

  As a means for coping with the above problem, there is a method of shifting the phase of the PWM signal when the interval of the ON / OFF timing of the switching element between one phase and the other phase is shorter than a threshold value. By shifting the phase of the PWM signal in this way, the interval between the on and off timings is increased, so that a stable signal is input to the current detector, and the current can be measured. A technique relating to such a phase shift of the PWM signal is described in Patent Document 5, for example.

JP 2007-112416 A JP-A-10-155278 JP-T-2005-53270 JP 2001-95279 A US Pat. No. 6,735,537

  However, in the motor control device that drives the motor based on the PWM signal, it is difficult to accurately detect the current value of each phase using a single current detector without changing the duty of each phase. Is still not resolved.

  At the time of current detection, when the PWM signal rise or fall time interval is shortened between one phase and the other, current detection is possible by shifting the phase of the PWM signal as described above. Become. However, in this case, it is necessary to always determine whether or not current detection is possible from the duty setting value of the PWM signal, and to calculate the phase shift amount. Further, it is necessary to calculate and set the current detection timing again so that the current can be detected according to the result of the calculated phase shift amount. For this reason, the calculation amount becomes enormous, the load on the CPU constituting the control unit increases, and there is a limit to speeding up the processing.

  Therefore, an object of the present invention is to detect the current value of each phase with high accuracy using a single current detection means, and not to determine whether current detection is possible or to calculate the current detection timing, thereby reducing the load on the CPU. An object of the present invention is to provide an electric motor control device that can be reduced.

  In the motor control device according to the present invention, three pairs of upper and lower arms each having switching elements on the upper arm and the lower arm are provided, and the three-phase motor is driven based on the on / off operation of each switching element by the PWM signal. Based on the driving means, the single current detection means for detecting the current value of each phase of the three-phase motor, the target current value of each phase and the current value of each phase detected by the current detection means, The duty setting means for setting the duty setting value according to the duty of the PWM signal, the carrier signal generating means for generating the carrier signal, and the duty setting value of each phase set by the duty setting means are compared to set the duty A comparator that determines the largest phase with the largest value, the middle phase with the middle duty setting value, and the smallest phase with the smallest duty setting value. And the rising phase of the carrier signal corresponding to the maximum phase based on the carrier signal generated by the carrier signal generating means and the comparison result by the comparing means, than the rising phase of the carrier signal corresponding to the intermediate phase. The rising phase of the carrier signal corresponding to the minimum phase is based on the maximum phase shift means that advances the current-detectable constant amount, the carrier signal generated by the carrier signal generation means, and the comparison result by the comparison means. A minimum phase shift means for delaying the current signal by a fixed amount from the rising phase of the carrier signal corresponding to the intermediate phase, and a carrier signal for each phase whose phases are shifted from each other by the maximum phase shift means and the minimum phase shift means; Based on the duty setting value of each phase set by the duty setting means, a PWM signal for each phase is generated and output to the driving means. And a PWM signal generating means. Then, the current detection means performs current detection in a predetermined section until each rising edge of the PWM signal corresponding to the intermediate phase and the PWM signal corresponding to the minimum phase.

  In this way, with respect to the phase with the maximum duty on the basis of the rising phase of the carrier signal corresponding to the intermediate phase, the phase of the carrier signal is the amount of time considering the time required for current detection, dead time, etc. Shift forward (phase advances). For the phase with the minimum duty, the phase of the carrier signal is shifted backward by the amount of time (the phase is delayed). As a result, the current detection time is reliably ensured by the phase shift, and each phase current can be accurately detected using a single current detection means. In addition, since the current detection timing is determined based on the rising edges of the intermediate-phase PWM signal and the minimum-phase PWM signal, the detection timing can always be set to a fixed position. For this reason, it is not necessary to perform current detection feasibility determination, phase shift amount calculation, and current detection timing calculation each time, and the processing becomes extremely simple.

  Furthermore, the phase of the phase with the maximum duty is advanced by a certain amount, and the phase of the phase with the smallest duty is delayed by a certain amount, so that sufficient time for current detection can be ensured while the “H” (High) ) The overlap time of the period can be as large as possible. As a result, unnecessary current flowing into and out of the switching circuit is reduced as much as possible, and as a result, an accompanying effect that the amount of heat generated by the electronic component can be suppressed is also obtained.

  In the present invention, instead of shifting the phase based on the rising phase of the carrier signal corresponding to the intermediate phase as described above, the phase is shifted based on the rising phase of the carrier signal corresponding to the maximum phase. Also good. Alternatively, the phase may be shifted with reference to the rising phase of the carrier signal corresponding to the minimum phase.

  In the present invention, the phase of the PWM signal may be shifted instead of shifting the phase of the carrier signal as described above. Also in this case, as in the case of the carrier signal, the method based on the phase of the PWM signal corresponding to the intermediate phase, the method based on the phase of the PWM signal corresponding to the maximum phase, and the PWM signal corresponding to the minimum phase Any of the methods based on the phase can be employed.

  In the above case, when the duty setting values of the two phases other than the maximum phase among the duty setting values set by the duty setting means are equal, one of the phases is determined as the intermediate phase by the comparison means, and the other This phase may be determined as the minimum phase.

  The present invention can also be realized as a device for controlling not only a three-phase motor but also a multi-phase motor having four or more phases. In this case, the motor control device is provided with a plurality of pairs of upper and lower arms each having switching elements on the upper arm and the lower arm in accordance with the number of phases of four or more phases, and the on / off operation of each switching element by the PWM signal Drive means for driving the multiphase motor based on the single phase current detection means for detecting the current value of each phase of the multiphase motor, the target current value of each phase and the current detection means for each phase detected by the current detection means Based on the current value, duty setting means for setting a duty setting value according to the duty of the PWM signal of each phase, carrier signal generation means for generating a carrier signal, and duty of each phase set by the duty setting means Comparing the setting value and determining the order of the magnitude of the duty setting value, the carrier signal generated by the carrier signal generating means and the comparing means Based on the comparison result, the rising phase of the carrier signal corresponding to each phase other than the maximum phase is set to the magnitude of the duty setting value with reference to the rising phase of the carrier signal corresponding to the maximum phase having the largest duty setting value. The phase shift means for delaying the current detection by a fixed amount in sequence according to the rank, the carrier signal of each phase shifted from each other by the phase shift means, and the duty setting value of each phase set by the duty setting means And a PWM signal generation means for generating a PWM signal for each phase and outputting the PWM signal to the drive means. Then, the current detection means performs current detection in a predetermined section until the rise of the PWM signal corresponding to each phase other than the maximum phase.

  In the present invention, instead of shifting the phase based on the rising phase of the carrier signal corresponding to the maximum phase as described above, the phase is shifted based on the rising phase of the carrier signal corresponding to the minimum phase. Also good. Alternatively, the phase may be shifted with reference to the rising phase of the carrier signal corresponding to an arbitrary intermediate phase.

  In the present invention, the phase of the PWM signal may be shifted instead of shifting the phase of the carrier signal as described above. In this case, as in the case of the carrier signal, a method based on the phase of the PWM signal corresponding to the maximum phase, a method based on the phase of the PWM signal corresponding to the minimum phase, and a PWM corresponding to an arbitrary intermediate phase Any of the methods based on the phase of the signal can be employed.

  In the above case, when there is an equal duty setting value among the duty setting values set by the duty setting means, a different order may be determined for the duty setting value.

  According to the present invention, since the current detection time can be sufficiently secured by the phase shift, each phase current can be accurately detected using a single current detection means, and the current detection is always performed at a fixed timing. As a result, determination of whether or not current detection is possible, calculation of current detection timing, and the like are unnecessary, and the load on the CPU can be reduced.

It is a circuit block diagram of the electric motor control apparatus with which this invention is applied. It is a block diagram which shows the electric motor control apparatus of 1st Embodiment. It is a figure explaining the principle which produces | generates a PWM signal from a carrier signal. It is a flowchart which shows the electric current detection procedure in 1st Embodiment. 3 is a timing chart of a carrier signal and a PWM signal in the first embodiment. It is a circuit diagram for demonstrating the detection of U-phase current. It is a circuit diagram for explaining detection of a W phase current. It is a block diagram which shows the electric motor control apparatus of 2nd Embodiment. It is a flowchart which shows the electric current detection procedure in 2nd Embodiment. It is a timing chart of a carrier signal and a PWM signal in the second embodiment. It is a block diagram which shows the electric motor control apparatus of 3rd Embodiment. It is a flowchart which shows the electric current detection procedure in 3rd Embodiment. It is a timing chart of a carrier signal and a PWM signal in a 3rd embodiment. It is a block diagram which shows the electric motor control apparatus of 4th Embodiment. It is a flowchart which shows the electric current detection procedure in 4th Embodiment. It is a timing chart of a carrier signal and a PWM signal in a 4th embodiment. It is a block diagram which shows the electric motor control apparatus of 5th Embodiment. It is a flowchart which shows the electric current detection procedure in 5th Embodiment. It is a timing chart of a carrier signal and a PWM signal in a 5th embodiment. It is a block diagram which shows the electric motor control apparatus of 6th Embodiment. It is a flowchart which shows the electric current detection procedure in 6th Embodiment. It is a timing chart of a carrier signal and a PWM signal in a 6th embodiment. It is a timing chart of the carrier signal in a 7th embodiment. It is a timing chart of the PWM signal in 7th Embodiment. It is a timing chart of the carrier signal in an 8th embodiment. It is a timing chart of the PWM signal in 8th Embodiment. It is a timing chart of the carrier signal in a 9th embodiment. It is a timing chart of the PWM signal in 9th Embodiment. It is a timing chart of the PWM signal in 10th Embodiment. It is a timing chart of the PWM signal in 11th Embodiment. It is a timing chart of the PWM signal in 12th Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a circuit configuration diagram of an electric motor control device to which the present invention is applied. The power supply circuit 1 includes a rectifier circuit, a smoothing circuit, and the like, and a capacitor C is connected to the output end. The switching circuit 2 includes a three-phase bridge in which a pair of upper and lower arms is provided in three sets corresponding to the U phase, the V phase, and the W phase. The U-phase upper arm A1 has a switching element Q1, and the U-phase lower arm A2 has a switching element Q2. The V-phase upper arm A3 has a switching element Q3, and the V-phase lower arm A4 has a switching element Q4. The W-phase upper arm A5 has a switching element Q5, and the W-phase lower arm A6 has a switching element Q6. These switching elements Q1 to Q6 are composed of, for example, FET (Field Effect Transistor).

  The driver IC 3 outputs a PWM signal of each phase for individually turning on / off the switching elements Q1 to Q6 to the gates of the switching elements Q1 to Q6. When the switching elements Q1 to Q6 are turned on / off, a three-phase voltage is supplied from the switching circuit 2 to the motor (electric motor) M, and the motor M rotates. The motor M is a three-phase brushless motor used in, for example, an electric power steering device for a vehicle. A current detection resistor R for detecting a current flowing through the motor M is connected between the power supply circuit 1 and the switching circuit 2. An amplifier circuit 5 composed of a differential amplifier or the like amplifies the voltage across the current detection resistor R and outputs the amplified voltage to the CPU 4 as a detected current value. The CPU 4 calculates a duty setting value corresponding to the duty of the PWM signal of each phase based on the detected current value given from the amplifier circuit 5 and the target current value. Then, the PWM signal of each phase generated based on the duty setting value and the sawtooth carrier signal is supplied to the driver IC 3.

  FIG. 2 is a block diagram showing the electric motor control device of the first embodiment (corresponding to claim 1) of the present invention. The carrier signal generation means 10 generates a sawtooth carrier signal for each phase having a predetermined frequency. The duty setting means 11 sets a duty setting value corresponding to the duty of the PWM signal of each phase based on the target current value of each phase and the current value of each phase detected by the current detection means 17. The comparing means 12 compares the duty setting values of the respective phases set by the duty setting means 11, and the maximum phase having the largest duty setting value, the intermediate phase having the middle duty setting value, and the duty setting. Determine the smallest phase with the smallest value. Based on the carrier signal generated by the carrier signal generation unit 10 and the comparison result by the comparison unit 12, the maximum phase shift unit 13 determines the rising phase of the carrier signal corresponding to the maximum phase as the carrier corresponding to the intermediate phase. It is advanced by a fixed amount that allows current detection rather than the phase of signal rise. Based on the carrier signal generated by the carrier signal generation unit 10 and the comparison result of the comparison unit 12, the minimum phase shift unit 14 determines the rising phase of the carrier signal corresponding to the minimum phase as the carrier corresponding to the intermediate phase. The signal is delayed by a certain amount from which the current can be detected. The PWM signal generating means 15 is based on the carrier signals of the respective phases whose phases are shifted from each other by the maximum phase moving means 13 and the minimum phase moving means 14, and the duty setting values of the respective phases set by the duty setting means 11. A PWM signal for each phase is generated and output to the driving means 16. The driving means 16 drives the motor M based on the on / off operation of the switching elements Q1 to Q6 by the PWM signal. The current detection means 17 performs current detection in a predetermined section until the rise of the PWM signal corresponding to the intermediate phase and the PWM signal corresponding to the minimum phase.

  Here, “a constant amount that can be detected by current” means the time until the output signal is stabilized when the PWM signal output from the PWM signal generation unit 15 rises from the OFF state to the ON state, and the current detection unit 17. It shows a longer time than the total time required to actually detect the current. Normally, when the PWM signal rises from the OFF state to the ON state, it becomes a constant value after the signal swings up and down until it reaches the set constant value. If current detection is performed while this signal is swinging, the current detection means 17 will detect an incorrect current value. For this reason, accurate current detection can be performed by shifting the phase by a time longer than the total time of the time until the PWM signal rises to the ON state and stabilizes and the time of actual current detection.

  The correspondence between each block in FIG. 2 and the circuit in FIG. 1 is as follows. The carrier signal generation unit 10, the duty setting unit 11, the comparison unit 12, the maximum phase movement unit 13, the minimum phase movement unit 14, and the PWM signal generation unit 15 are blocks corresponding to some of the functions of the CPU 4. The driving unit 16 is a block configured by the driver IC 3 and the switching circuit 2. The current detection means 17 is a block corresponding to a part of the functions of the current detection resistor R and the amplifier circuit 5 and the CPU 4.

  FIG. 3 is a diagram for explaining the principle of generating a PWM signal from a carrier signal in the PWM signal generating means 15. As shown in FIG. 3A, for the sawtooth carrier signal, a duty setting value 1 that is a threshold is set, and a section where the carrier signal level is less than the setting value 1 is set to “H” (High). When a section having a value of 1 or more is set to “L” (Low) and the carrier signal is binarized, a PWM signal as shown in FIG. In FIG. 3A, since the duty setting value 1 is set high, in the PWM signal of FIG. 3C, the “H” section is long and the “L” section is short. As shown in FIG. 3B, when the duty setting value 2 is set for the carrier signal and the carrier signal is binarized in the same manner, a PWM signal as shown in FIG. 3D is obtained. In FIG. 3B, since the duty setting value 2 is set low, in the PWM signal of FIG. 3D, the “H” section is short and the “L” section is long. Therefore, the duty of the PWM signal can be adjusted by changing the duty setting value.

  FIG. 4 is a flowchart showing a current detection procedure in the first embodiment. In step S11, the duty setting means 11 sets the U-phase / V-phase / W-phase duty setting values based on the target current value and the detected current value of each phase. In step S12, the comparison unit 12 compares the duty setting values of the respective phases, and ranks them according to the set values. That is, the maximum phase, the intermediate phase, and the minimum phase are determined in the order of the size of the duty setting value. In the present embodiment, the U phase is the maximum phase, the V phase is the intermediate phase, and the W phase is the minimum phase. Next, in step S13, the maximum phase shift means 13 sets the phase shift amount of the carrier signal corresponding to the maximum phase (U phase). In step S14, the minimum phase shift means 14 sets the minimum phase (W phase). The phase shift amount of the carrier signal corresponding to is set.

  Here, the phase shift of the carrier signal will be described. FIG. 5 is a timing chart of the carrier signal and the PWM signal in the first embodiment. In the present embodiment, the phase of the U-phase carrier signal that is the maximum phase is advanced with respect to the V-phase carrier signal that is the intermediate phase, and the phase of the W-phase carrier signal that is the minimum phase is delayed. That is, with reference to the rising phase Y of the V-phase carrier signal, the rising phase of the U-phase carrier signal is shifted by a certain amount in the advance direction a, and the rising phase of the W-phase carrier signal is shifted by a certain amount in the delaying direction b. . These phase shift amounts are set to such shift amounts that the current detection means 17 can detect the motor current.

  Next, in step S15, the PWM signal generator 15 generates U-phase, V-phase, and W-phase PWM signals based on the U-phase, V-phase, and W-phase carrier signals described above. Since the U-phase, V-phase, and W-phase carrier signals are out of phase with each other, the U-phase, V-phase, and W-phase PWM signals are also out of phase with each other as shown in FIG. . That is, the phase of the U-phase PWM signal is advanced with respect to the V-phase PWM signal, and the phase of the W-phase PWM signal is delayed with respect to the V-phase PWM signal. In FIG. 5, the broken lines in the U-phase PWM signal and the W-phase PWM signal represent the PWM signal when there is no phase shift.

  The U-phase / V-phase / W-phase PWM signals shown in FIG. 5 are the PWM signals applied to the switching elements Q1, Q3, Q5 of the upper arms A1, A3, A5 of the respective phases in the switching circuit 2 (FIG. 1). Represents. The PWM signals applied to the switching elements Q2, Q4, Q6 of the lower arms A2, A4, A6 are signals obtained by inverting the PWM signals in FIG. 5 (not shown). In this case, a dead time is provided between the PWM signal applied to the switching element of the upper arm and the PWM signal applied to the switching element of the lower arm to prevent the upper and lower switching elements from being turned on simultaneously. . The same applies to timing charts described later.

  Next, in step S16, the current detection means 17 detects the current values of the U phase that is the maximum phase and the W phase that is the minimum phase. In this case, the U-phase current value is detected in the shaded section Tu shown in FIG. This section Tu is a predetermined section before the rise of the V-phase PWM signal in the section from the rise of the U-phase PWM signal that is the maximum phase to the rise of the V-phase PWM signal that is the intermediate phase. The time width of the section Tu is, for example, 2 μs. In the section Tu, the U-phase PWM signal is “H”, the V-phase PWM signal is “L”, and the W-phase PWM signal is “L”. Therefore, as shown in FIG. Q1 is on, V-phase upper arm switching element Q3 is off, and W-phase upper arm switching element Q5 is off. As a result, a current flows through the motor M along a path indicated by an arrow, and a U-phase current flows through the current detection resistor R. A voltage generated at both ends of the current detection resistor R by the U-phase current is input to the CPU 4 via the amplifier circuit 5 (FIG. 1), and AD conversion is performed by the CPU 4 to detect the U-phase current value. Therefore, the AD conversion for the U-phase current ends until the V-phase PWM signal rises (until the last timing of the section Tu).

  On the other hand, the W-phase current value is detected in the shaded section Tw shown in FIG. This interval Tw is a predetermined interval before the rise of the W-phase PWM signal in the interval from the rise of the V-phase PWM signal that is the intermediate phase to the rise of the W-phase PWM signal that is the minimum phase. The time width of the section Tw is, for example, 2 μs. In the section Tw, the U-phase PWM signal is “H”, the V-phase PWM signal is “H”, and the W-phase PWM signal is “L”. Therefore, as shown in FIG. Q1 is turned on, V-phase upper arm switching element Q3 is turned on, and W-phase upper arm switching element Q5 is turned off. As a result, a current flows through the motor M along the path indicated by the arrow, and a W-phase current flows through the current detection resistor R. The voltage generated at both ends of the current detection resistor R by the W-phase current is input to the CPU 4 via the amplifier circuit 5 (FIG. 1), and AD conversion is performed by the CPU 4 to detect the W-phase current value. Therefore, AD conversion for the W-phase current is completed until the W-phase PWM signal rises (until the last timing of the section Tw).

  Note that in FIG. 5, one cycle of the carrier signal is 50 μs, and carrier signals for five cycles are shown, and the U-phase current and the W-phase current are detected from the fourth cycle to the fifth cycle. This is an example, and current detection may be performed in any cycle. The same applies to the timing chart described later.

When the current values of the maximum phase (U phase) and the minimum phase (W phase) are detected as described above, next, the current values of the remaining intermediate phase (V phase) are calculated in step S17. Although the U-phase current value and the W-phase current value are both actually measured values, the V-phase current value is obtained by calculation. That is, when the U-phase current value is Iu, the V-phase current value is Iv, and the W-phase current value is Iw, the following relationship is established between them.
Iu + Iv + Iw = 0 (1)
Therefore, if the U-phase current value Iu and the W-phase current value Iw are known, the V-phase current value Iv is
Iv = − (Iu + Iv) (2)
Can be calculated as

  As described above, in the first embodiment, the phase of the carrier signal of the maximum phase (U phase) and the minimum phase (W phase) is shifted by a certain amount with reference to the carrier signal of the intermediate phase (V phase). A sufficient time for current detection by the current detection means 17 (time width of sections Tu and Tw in FIG. 5) can be secured. For this reason, each phase current can be accurately detected using a single current detection resistor R.

  Also, since the current detection timing is determined based on the rise of each PWM signal of the intermediate phase (V phase) and the minimum phase (W phase), the detection timing is always set to a fixed position (section Tu, Tw). be able to. For this reason, it is not necessary for the CPU 4 to determine whether or not current detection is possible, to calculate the phase shift amount, and to calculate the current detection timing each time, and the processing becomes extremely simple.

  Furthermore, the phase of the maximum phase (U phase) is advanced by a certain amount, and the phase of the minimum phase (W phase) is delayed by a certain amount, so that sufficient time for current detection can be secured and “H” of the three-phase PWM signal. The overlap time of the period can be as large as possible. Thereby, unnecessary current flowing into and out of the switching circuit 2 is reduced as much as possible, and the amount of heat generated by the electronic component can be suppressed.

  FIG. 8 is a block diagram showing an electric motor control device of a second embodiment (corresponding to claim 2) of the present invention. In the figure, the same reference numerals as in FIG. 2 are assigned to the same or corresponding parts as in FIG.

  In FIG. 8, an intermediate phase transfer means 18 is provided instead of the maximum phase transfer means 13 of FIG. The intermediate phase transfer means 18 is a block corresponding to a part of the function of the CPU 4. The correspondence between the other blocks and the circuit in FIG. 1 is basically the same as in FIG. Further, the operations of the carrier signal generation means 10, the duty setting means 11, the comparison means 12, the drive means 16, the current detection means 17, and the motor M are basically the same as those in FIG.

  Based on the carrier signal generated by the carrier signal generation unit 10 and the comparison result of the comparison unit 12, the intermediate phase transfer unit 18 sets the rising phase of the carrier signal corresponding to the intermediate phase to the carrier corresponding to the maximum phase. The signal is delayed by a certain amount from which the current can be detected. Further, the minimum phase shift means 14 corresponds to the rising phase of the carrier signal corresponding to the minimum phase to the intermediate phase based on the carrier signal generated by the carrier signal generation means 10 and the comparison result by the comparison means 12. The carrier signal is delayed from the rising phase of the carrier signal corresponding to the maximum phase so as to be delayed by a certain amount capable of detecting current from the rising phase of the delayed carrier signal. That is, in the second embodiment, the phases of the intermediate and minimum phase carrier signals are shifted with reference to the maximum phase carrier signal. Again, the U phase is the maximum phase, the V phase is the intermediate phase, and the W phase is the minimum phase.

  The PWM signal generation means 15 is based on the carrier signals of the respective phases whose phases are shifted from each other by the intermediate phase movement means 18 and the minimum phase movement means 14 and the duty setting values of the respective phases set by the duty setting means 11. A PWM signal for each phase is generated and output to the driving means 16.

  FIG. 9 is a flowchart showing a current detection procedure in the second embodiment. In FIG. 9, step S13 in FIG. 4, that is, the step of setting the phase shift amount of the maximum phase carrier signal is replaced with step S13a of setting the phase shift amount of the intermediate phase carrier signal. Other steps are the same as in FIG.

  In step S11, the duty setting means 11 sets U-phase / V-phase / W-phase duty setting values, and in step S12, the comparison means 12 ranks the duty setting values of the respective phases. In S13a, the intermediate phase moving means 18 sets the phase shift amount of the carrier signal corresponding to the intermediate phase (V phase). In step S14, the minimum phase shifter 14 sets the phase shift amount of the carrier signal corresponding to the minimum phase (W phase).

  Here, the phase shift of the carrier signal will be described. FIG. 10 is a timing chart of the carrier signal and the PWM signal in the second embodiment. In this embodiment, the phases of the carrier signals of the intermediate phase and the minimum phase are delayed with respect to the U-phase carrier signal which is the maximum phase. That is, with reference to the rising phase Y of the U-phase carrier signal, the rising phase of the V-phase carrier signal is shifted by a certain amount in the delay direction b, and the rising phase of the W-phase carrier signal is also shifted by a certain amount in the delay direction b. . At this time, the phase shift amount is larger in the W phase having a smaller duty set value. Therefore, the rising phase of the W-phase carrier signal is delayed from the rising phase of the V-phase carrier signal. The phase shift amounts between the U phase and the V phase and between the V phase and the W phase are set to such a shift amount that the current detection means 17 can detect the motor current.

  Next, in step S15, the PWM signal generator 15 generates U-phase, V-phase, and W-phase PWM signals based on the U-phase, V-phase, and W-phase carrier signals described above. Since the U-phase, V-phase, and W-phase carrier signals are out of phase with each other, the U-phase, V-phase, and W-phase PWM signals are also out of phase with each other as shown in FIG. . That is, the phase of the V-phase PWM signal is delayed with respect to the U-phase PWM signal, and the phase of the W-phase PWM signal is further delayed with respect to the U-phase PWM signal. In FIG. 5, the broken lines in the V-phase PWM signal and the W-phase PWM signal represent the PWM signal when there is no phase shift.

  The processes in steps S16 and S17 are the same as in the first embodiment. In step S16, the U-phase current value is detected in the section Tu in FIG. 10, and the W-phase current value is detected in the section Tw. The sections Tu and Tw are determined in the same manner as the sections Tu and Tw in FIG. When the current values Iu and Iw of the maximum phase (U phase) and the minimum phase (W phase) are detected, in step S17, the current value Iv of the remaining intermediate phase (V phase) is expressed by the equation (2). calculate.

  According to the second embodiment as described above, the phase of the carrier signal of the intermediate phase (V phase) and the minimum phase (W phase) is shifted by a certain amount with reference to the carrier signal of the maximum phase (U phase), Since current detection is always performed at fixed positions (sections Tu and Tw), the same effect as in the first embodiment can be obtained.

  FIG. 11 is a block diagram showing an electric motor control device according to a third embodiment (corresponding to claim 3) of the present invention. In the figure, the same reference numerals as in FIG. 2 are assigned to the same or corresponding parts as in FIG.

  In FIG. 11, an intermediate phase transfer means 18 is provided instead of the minimum phase transfer means 14 of FIG. The intermediate phase transfer means 18 is a block corresponding to a part of the function of the CPU 4. The correspondence between the other blocks and the circuit in FIG. 1 is basically the same as in FIG. Further, the operations of the carrier signal generation means 10, the duty setting means 11, the comparison means 12, the drive means 16, the current detection means 17, and the motor M are basically the same as those in FIG.

  Based on the carrier signal generated by the carrier signal generation unit 10 and the comparison result of the comparison unit 12, the intermediate phase transfer unit 18 sets the rising phase of the carrier signal corresponding to the intermediate phase to the carrier corresponding to the minimum phase. It is advanced by a fixed amount that allows current detection rather than the phase of signal rise. Further, the maximum phase shift means 13 corresponds to the rising phase of the carrier signal corresponding to the maximum phase based on the carrier signal generated by the carrier signal generation means 10 and the comparison result by the comparison means 12 to the intermediate phase. The carrier signal is advanced from the rising phase of the carrier signal corresponding to the minimum phase so that the current phase can be advanced by a fixed amount from the rising phase of the rising carrier signal. That is, in the third embodiment, the phases of the intermediate phase and maximum phase carrier signals are shifted with reference to the minimum phase carrier signal. Again, the U phase is the maximum phase, the V phase is the intermediate phase, and the W phase is the minimum phase.

  The PWM signal generating means 15 is based on the carrier signals of the respective phases whose phases are shifted from each other by the intermediate phase moving means 18 and the maximum phase moving means 13 and the duty setting values of the respective phases set by the duty setting means 11. A PWM signal for each phase is generated and output to the driving means 16.

  FIG. 12 is a flowchart showing a current detection procedure in the third embodiment. In FIG. 12, step S14 of FIG. 4, that is, the step of setting the phase shift amount of the carrier signal of the minimum phase is replaced with step S14a of setting the phase shift amount of the carrier signal of the intermediate phase. Other steps are the same as in FIG.

  In step S11, the duty setting means 11 sets U-phase / V-phase / W-phase duty setting values, and in step S12, the comparison means 12 ranks the duty setting values of the respective phases. In S13, the maximum phase moving means 13 sets the phase shift amount of the carrier signal corresponding to the maximum phase (U phase). In step S14a, the intermediate phase moving means 18 sets the phase shift amount of the carrier signal corresponding to the intermediate phase (V phase).

  Here, the phase shift of the carrier signal will be described. FIG. 13 is a timing chart of the carrier signal and the PWM signal in the third embodiment. In this embodiment, the phase of each carrier signal of the maximum phase and the minimum phase is advanced with respect to the carrier signal of the W phase that is the minimum phase. That is, with reference to the rising phase Y of the W-phase carrier signal, the rising phase of the U-phase carrier signal is shifted by a certain amount in the advancing direction a, and the rising phase of the V-phase carrier signal is also shifted by a certain amount in the advancing direction a. . At this time, the phase shift amount is larger in the U phase having a larger duty setting value. Therefore, the rising phase of the U-phase carrier signal is ahead of the rising phase of the V-phase carrier signal. Further, the phase shift amount between the W phase and the V phase and between the V phase and the U phase is set to such a shift amount that the current detection means 17 can detect the motor current.

  Next, in step S15, the PWM signal generator 15 generates U-phase, V-phase, and W-phase PWM signals based on the U-phase, V-phase, and W-phase carrier signals described above. Since the U-phase, V-phase, and W-phase carrier signals are out of phase with each other, the U-phase, V-phase, and W-phase PWM signals are also out of phase with each other as shown in FIG. . That is, the phase of the V-phase PWM signal is advanced with respect to the W-phase PWM signal, and the phase of the U-phase PWM signal is further advanced with respect to the W-phase PWM signal. In FIG. 13, the broken lines in the U-phase PWM signal and the V-phase PWM signal represent the PWM signal when there is no phase shift.

  The processes in steps S16 and S17 are the same as in the first embodiment. In step S16, the U-phase current value is detected in the section Tu of FIG. 13, and the W-phase current value is detected in the section Tw. The sections Tu and Tw are determined in the same manner as the sections Tu and Tw in FIG. When the current values Iu and Iw of the maximum phase (U phase) and the minimum phase (W phase) are detected, in step S17, the current value Iv of the remaining intermediate phase (V phase) is expressed by the equation (2). calculate.

  According to the third embodiment as described above, the phase of the carrier signal of the maximum phase (U phase) and the intermediate phase (V phase) is shifted by a certain amount with reference to the carrier signal of the minimum phase (W phase), Since current detection is always performed at fixed positions (sections Tu and Tw), the same effect as in the first embodiment can be obtained.

  FIG. 14 is a block diagram showing an electric motor control device according to a fourth embodiment (corresponding to claim 4) of the present invention. The carrier signal generation means 10 generates a sawtooth carrier signal for each phase having a predetermined frequency. The duty setting means 11 sets a duty setting value corresponding to the duty of the PWM signal of each phase based on the target current value of each phase and the current value of each phase detected by the current detection means 17. The PWM signal generation unit 15 generates a PWM signal of each phase based on the duty setting value of each phase set by the duty setting unit 11 and the carrier signal generated by the carrier signal generation unit 10. The comparing means 12 compares the duty setting values of the respective phases set by the duty setting means 11, and the maximum phase having the largest duty setting value, the intermediate phase having the middle duty setting value, and the duty setting. Determine the smallest phase with the smallest value. Based on the PWM signal generated by the PWM signal generation unit 15 and the comparison result of the comparison unit 12, the maximum phase shift unit 13 determines the rising phase of the PWM signal corresponding to the maximum phase as the PWM corresponding to the intermediate phase. It is advanced by a fixed amount that allows current detection rather than the phase of signal rise. Based on the PWM signal generated by the PWM signal generation unit 15 and the comparison result by the comparison unit 12, the minimum phase shift unit 14 changes the rising phase of the PWM signal corresponding to the minimum phase to the PWM corresponding to the intermediate phase. The signal is delayed by a certain amount from which the current can be detected. The driving unit 16 drives the motor M based on the PWM signals of the respective phases whose phases are shifted from each other by the maximum phase moving unit 13 and the minimum phase moving unit 14. The current detection means 17 performs current detection in a predetermined section until the rise of the PWM signal corresponding to the intermediate phase and the PWM signal corresponding to the minimum phase.

  The correspondence between each block in FIG. 14 and the circuit in FIG. 1 is as follows. The carrier signal generation unit 10, the duty setting unit 11, the comparison unit 12, the maximum phase movement unit 13, the minimum phase movement unit 14, and the PWM signal generation unit 15 are blocks corresponding to some of the functions of the CPU 4. The driving unit 16 is a block configured by the driver IC 3 and the switching circuit 2. The current detection means 17 is a block corresponding to a part of the functions of the current detection resistor R and the amplifier circuit 5 and the CPU 4.

  FIG. 15 is a flowchart showing a current detection procedure in the fourth embodiment. In step S21, the duty setting means 11 sets the U-phase / V-phase / W-phase duty setting values based on the target current value and the detected current value of each phase. In step S22, the comparison means 12 compares the duty setting values of the respective phases, and ranks them according to the size of the setting values. That is, the maximum phase, the intermediate phase, and the minimum phase are determined in the order of the size of the duty setting value. In the present embodiment, the U phase is the maximum phase, the V phase is the intermediate phase, and the W phase is the minimum phase. In step S23, the PWM signal generation unit 15 generates U-phase, V-phase, and W-phase PWM signals based on the carrier signal and the duty setting value. Next, in step S24, the maximum phase moving unit 13 sets the phase shift amount of the PWM signal corresponding to the maximum phase (U phase), and in step S25, the minimum phase moving unit 14 sets the minimum phase (W phase). The phase shift amount of the PWM signal corresponding to is set.

  Here, the phase shift of the PWM signal will be described. FIG. 16 is a timing chart of the carrier signal and the PWM signal in the fourth embodiment. In this embodiment, the phase of the U-phase PWM signal that is the maximum phase is advanced with respect to the V-phase PWM signal that is the intermediate phase, and the phase of the W-phase PWM signal that is the minimum phase is delayed. That is, with reference to the rising phase Y of the V-phase PWM signal, the rising phase of the U-phase PWM signal is shifted by a certain amount in the advance direction a, and the rising phase of the W-phase PWM signal is shifted by a certain amount in the delay direction b. . These phase shift amounts are set to such shift amounts that the current detection means 17 can detect the motor current.

  Due to such a phase shift, the U-phase, V-phase, and W-phase PWM signals are signals that are out of phase with each other. That is, the phase of the U-phase PWM signal is advanced with respect to the V-phase PWM signal, and the phase of the W-phase PWM signal is delayed with respect to the V-phase PWM signal. In FIG. 16, a broken line in the U-phase PWM signal and the W-phase PWM signal represents the PWM signal when there is no phase shift.

  Steps S26 and S27 are the same as steps S16 and S17 of FIG. 4 in the first embodiment. In step S26, the current detection means 17 detects the current values of the U phase that is the maximum phase and the W phase that is the minimum phase. In this case, the U-phase current value is detected in the section Tu in FIG. 16, and the W-phase current value is detected in the section Tw. The sections Tu and Tw are determined in the same manner as the sections Tu and Tw in FIG. When the current values Iu and Iw of the maximum phase (U phase) and the minimum phase (W phase) are detected, in step S27, the current value Iv of the remaining intermediate phase (V phase) is expressed by the equation (2). calculate.

  According to the fourth embodiment as described above, the phase of the PWM signal of the intermediate phase (V phase) and the minimum phase (W phase) is shifted by a certain amount with reference to the PWM signal of the intermediate phase (V phase), and Since current detection is always performed at fixed positions (sections Tu and Tw), the same effect as in the first embodiment can be obtained.

  FIG. 17 is a block diagram showing an electric motor control device of a fifth embodiment (corresponding to claim 5) of the present invention. In the figure, the same reference numerals as in FIG. 14 are given to the same or corresponding parts as in FIG.

  In FIG. 17, an intermediate phase transfer means 18 is provided instead of the maximum phase transfer means 13 of FIG. The intermediate phase transfer means 18 is a block corresponding to a part of the function of the CPU 4. The correspondence between the other blocks and the circuit of FIG. 1 is basically the same as in FIG. Further, the operations of the carrier signal generation means 10, the duty setting means 11, the comparison means 12, the drive means 16, the current detection means 17, and the motor M are basically the same as in the case of FIG.

  Based on the PWM signal generated by the PWM signal generation unit 15 and the comparison result by the comparison unit 12, the intermediate phase moving unit 18 sets the rising phase of the PWM signal corresponding to the intermediate phase to the PWM corresponding to the maximum phase. The signal is delayed by a certain amount from which the current can be detected. Further, the minimum phase shift unit 14 corresponds to the rising phase of the PWM signal corresponding to the minimum phase based on the PWM signal generated by the PWM signal generation unit 15 and the comparison result of the comparison unit 12 to the intermediate phase. The PWM signal is delayed from the rising phase of the PWM signal corresponding to the maximum phase so as to be delayed by a fixed amount capable of detecting current from the rising phase of the delayed PWM signal. That is, in the fifth embodiment, the phase of the intermediate phase and the minimum phase PWM signal is shifted with reference to the maximum phase PWM signal. Again, the U phase is the maximum phase, the V phase is the intermediate phase, and the W phase is the minimum phase.

  The driving unit 16 drives the motor M based on the PWM signals of the respective phases whose phases are shifted from each other by the intermediate phase moving unit 18 and the minimum phase moving unit 14.

  FIG. 18 is a flowchart showing a current detection procedure in the fifth embodiment. In FIG. 18, step S24 of FIG. 15, that is, the step of setting the phase shift amount of the maximum phase PWM signal is replaced with step S24a of setting the phase shift amount of the intermediate phase PWM signal. Other steps are the same as in FIG.

  In step S21, the duty setting means 11 sets U-phase / V-phase / W-phase duty setting values, and in step S22, the comparison means 12 ranks the duty setting values of the respective phases. In S23, the PWM signal generation means 15 generates U-phase / V-phase / W-phase PWM signals. Next, in step S24a, the intermediate phase moving unit 18 sets the phase shift amount of the PWM signal corresponding to the intermediate phase (V phase). In step S25, the minimum phase moving unit 14 sets the minimum phase (W phase). The phase shift amount of the PWM signal corresponding to is set.

  Here, the phase shift of the PWM signal will be described. FIG. 19 is a timing chart of the carrier signal and the PWM signal in the fifth embodiment. In the present embodiment, the phases of the PWM signals of the intermediate phase and the minimum phase are delayed with respect to the U-phase PWM signal which is the maximum phase. That is, the rising phase of the V-phase PWM signal is shifted by a certain amount in the delay direction b with the rising phase Y of the U-phase PWM signal as a reference, and the rising phase of the W-phase PWM signal is also shifted by a certain amount in the delaying direction b. . At this time, the phase shift amount is larger in the W phase having a smaller duty set value. Therefore, the rising phase of the W-phase PWM signal is delayed from the rising phase of the V-phase PWM signal. The phase shift amounts between the U phase and the V phase and between the V phase and the W phase are set to such a shift amount that the current detection means 17 can detect the motor current.

  Due to such a phase shift, the U-phase, V-phase, and W-phase PWM signals are signals that are out of phase with each other. That is, the phase of the V-phase PWM signal is delayed with respect to the U-phase PWM signal, and the phase of the W-phase PWM signal is further delayed with respect to the U-phase PWM signal. In FIG. 19, the broken lines in the V-phase PWM signal and the W-phase PWM signal represent the PWM signal when there is no phase shift.

  Steps S26 and S27 are the same as steps S26 and S27 of FIG. 15 in the fourth embodiment. In step S26, the current detection means 17 detects the current values of the U phase that is the maximum phase and the W phase that is the minimum phase. In this case, the U-phase current value is detected in the section Tu in FIG. 19, and the W-phase current value is detected in the section Tw. The sections Tu and Tw are determined in the same manner as the sections Tu and Tw in FIG. When the current values Iu and Iw of the maximum phase (U phase) and the minimum phase (W phase) are detected, in step S27, the current value Iv of the remaining intermediate phase (V phase) is expressed by the equation (2). calculate.

  According to the fifth embodiment as described above, the phase of the PWM signal of the intermediate phase (V phase) and the minimum phase (W phase) is shifted by a certain amount with reference to the PWM signal of the maximum phase (U phase), Since current detection is always performed at fixed positions (sections Tu and Tw), the same effect as in the first embodiment can be obtained.

  FIG. 20 is a block diagram showing an electric motor control apparatus according to a sixth embodiment (corresponding to claim 6) of the present invention. In the figure, the same reference numerals as in FIG. 14 are given to the same or corresponding parts as in FIG.

  In FIG. 20, an intermediate phase transfer means 18 is provided instead of the minimum phase transfer means 14 of FIG. The intermediate phase transfer means 18 is a block corresponding to a part of the function of the CPU 4. The correspondence between the other blocks and the circuit of FIG. 1 is basically the same as in FIG. Further, the operations of the carrier signal generation means 10, the duty setting means 11, the comparison means 12, the drive means 16, the current detection means 17, and the motor M are basically the same as in the case of FIG.

  Based on the PWM signal generated by the PWM signal generating unit 15 and the comparison result by the comparing unit 12, the intermediate phase moving unit 18 sets the rising phase of the PWM signal corresponding to the intermediate phase to the PWM corresponding to the minimum phase. It is advanced by a fixed amount that allows current detection rather than the phase of signal rise. Further, the maximum phase shift means 13 corresponds to the rising phase of the PWM signal corresponding to the maximum phase based on the PWM signal generated by the PWM signal generation means 15 and the comparison result by the comparison means 12 to the intermediate phase. The PWM signal is advanced from the rising phase of the PWM signal corresponding to the minimum phase so as to advance by a certain amount capable of detecting current from the rising phase of the advanced PWM signal. That is, in the sixth embodiment, the phases of the maximum-phase and intermediate-phase PWM signals are shifted with reference to the minimum-phase PWM signal. Again, the U phase is the maximum phase, the V phase is the intermediate phase, and the W phase is the minimum phase.

  The driving unit 16 drives the motor M based on the PWM signals of the respective phases whose phases are shifted from each other by the maximum phase moving unit 13 and the intermediate phase moving unit 18.

  FIG. 21 is a flowchart showing a current detection procedure in the sixth embodiment. In FIG. 21, step S25 of FIG. 15, that is, the step of setting the phase shift amount of the minimum phase PWM signal is replaced with step S25a of setting the phase shift amount of the intermediate phase PWM signal. Other steps are the same as in FIG.

  In step S21, the duty setting means 11 sets U-phase / V-phase / W-phase duty setting values, and in step S22, the comparison means 12 ranks the duty setting values of the respective phases. In S23, the PWM signal generation means 15 generates U-phase / V-phase / W-phase PWM signals. Next, in step S24, the maximum phase moving unit 13 sets the phase shift amount of the PWM signal corresponding to the maximum phase (U phase). In step S25a, the intermediate phase moving unit 18 sets the intermediate phase (V phase). The phase shift amount of the PWM signal corresponding to is set.

  Here, the phase shift of the PWM signal will be described. FIG. 22 is a timing chart of the carrier signal and the PWM signal in the sixth embodiment. In the present embodiment, the phases of the PWM signals of the maximum phase and the intermediate phase are advanced with respect to the PWM signal of the W phase that is the minimum phase. That is, with reference to the rising phase Y of the W-phase PWM signal, the rising phase of the U-phase PWM signal is shifted by a certain amount in the advancing direction a, and the rising phase of the V-phase PWM signal is also shifted by a certain amount in the advancing direction a. . At this time, the phase shift amount is larger in the U phase having a larger duty setting value. Therefore, the rising phase of the U-phase PWM signal is ahead of the rising phase of the V-phase PWM signal. Further, the phase shift amount between the W phase and the V phase and between the V phase and the U phase is set to such a shift amount that the current detection means 17 can detect the motor current.

  Due to such a phase shift, the U-phase, V-phase, and W-phase PWM signals are signals that are out of phase with each other. That is, the phase of the V-phase PWM signal is advanced with respect to the W-phase PWM signal, and the phase of the U-phase PWM signal is further advanced with respect to the W-phase PWM signal. In FIG. 22, the broken lines in the U-phase PWM signal and the V-phase PWM signal represent the PWM signal when there is no phase shift.

  Steps S26 and S27 are the same as steps S26 and S27 of FIG. 15 in the fourth embodiment. In step S26, the current detection means 17 detects the current values of the U phase that is the maximum phase and the W phase that is the minimum phase. In this case, the U-phase current value is detected in the section Tu in FIG. 22, and the W-phase current value is detected in the section Tw. The sections Tu and Tw are determined in the same manner as the sections Tu and Tw in FIG. When the current values Iu and Iw of the maximum phase (U phase) and the minimum phase (W phase) are detected, in step S27, the current value Iv of the remaining intermediate phase (V phase) is expressed by the equation (2). calculate.

  According to the sixth embodiment as described above, the phase of the PWM signal of the maximum phase (U phase) and the intermediate phase (V phase) is shifted by a certain amount with reference to the PWM signal of the minimum phase (W phase), Since current detection is always performed at fixed positions (sections Tu and Tw), the same effect as in the first embodiment can be obtained.

  In the first to sixth embodiments described above, when the duty setting values set by the duty setting means 11 are equal to the two-phase duty setting values other than the maximum phase, the comparison means 12 is either One phase is determined as the intermediate phase and the other phase is determined as the minimum phase.

  In the above embodiments, a control device for a three-phase motor has been described. However, the present invention is not limited to a three-phase motor, and can also be realized as a control device for a multi-phase motor having four or more phases. In this case, in the switching circuit 2 of FIG. 1, a plurality of pairs of upper and lower arms are provided according to the number of phases. Hereinafter, an embodiment when the present invention is applied to a control device for a multiphase motor will be described.

  FIG. 23A and FIG. 23B are timing charts showing a carrier signal and a PWM signal, respectively, in the seventh embodiment (corresponding to claim 8). The present embodiment is a modification of the above-described second embodiment, and the configuration of the motor control device is basically the same as that shown in FIG. However, the two blocks of the intermediate phase shift means 18 and the minimum phase shift means 14 in FIG. 8 are replaced with one block called the phase shift means. The motor M constitutes the multiphase motor in the seventh embodiment. The current detection procedure is basically the same as the procedure shown in FIG. 9 except that the three phases become n phases (n ≧ 4) and there are a plurality of intermediate phases between the maximum phase and the minimum phase. .

  In the seventh embodiment, similarly to the second embodiment, the phase of the carrier signal of each phase other than the maximum phase is delayed by the phase shift means with reference to the carrier signal of the maximum phase. That is, in FIG. 23A, each of the second, third,..., N−2, n−1th phases as the intermediate phase with reference to the rising phase Y of the carrier signal of the maximum phase (first phase). The rising phase of the carrier signal is sequentially shifted by a certain amount in the delay direction b in accordance with the order of the magnitude of the duty setting value, and the rising phase of the carrier signal of the minimum phase (n-th phase) is similarly Shift a certain amount in the delay direction b. At this time, the phase shift amount increases as the duty setting value decreases. Further, the phase shift amount between the phases is set to a shift amount that enables the current detection means 17 to detect the motor current.

  Thus, since the phases of the carrier signals of the respective phases are shifted from each other, the PWM signals generated by the PWM signal generating means 15 based on these are also signals whose phases are shifted from each other as shown in FIG. 23B. . Then, based on the same principle as in the first embodiment, the current value of each phase is detected in each of (n−1) sections indicated by T1 in FIG. 23B. Each of these intervals is a predetermined interval before the rise of the PWM signal of each phase other than the maximum phase in the interval from the rise of the PWM signal of a certain phase to the rise of the PWM signal of the next phase. The time width of each section is 2 μs, for example. When each current value of the (n−1) phase is detected in the section T1, the remaining one-phase current value is calculated by calculation based on the same concept as the equation (2).

  According to the seventh embodiment as described above, the phase of the carrier signal other than the maximum phase is shifted by a certain amount with reference to the carrier signal of the maximum phase, and current detection is always performed at a fixed position (each section of T1). Therefore, even in the case of a multiphase motor, the same effect as that of the first embodiment can be obtained.

  24A and 24B are timing charts showing a carrier signal and a PWM signal, respectively, in the eighth embodiment (corresponding to claim 9). This embodiment is a modification of the above-described third embodiment, and the configuration of the motor control device is basically the same as that shown in FIG. However, the two blocks of the maximum phase shift means 13 and the intermediate phase shift means 18 in FIG. 11 are replaced with one block called the phase shift means. The motor M constitutes the multiphase motor in the eighth embodiment. The current detection procedure is basically the same as the procedure shown in FIG. 12 except that three phases are n phases (n ≧ 4) and there are a plurality of intermediate phases between the maximum phase and the minimum phase. .

  In the eighth embodiment, similarly to the third embodiment, the phase of the carrier signal of each phase other than the minimum phase is advanced by the phase shift means with reference to the carrier signal of the minimum phase. That is, in FIG. 24A, with reference to the rising phase Y of the carrier signal of the minimum phase (nth phase), each of the n−1, n−2,. The rising phase of the carrier signal is sequentially shifted by a fixed amount in the advance direction a in accordance with the order of the magnitude of the duty setting value, and the rising phase of the carrier signal of the maximum phase (first phase) is also the same Shift a certain amount in the advancing direction a. At this time, the phase shift amount increases as the duty setting value increases. Further, the phase shift amount between the phases is set to a shift amount that enables the current detection means 17 to detect the motor current.

  Thus, since the phases of the carrier signals of the respective phases are shifted from each other, the PWM signals generated by the PWM signal generating means 15 based on these are also signals whose phases are shifted from each other as shown in FIG. 24B. . Then, based on the same principle as in the first embodiment, the current value of each phase is detected in each of n−1 sections indicated by T2 in FIG. 24B. Each section of T2 is determined in the same manner as each section of T1 in FIG. 23B. When each current value of the (n−1) phase is detected in the section T2, the current value of the remaining one phase is calculated by calculation based on the same concept as the equation (2).

  According to the eighth embodiment as described above, the phase of the carrier signal other than the minimum phase is shifted by a fixed amount with reference to the carrier signal of the minimum phase, and current detection is always performed at a fixed position (each section of T2). Therefore, even in the case of a multiphase motor, the same effect as that of the first embodiment can be obtained.

  25A and 25B are timing charts showing a carrier signal and a PWM signal, respectively, in the ninth embodiment (corresponding to claim 10). The present embodiment is a modification of the first embodiment described above, and the configuration of the motor control device is basically the same as that shown in FIG. However, the two blocks of the maximum phase shift means 13 and the minimum phase shift means 14 in FIG. 2 are replaced with one block called the phase shift means. The motor M constitutes the multiphase motor in the ninth embodiment. The current detection procedure is also basically the same as the procedure shown in FIG. 4 except that the three phases become n phases (n ≧ 4) and there are a plurality of intermediate phases between the maximum phase and the minimum phase. .

  In the ninth embodiment, similarly to the first embodiment, the phase shift is performed with reference to the carrier signal of the intermediate phase. In this case, the intermediate phase is an arbitrary intermediate phase (hereinafter referred to as the maximum phase and the minimum phase). "Arbitrary phase"). Then, with respect to each phase other than the arbitrary phase, the phase of the carrier signal is advanced or delayed by the phase shift means according to the magnitude relationship of the duty setting value. That is, in FIG. 25A, with reference to the rising phase Y of the carrier signal of the mth phase (arbitrary phase), the duty setting value is larger than that of the arbitrary phase and the maximum phase (the first phase) For each phase up to (phase), the phase of the rising edge of the carrier signal is sequentially shifted by a certain amount in the advance direction a in accordance with the order of the magnitude of the duty setting value. In addition, for each phase from the m + 1st phase to the minimum phase (nth phase) where the duty setting value is smaller than that of the arbitrary phase, the rising phase of the carrier signal is represented by the rank of the duty setting value. In response to this, a certain amount is sequentially shifted in the delay direction b. At this time, in the advance direction a, the phase shift amount increases as the phase of the duty setting value increases, and in the delay direction b, the phase shift amount increases as the phase of the duty set value decreases. Further, the phase shift amount between the phases in the respective directions a and b is set to such a shift amount that the current detection means 17 can detect the motor current.

  Thus, since the phases of the carrier signals of the respective phases are shifted from each other, the PWM signals generated by the PWM signal generating means 15 based on these are also signals whose phases are shifted from each other as shown in FIG. 25B. . Then, based on the same principle as in the first embodiment, the current value of each phase is detected in each of n−1 sections indicated by T3 in FIG. 25B. Each section of T3 is determined in the same manner as each section of T1 in FIG. 23B. When each current value of the n−1 phase is detected in the section T3, the remaining one phase current value is calculated by calculation based on the same concept as the equation (2).

  According to the ninth embodiment as described above, the phase of the carrier signal other than the arbitrary phase is shifted by a certain amount with reference to the carrier signal of the arbitrary phase, and the current detection is always performed at the fixed position (each section of T3). Therefore, even in the case of a multiphase motor, the same effect as that of the first embodiment can be obtained.

  FIG. 26 is a timing chart showing PWM signals in the tenth embodiment (corresponding to claim 11). In FIG. 26, the carrier signal is not shown. This embodiment is a modification of the above-described fifth embodiment, and the configuration of the motor control device is basically the same as that shown in FIG. However, the two blocks of the intermediate phase shift means 18 and the minimum phase shift means 14 in FIG. 17 are replaced with one block called the phase shift means. The motor M constitutes the multiphase motor in the tenth embodiment. Also, the current detection procedure is basically the same as the procedure shown in FIG. 18 except that three phases become n phases (n ≧ 4) and there are a plurality of intermediate phases between the maximum phase and the minimum phase. .

  In the tenth embodiment, similarly to the fifth embodiment, the phase of the PWM signal of each phase other than the maximum phase is delayed by the phase shift means with the PWM signal of the maximum phase as a reference. That is, in FIG. 26, with reference to the rising phase Y of the PWM signal of the maximum phase (first phase), the PWM signals of the second, third,. The rising phase is sequentially shifted by a fixed amount in the delay direction b according to the order of the magnitude of the duty setting value, and the rising phase of the PWM signal of the minimum phase (n-th phase) is also shifted in the delay direction b. Shift a certain amount. At this time, the phase shift amount increases as the duty setting value decreases. Further, the phase shift amount between the phases is set to a shift amount that enables the current detection means 17 to detect the motor current.

  Due to such a phase shift, the PWM signals of the respective phases become signals whose phases are shifted from each other. Then, based on the same principle as in the first embodiment, the current value of each phase is detected in each of n−1 sections indicated by T4 in FIG. Each section of T4 is determined in the same manner as each section of T1 in FIG. 23B. When each current value of the (n−1) phase is detected in the section T4, the remaining one-phase current value is calculated by calculation based on the same concept as the equation (2).

  According to the tenth embodiment as described above, the phase of the PWM signal other than the maximum phase is shifted by a fixed amount with reference to the maximum phase PWM signal, and current detection is always performed at a fixed position (each section of T4). Therefore, even in the case of a multiphase motor, the same effect as that of the first embodiment can be obtained.

  FIG. 27 is a timing chart showing PWM signals in the eleventh embodiment (corresponding to claim 12). In FIG. 27, the carrier signal is not shown. The present embodiment is a modification of the above-described sixth embodiment, and the configuration of the motor control device is basically the same as that shown in FIG. However, the two blocks of the maximum phase shift means 13 and the intermediate phase shift means 18 in FIG. 20 are replaced with one block called the phase shift means. The motor M constitutes the multiphase motor in the eleventh embodiment. The current detection procedure is basically the same as the procedure shown in FIG. 21 except that the three phases are n phases (n ≧ 4) and there are a plurality of intermediate phases between the maximum phase and the minimum phase. .

  In the eleventh embodiment, similarly to the sixth embodiment, the phase of the PWM signal of each phase other than the minimum phase is advanced by the phase shift means with reference to the PWM signal of the minimum phase. That is, in FIG. 27, with reference to the rising phase Y of the PWM signal of the minimum phase (n-th phase), the n-1th, n-2th,. The rising phase is sequentially shifted by a fixed amount in the advance direction a in accordance with the order of the magnitude of the duty setting value, and the rising phase of the PWM signal of the maximum phase (first phase) is similarly advanced in the advance direction a. Shift a certain amount. At this time, the phase shift amount increases as the duty setting value increases. Further, the phase shift amount between the phases is set to a shift amount that enables the current detection means 17 to detect the motor current.

  Due to such a phase shift, the PWM signals of the respective phases become signals whose phases are shifted from each other. Then, based on the same principle as in the first embodiment, the current value of each phase is detected in each of n−1 sections indicated by T5 in FIG. Each section of T5 is determined in the same manner as each section of T1 in FIG. 23B. When each current value of the n−1 phase is detected in the section T5, the remaining one-phase current value is calculated by calculation based on the same concept as the equation (2).

  According to the eleventh embodiment as described above, the phase of the PWM signal other than the minimum phase is shifted by a certain amount on the basis of the PWM signal of the minimum phase, and current detection is always performed at a fixed position (each section of T5). Therefore, even in the case of a multiphase motor, the same effect as that of the first embodiment can be obtained.

  FIG. 28 is a timing chart showing PWM signals in the twelfth embodiment (corresponding to claim 13). In FIG. 28, the carrier signal is not shown. The present embodiment is a modification of the above-described fourth embodiment, and the configuration of the motor control device is basically the same as that shown in FIG. However, the two blocks of the maximum phase shift means 13 and the minimum phase shift means 14 in FIG. 14 are replaced with one block called the phase shift means. The motor M constitutes the multiphase motor in the twelfth embodiment. The current detection procedure is basically the same as the procedure shown in FIG. 15 except that the three phases are n phases (n ≧ 4) and there are a plurality of intermediate phases between the maximum phase and the minimum phase. .

  In the twelfth embodiment, similarly to the fourth embodiment, the phase shift is performed with reference to the intermediate phase PWM signal. In this case, the intermediate phase is an arbitrary intermediate phase (arbitrary phase except the maximum phase and the minimum phase). ) Then, with respect to each phase other than the arbitrary phase, the phase of the PWM signal is advanced or delayed according to the magnitude relationship of the duty setting value. That is, in FIG. 28, with reference to the rising phase Y of the PWM signal of the mth phase (arbitrary phase), the duty setting value is larger than that of the arbitrary phase and the maximum phase (the first phase) For each phase up to (phase), the rising phase of the PWM signal is sequentially shifted by a certain amount in the advance direction a in accordance with the order of the magnitude of the duty setting value. In addition, for each phase from the m + 1st phase to the minimum phase (nth phase) where the duty setting value is smaller than that of the arbitrary phase, the rising phase of the PWM signal is represented by the rank of the duty setting value. In response to this, a certain amount is sequentially shifted in the delay direction b. At this time, in the advance direction a, the phase shift amount increases as the phase of the duty setting value increases, and in the delay direction b, the phase shift amount increases as the phase of the duty set value decreases. Further, the phase shift amount between the phases in the respective directions a and b is set to such a shift amount that the current detection means 17 can detect the motor current.

  Due to such a phase shift, the PWM signals of the respective phases become signals whose phases are shifted from each other. Then, based on the same principle as in the first embodiment, the current value of each phase is detected in each of n−1 sections indicated by T6 in FIG. Each section of T6 is determined in the same manner as each section of T1 in FIG. 23B. When each current value of the n−1 phase is detected in the section T6, the remaining one-phase current value is calculated by calculation based on the same concept as the equation (2).

  According to the twelfth embodiment as described above, the phase of the PWM signal other than the arbitrary phase is shifted by a certain amount on the basis of the PWM signal of the arbitrary phase, and the current detection is always performed at the fixed position (each section of T6). Therefore, even in the case of a multiphase motor, the same effect as that of the first embodiment can be obtained.

  In the seventh to twelfth embodiments described above, when there is an equal duty setting value among the duty setting values set by the duty setting means 11, the comparison means 12 differs from the duty setting value. Determine the ranking.

  In the present invention, various embodiments other than those described above can be adopted. For example, although FETs are used as the switching elements Q1 to Q6 in FIG. 1, other switching elements such as IGBTs (insulated gate bipolar mode transistors) may be used.

  In each of the above embodiments, the case where the U phase is the maximum phase, the V phase is the intermediate phase, and the W phase is the minimum phase is an example, but this is an example, for example, the U phase is the minimum phase. When the V phase is the intermediate phase and the W phase is the maximum phase, or when the U phase is the intermediate phase, the V phase is the minimum phase, and the W phase is the maximum phase, each phase and the maximum phase / intermediate phase / minimum phase In any case, the effects of the present invention can be obtained.

  Further, in each of the above embodiments, the brushless motor is exemplified as the electric motor. However, the present invention can be applied to all control devices for controlling an electric motor having a plurality of phases such as an induction motor and a synchronous motor. .

1 Power supply circuit 2 Switching circuit 3 Driver IC
4 CPU
DESCRIPTION OF SYMBOLS 5 Amplifier circuit 10 Carrier signal production | generation means 11 Duty setting means 12 Comparison means 13 Maximum phase movement means 14 Minimum phase movement means 15 PWM signal generation means 16 Drive means 17 Current detection means 18 Intermediate phase movement means M Motor A1-A6 Arm Q1- Q6 Switching element R Current detection resistor

Claims (14)

Three pairs of upper and lower arms each having a switching element on the upper arm and the lower arm are provided, and driving means for driving the three-phase motor based on on / off operation of each switching element by a PWM (Pulse Width Modulation) signal;
A single current detecting means for detecting a current value of each phase of the three-phase motor;
Duty setting means for setting a duty setting value according to the duty of the PWM signal of each phase based on the target current value of each phase and the current value of each phase detected by the current detection means;
Carrier signal generating means for generating a carrier signal;
Comparing the duty setting value of each phase set by the duty setting means, the maximum phase with the largest duty setting value, the intermediate phase with the middle duty setting value, the magnitude of the duty setting value A comparison means for determining the smallest minimum phase;
Based on the carrier signal generated by the carrier signal generation means and the comparison result by the comparison means, the rising phase of the carrier signal corresponding to the maximum phase is changed to the rising phase of the carrier signal corresponding to the intermediate phase. Rather than the maximum phase transfer means to advance a certain amount of current detectable,
Based on the carrier signal generated by the carrier signal generation means and the comparison result by the comparison means, the rising phase of the carrier signal corresponding to the minimum phase is changed to the rising phase of the carrier signal corresponding to the intermediate phase. Rather than a minimum phase transfer means for delaying the current detection by a certain amount,
A PWM signal of each phase is generated based on the carrier signal of each phase shifted from each other by the maximum phase moving unit and the minimum phase moving unit and the duty setting value of each phase set by the duty setting unit. PWM signal generating means for outputting to the driving means,
The motor control device according to claim 1, wherein the current detection means detects current in a predetermined section until a rise of each of the PWM signal corresponding to the intermediate phase and the PWM signal corresponding to the minimum phase. Three pairs of upper and lower arms each having a switching element on the upper arm and the lower arm are provided, and driving means for driving the three-phase motor based on on / off operation of each switching element by a PWM signal;
A single current detecting means for detecting a current value of each phase of the three-phase motor;
Duty setting means for setting a duty setting value according to the duty of the PWM signal of each phase based on the target current value of each phase and the current value of each phase detected by the current detection means;
Carrier signal generating means for generating a carrier signal;
Comparing the duty setting value of each phase set by the duty setting means, the maximum phase with the largest duty setting value, the intermediate phase with the middle duty setting value, the magnitude of the duty setting value A comparison means for determining the smallest minimum phase;
Based on the carrier signal generated by the carrier signal generating means and the comparison result by the comparing means, the rising phase of the carrier signal corresponding to the intermediate phase is changed to the rising phase of the carrier signal corresponding to the maximum phase. Intermediate phase transfer means for delaying the current detection by a certain amount,
Based on the carrier signal generated by the carrier signal generation means and the comparison result by the comparison means, the rising phase of the carrier signal corresponding to the minimum phase is changed to that of the delayed carrier signal corresponding to the intermediate phase. Minimum phase shifting means for delaying from the rising phase of the carrier signal corresponding to the maximum phase so as to be delayed by a certain amount of current detectable from the rising phase;
A PWM signal of each phase is generated based on the carrier signal of each phase shifted from each other by the intermediate phase moving unit and the minimum phase moving unit and the duty setting value of each phase set by the duty setting unit. PWM signal generating means for outputting to the driving means,
The motor control device according to claim 1, wherein the current detection means detects current in a predetermined section until a rise of each of the PWM signal corresponding to the intermediate phase and the PWM signal corresponding to the minimum phase. Three pairs of upper and lower arms each having a switching element on the upper arm and the lower arm are provided, and driving means for driving the three-phase motor based on on / off operation of each switching element by a PWM signal;
A single current detecting means for detecting a current value of each phase of the three-phase motor;
Duty setting means for setting a duty setting value according to the duty of the PWM signal of each phase based on the target current value of each phase and the current value of each phase detected by the current detection means;
Carrier signal generating means for generating a carrier signal;
Comparing the duty setting value of each phase set by the duty setting means, the maximum phase with the largest duty setting value, the intermediate phase with the middle duty setting value, the magnitude of the duty setting value A comparison means for determining the smallest minimum phase;
Based on the carrier signal generated by the carrier signal generation means and the comparison result by the comparison means, the rising phase of the carrier signal corresponding to the intermediate phase is changed to the rising phase of the carrier signal corresponding to the minimum phase. Rather than an intermediate phase transfer means that advances a certain amount of current detectable,
Based on the carrier signal generated by the carrier signal generation means and the comparison result by the comparison means, the rising phase of the carrier signal corresponding to the maximum phase is changed to that of the advanced carrier signal corresponding to the intermediate phase. Maximum phase moving means that advances from the rising phase of the carrier signal corresponding to the minimum phase so as to advance a certain amount of current detectable from the rising phase;
A PWM signal of each phase is generated based on the carrier signal of each phase shifted from each other by the intermediate phase moving unit and the maximum phase moving unit and the duty setting value of each phase set by the duty setting unit. PWM signal generating means for outputting to the driving means,
The motor control device according to claim 1, wherein the current detection means detects current in a predetermined section until a rise of each of the PWM signal corresponding to the intermediate phase and the PWM signal corresponding to the minimum phase. Three pairs of upper and lower arms each having a switching element on the upper arm and the lower arm are provided, and driving means for driving the three-phase motor based on on / off operation of each switching element by a PWM signal;
A single current detecting means for detecting a current value of each phase of the three-phase motor;
Duty setting means for setting a duty setting value according to the duty of the PWM signal of each phase based on the target current value of each phase and the current value of each phase detected by the current detection means;
Carrier signal generating means for generating a carrier signal;
PWM signal generation means for generating a PWM signal for each phase based on the duty setting value for each phase set by the duty setting means and the carrier signal generated by the carrier signal generation means;
Comparing the duty setting value of each phase set by the duty setting means, the maximum phase with the largest duty setting value, the intermediate phase with the middle duty setting value, the magnitude of the duty setting value A comparison means for determining the smallest minimum phase;
Based on the PWM signal generated by the PWM signal generating means and the comparison result by the comparing means, the rising phase of the PWM signal corresponding to the maximum phase is changed to the rising phase of the PWM signal corresponding to the intermediate phase. Rather than the maximum phase transfer means to advance a certain amount of current detectable,
Based on the PWM signal generated by the PWM signal generation unit and the comparison result by the comparison unit, the rising phase of the PWM signal corresponding to the minimum phase is changed to the rising phase of the PWM signal corresponding to the intermediate phase. And a minimum phase transfer means for delaying the current detection by a certain amount, and
The driving means drives the three-phase motor based on PWM signals of respective phases whose phases are shifted from each other by the maximum phase moving means and the minimum phase moving means,
The motor control device according to claim 1, wherein the current detection means detects current in a predetermined section until a rise of each of the PWM signal corresponding to the intermediate phase and the PWM signal corresponding to the minimum phase. Three pairs of upper and lower arms each having a switching element on the upper arm and the lower arm are provided, and driving means for driving the three-phase motor based on on / off operation of each switching element by a PWM signal;
A single current detecting means for detecting a current value of each phase of the three-phase motor;
Duty setting means for setting a duty setting value according to the duty of the PWM signal of each phase based on the target current value of each phase and the current value of each phase detected by the current detection means;
Carrier signal generating means for generating a carrier signal;
PWM signal generation means for generating a PWM signal for each phase based on the duty setting value for each phase set by the duty setting means and the carrier signal generated by the carrier signal generation means;
Comparing the duty setting value of each phase set by the duty setting means, the maximum phase with the largest duty setting value, the intermediate phase with the middle duty setting value, the magnitude of the duty setting value A comparison means for determining the smallest minimum phase;
Based on the PWM signal generated by the PWM signal generating means and the comparison result by the comparing means, the rising phase of the PWM signal corresponding to the intermediate phase is changed to the rising phase of the PWM signal corresponding to the maximum phase. Intermediate phase transfer means for delaying the current detection by a certain amount,
Based on the PWM signal generated by the PWM signal generation means and the comparison result by the comparison means, the rising phase of the PWM signal corresponding to the minimum phase is changed to that of the delayed phase of the PWM signal corresponding to the intermediate phase. Minimum phase shift means for delaying from the rising phase of the PWM signal corresponding to the maximum phase so as to be delayed by a certain amount capable of current detection from the rising phase,
The driving means drives the three-phase motor based on PWM signals of respective phases whose phases are shifted from each other by the intermediate phase moving means and the minimum phase moving means,
The motor control device according to claim 1, wherein the current detection means detects current in a predetermined section until a rise of each of the PWM signal corresponding to the intermediate phase and the PWM signal corresponding to the minimum phase. Three pairs of upper and lower arms each having a switching element on the upper arm and the lower arm are provided, and driving means for driving the three-phase motor based on on / off operation of each switching element by a PWM signal;
A single current detecting means for detecting a current value of each phase of the three-phase motor;
Duty setting means for setting a duty setting value according to the duty of the PWM signal of each phase based on the target current value of each phase and the current value of each phase detected by the current detection means;
Carrier signal generating means for generating a carrier signal;
PWM signal generation means for generating a PWM signal for each phase based on the duty setting value for each phase set by the duty setting means and the carrier signal generated by the carrier signal generation means;
Comparing the duty setting value of each phase set by the duty setting means, the maximum phase with the largest duty setting value, the intermediate phase with the middle duty setting value, the magnitude of the duty setting value A comparison means for determining the smallest minimum phase;
Based on the PWM signal generated by the PWM signal generating means and the comparison result by the comparing means, the rising phase of the PWM signal corresponding to the intermediate phase is changed to the rising phase of the PWM signal corresponding to the minimum phase. Rather than an intermediate phase transfer means that advances a certain amount of current detectable,
Based on the PWM signal generated by the PWM signal generating means and the comparison result by the comparing means, the rising phase of the PWM signal corresponding to the maximum phase is changed to that of the advanced PWM signal corresponding to the intermediate phase. A maximum phase moving means that advances from the rising phase of the PWM signal corresponding to the minimum phase so as to advance by a certain amount capable of detecting current from the rising phase;
The driving means drives the three-phase motor based on PWM signals of respective phases whose phases are shifted from each other by the intermediate phase moving means and the maximum phase moving means,
The motor control device according to claim 1, wherein the current detection means detects current in a predetermined section until a rise of each of the PWM signal corresponding to the intermediate phase and the PWM signal corresponding to the minimum phase. In the motor control device according to any one of claims 1 to 6,
The comparison means determines one of the two phases other than the maximum phase among the duty setting values set by the duty setting means as an intermediate phase and determines the other phase as the other phase. Is determined as the minimum phase. A pair of upper and lower arms each having switching elements on the upper arm and lower arm are provided according to the number of phases of four or more phases, and the multi-phase motor is driven based on the ON / OFF operation of each switching element by the PWM signal Driving means for
A single current detecting means for detecting a current value of each phase of the multiphase motor;
Duty setting means for setting a duty setting value according to the duty of the PWM signal of each phase based on the target current value of each phase and the current value of each phase detected by the current detection means;
Carrier signal generating means for generating a carrier signal;
Comparing means for comparing the duty setting values of the respective phases set by the duty setting means and determining the rank order of the duty setting values;
Based on the carrier signal generated by the carrier signal generation means and the comparison result by the comparison means, each phase other than the maximum phase is determined based on the rising phase of the carrier signal corresponding to the maximum phase having the largest duty setting value. Phase shift means for sequentially delaying the rising phase of the carrier signal corresponding to the phase by a predetermined amount capable of current detection according to the order of the magnitude of the duty setting value;
A PWM signal of each phase is generated based on the carrier signal of each phase shifted from each other by the phase shifting unit and the duty setting value of each phase set by the duty setting unit, and is output to the driving unit. PWM signal generating means,
The electric motor control device according to claim 1, wherein the current detection means detects current in a predetermined section until a rise of a PWM signal corresponding to each phase other than the maximum phase. A pair of upper and lower arms each having switching elements on the upper arm and lower arm are provided according to the number of phases of four or more phases, and the multi-phase motor is driven based on the ON / OFF operation of each switching element by the PWM signal Driving means for
A single current detecting means for detecting a current value of each phase of the multiphase motor;
Duty setting means for setting a duty setting value according to the duty of the PWM signal of each phase based on the target current value of each phase and the current value of each phase detected by the current detection means;
Carrier signal generating means for generating a carrier signal;
Comparing means for comparing the duty setting values of the respective phases set by the duty setting means and determining the rank order of the duty setting values;
Based on the carrier signal generated by the carrier signal generation means and the comparison result by the comparison means, each phase other than the minimum phase is based on the rising phase of the carrier signal corresponding to the minimum phase having the smallest duty setting value. Phase shift means for advancing the phase of the rising edge of the carrier signal corresponding to the phase by a certain amount capable of current detection sequentially in accordance with the rank order of the duty setting value;
A PWM signal of each phase is generated based on the carrier signal of each phase shifted from each other by the phase shifting unit and the duty setting value of each phase set by the duty setting unit, and is output to the driving unit. PWM signal generating means,
The motor control device according to claim 1, wherein the current detection means detects current in a predetermined section until a rise of a PWM signal corresponding to each phase other than the maximum phase having the largest duty setting value. A pair of upper and lower arms each having switching elements on the upper arm and lower arm are provided according to the number of phases of four or more phases, and the multi-phase motor is driven based on the ON / OFF operation of each switching element by the PWM signal Driving means for
A single current detecting means for detecting a current value of each phase of the multiphase motor;
Duty setting means for setting a duty setting value according to the duty of the PWM signal of each phase based on the target current value of each phase and the current value of each phase detected by the current detection means;
Carrier signal generating means for generating a carrier signal;
Comparing means for comparing the duty setting values of the respective phases set by the duty setting means and determining the rank order of the duty setting values;
Based on the carrier signal generated by the carrier signal generation means and the comparison result by the comparison means, the carrier signal corresponding to an arbitrary intermediate phase excluding the maximum phase having the largest duty setting value and the minimum phase having the smallest duty setting value. With respect to the phase of the rising edge, the phase of the carrier signal that is larger than the duty setting value of the intermediate phase can be detected in sequence according to the order of magnitude of the duty setting value for the phase of the carrier signal. For a phase that is advanced by a certain amount and whose duty setting value is smaller than the duty setting value of the intermediate phase, the phase of the rising edge of the carrier signal is a constant amount that can be detected in sequence according to the rank order of the duty setting value. Phase shifting means to delay only,
A PWM signal of each phase is generated based on the carrier signal of each phase shifted from each other by the phase shifting unit and the duty setting value of each phase set by the duty setting unit, and is output to the driving unit. PWM signal generating means,
The electric motor control device according to claim 1, wherein the current detection means detects current in a predetermined section until a rise of a PWM signal corresponding to each phase other than the maximum phase. A pair of upper and lower arms each having switching elements on the upper arm and lower arm are provided according to the number of phases of four or more phases, and the multi-phase motor is driven based on the ON / OFF operation of each switching element by the PWM signal Driving means for
A single current detecting means for detecting a current value of each phase of the multiphase motor;
Duty setting means for setting a duty setting value according to the duty of the PWM signal of each phase based on the target current value of each phase and the current value of each phase detected by the current detection means;
Carrier signal generating means for generating a carrier signal;
PWM signal generation means for generating a PWM signal for each phase based on the duty setting value for each phase set by the duty setting means and the carrier signal generated by the carrier signal generation means;
Comparing means for comparing the duty setting values of the respective phases set by the duty setting means and determining the rank order of the duty setting values;
Based on the PWM signal generated by the PWM signal generation means and the comparison result by the comparison means, each phase other than the maximum phase is based on the rising phase of the PWM signal corresponding to the maximum phase having the largest duty setting value. Phase shift means for delaying the phase of the rising edge of the PWM signal corresponding to the phase by a certain amount capable of detecting current sequentially in accordance with the order of the magnitude of the duty setting value;
The driving means drives the multiphase motor based on PWM signals of respective phases whose phases are shifted from each other by the phase moving means,
The electric motor control device according to claim 1, wherein the current detection means detects current in a predetermined section until a rise of a PWM signal corresponding to each phase other than the maximum phase. A pair of upper and lower arms each having switching elements on the upper arm and lower arm are provided according to the number of phases of four or more phases, and the multi-phase motor is driven based on the ON / OFF operation of each switching element by the PWM signal Driving means for
A single current detecting means for detecting a current value of each phase of the multiphase motor;
Duty setting means for setting a duty setting value according to the duty of the PWM signal of each phase based on the target current value of each phase and the current value of each phase detected by the current detection means;
Carrier signal generating means for generating a carrier signal;
PWM signal generation means for generating a PWM signal for each phase based on the duty setting value for each phase set by the duty setting means and the carrier signal generated by the carrier signal generation means;
Comparing means for comparing the duty setting values of the respective phases set by the duty setting means and determining the rank order of the duty setting values;
Based on the PWM signal generated by the PWM signal generation means and the comparison result by the comparison means, each phase other than the minimum phase is based on the rising phase of the PWM signal corresponding to the minimum phase having the smallest duty setting value. Phase shift means for advancing the phase of the rising edge of the PWM signal corresponding to the phase sequentially by a certain amount capable of current detection in accordance with the order of the magnitude of the duty setting value;
The driving means drives the multiphase motor based on PWM signals of respective phases whose phases are shifted from each other by the phase moving means,
The motor control device according to claim 1, wherein the current detection means detects current in a predetermined section until a rise of a PWM signal corresponding to each phase other than the maximum phase having the largest duty setting value. A pair of upper and lower arms each having switching elements on the upper arm and lower arm are provided according to the number of phases of four or more phases, and the multi-phase motor is driven based on the ON / OFF operation of each switching element by the PWM signal Driving means for
A single current detecting means for detecting a current value of each phase of the multiphase motor;
Duty setting means for setting a duty setting value according to the duty of the PWM signal of each phase based on the target current value of each phase and the current value of each phase detected by the current detection means;
Carrier signal generating means for generating a carrier signal;
PWM signal generation means for generating a PWM signal for each phase based on the duty setting value for each phase set by the duty setting means and the carrier signal generated by the carrier signal generation means;
Comparing means for comparing the duty setting values of the respective phases set by the duty setting means and determining the rank order of the duty setting values;
Based on the PWM signal generated by the PWM signal generation means and the comparison result by the comparison means, the PWM signal corresponding to an arbitrary intermediate phase excluding the largest phase having the largest duty setting value and the smallest phase having the smallest duty setting value. With respect to the phase of the rising phase, for the phase where the duty setting value is larger than the duty setting value of the intermediate phase, the phase of the rising edge of the PWM signal can be sequentially detected according to the rank order of the duty setting value. For a phase that is advanced by a fixed amount and whose duty setting value is smaller than the duty setting value of the intermediate phase, the phase of the rising edge of the PWM signal is sequentially fixed according to the order of the magnitude of the duty setting value. Phase shifting means for delaying only,
The driving means drives the multiphase motor based on PWM signals of respective phases whose phases are shifted from each other by the phase moving means,
The electric motor control device according to claim 1, wherein the current detection means detects current in a predetermined section until a rise of a PWM signal corresponding to each phase other than the maximum phase. In the motor control device according to any one of claims 8 to 13,
The motor control apparatus according to claim 1, wherein when the equal duty setting value exists among the duty setting values set by the duty setting means, the comparison means determines a different order for the duty setting value.

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