JP2000236258A - D/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce nonlinearity error of a conversion output. SOLUTION: This D/A converter is equipped with constant-current cells 1a to 63a and 1b to 63b constituting a constant-current matrix of 16 columns by 8 rows, an analog signal output terminal 66 where cell currents from constant-current cells having turned on are added, and a row decoder 64 and a column decoder 6, which generate column decoding signals x1 to x8 and row decoding signals ya1 to ya8 and yb1 to yb8 according to 6-bit digital input data DI and selectively turns on every two constant-current cells with those decoding signals. Constant-current cells ka and kb are two constant-current cells, which always turn on at the same time with the same decoding signal, have their cell currents set to a half as large as the step current of a D/A converter and are laid out where cell current variance due to the resistance component of a power line is compensated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current addition type in which a plurality of constant current cells integrated on a semiconductor substrate are selectively turned on, and the current from the turned on constant current cells is added to a common output terminal. The present invention relates to a D / A converter, and particularly to a D / A converter capable of reducing a non-linear error of a conversion output caused by a variation in a current value between the plurality of constant current cells.
It concerns a converter.

[0002]

2. Description of the Related Art A current addition type D / A converter in which a plurality of constant current cells are arranged in a matrix is called a current cell matrix type. High-speed D / A converters for video and the like are generally of the current cell matrix type.
As such a current cell matrix type D / A converter, for example, "An 80-MHz 8-bit CMOS D / A Converter"
(IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL.SC-21, N
O.6 DECEMBER 1986 pp.983-988). The current addition type D / A converters include those using GND as a reference for analog output and those using power supply voltage as a reference for analog output. As a conventional current addition type D / A converter, a current cell matrix type D / A converter using GND as a reference for analog output will be described below, but a power supply voltage is used as a reference for analog output. Can be similarly explained by exchanging the power supply and the GND.

FIG. 4 is a block diagram of a conventional current addition type 6-bit D / A converter (a layout diagram of a constant current cell is shown). FIG. 5 is a layout diagram of power supply lines in the D / A converter of FIG. D / in FIG.
The A converter includes 63 constant current cells 1 to 63, a row decoder (row decoder) 64, a column decoder (column decoder) 65, and an analog signal output terminal 66. A resistor 67 is usually provided between the output terminal 66 and GND.

The D / A converter of FIG. 4 includes d5, d4, d
Digital data DI consisting of 6 bits of 3, 3, d2, d1, and d0 is input. The lower three bits d2, d1, and d0 of the 6-bit input data DI are input to the column decoder 65, and the upper three bits d5, d4, and d3 are input to the row decoder 64.

[0005] 63 constant current cells 1 to 63 are laid out in a matrix of 8 columns and 8 rows on a semiconductor substrate.
A constant current cell matrix is formed. Row decoder 6
4 and the column decoder 65 generate column decode signals x1 to x8 and row decode signals ya1 to ya8, yb1 to yb8 according to the input data DI, and select the number of constant current cells corresponding to the input data DI by using these decode signals. On.

The turned-on constant current cells add a cell current Ic to the output terminal 66, respectively. The cell current Ic is D /
It is set to (the expected value of) the step current of the A converter Is.

When p (p is an arbitrary integer from 0 to 63) constant current cells are turned on in accordance with the input data DI, an output current IOUT = p × Is flows to the output terminal 66, and this output current IOUT is It becomes the analog output signal of the A converter. The D / A converter of FIG. 4 generates a 64-step analog output signal for 6-bit digital input data DI.

The first row of the constant current cell matrix composed of 63 constant current cells 1 to 63 includes a constant current cell 1
8 are laid out, and the eighth row includes constant current cells 57 to
63 is laid out. In the first column of the constant current cell matrix, constant current cells 7, 15, 23, 31,
39, 47, 55, 63 are laid out, and the eighth column includes constant current cells 1, 9, 17, 25, 33, 41, 4
9, 57 are laid out, and in the eighth column, constant current cells 8, 16, 24, 32, 40, 48, 56 are laid out.

The column decode signal x7 is input to the constant current cell in the first column, the column decode signal x1 is input to the constant current cell in the fourth column, and the column decode signal x1 is input to the constant current cell in the fifth column. The decode signal x2 is input, and the column decode signal x8 is input to the eighth column of constant current cells. That is, the first column to the first column on the layout of the constant current cell matrix
Eighth, when the column numbers are assigned as shown in FIG. 5, the column decode signal xi is input to the constant current cells in the column of the column number i (i is an arbitrary integer from 1 to 8). Also, the row decode signals yaj and ybj are input to the constant current cells in the j-th row (j is an arbitrary integer from 1 to 8).

FIG. 6 shows that a constant current cell is turned on / off by a column decode signal xi and a row decode signal yaj, ybj.
FIG. 9 is a diagram illustrating an off condition. Column decode signal x1
X8 becomes 1 (power supply Vd level) in order from x1 as the data value of the lower bits of the input data DI increases. x8 is always 0 (GND level). The row decode signals ya1 to ya8 and yb1 to yb8 become 1 sequentially from ya2 and yb1 as the data value of the upper bits of the input data DI increases. ya1 is always 1 and yb8 is always 0. Row decode signal ya (j
+1) and ybj are the same, so if ybj = 1, yaj = 1 will always be obtained.

The digital input data DI is, for example, 01
1110 (d0 = d5 = 0, d1 = d2 = d3 = d4 =
When 1), as shown in FIG. 7, x1 to x6 = 1,
x7 = x8 = 0, ya1 to ya4 = 1, ya5 to ya8
= 0, yb1 to yb3 = 1, yb4 to yb8 = 0, and all the constant current cells 1 to 24 in the first to third rows are set.
And the constant current cells 25 to 30 in the second to seventh columns of the fourth row, that is, in the columns of the fourth row to column numbers 1 to 6.
Is turned on, and the cell current Ic from the 30 current cells 1 to 30 is added to the output terminal 66. The other constant current cells 31 to 63 remain off. in this way,
The reference numerals attached to the constant current cells indicate the priority of turning on the constant current cells in the 63 constant current cells constituting the constant current cell matrix. The column numbers indicate the priority of turning on the constant current cells among the eight constant current cells laid out in the same row.

As shown in FIG. 5, a power supply pattern 71 for supplying a power supply voltage to the constant current cells 1 to 63 and eight power supply lines 72 are provided on the semiconductor substrate on which the constant current cell matrix is laid out. ing. The power supply pattern 71 is laid out outside the eighth column of the constant current cell matrix. The power supply lines 72 are laid out in the horizontal direction (row direction) from the power supply pattern 71 along the first to eighth rows of the constant current cell matrix. The constant current cells laid out in the same row are supplied with a power supply voltage from the same power supply line.

In the above constant current cell matrix,
As shown in FIG. 4 and FIG. 5, the constant current cells are not sequentially laid out in the priority order (the assigned code and column number) for turning on. This is for the reason described below.

As described in the above document, the width of the power supply line 72 cannot be made too large due to the limitation of the area of the constant current cell matrix. Therefore, as shown in FIG. 5, a voltage drop occurs in the power supply line 72 due to the resistance component R, and the power supply voltage supplied to the constant current cells laid out in the same row varies (slope in the column direction). I do. Due to the variation in the power supply voltage, the value of the cell current Ic output from the constant current cells in the same row varies (inclination in the column direction).
Therefore, if the constant current cells are sequentially laid out in terms of the priority order (the attached code and column number), the linearity of the converted output deteriorates.

Since the potential of the power supply line 72 at the column number 2 is higher than the potential at the column number 1 by the resistance component R of the power supply line, the cell current Ic of the constant current cell of the column number 2 is Min, higher than the constant current cell of column number 1. Conversely, the potential of the power supply line 72 at the column number 3 becomes lower than the potential at the column number 1 by the resistance component R, and the cell current Ic of the constant current cell of the column number 3 is accordingly reduced by the column. It is lower than the constant current cell of No. 1.

Assuming that the difference between the cell currents Ic between the constant current cells laid out in the adjacent columns is 2ΔIc, the cell current Ic in the fourth column (column No. 1) becomes a step current ( When the power supply voltage is set to be Is, the output from the constant current cells in the first to eighth columns (column numbers 8, 6, 4, 2, 1, 3, 5, 7) is obtained. Cell current Ic is Ie-6ΔI
c, Ie-4ΔIc, Ie-2ΔIc, Ie, Ie + 2
ΔIc, Ie + 4ΔIc, Ie + 6ΔIc, Ie + 8Δ
Ic. For example, when only the constant current cells in the columns of column numbers 1, 2, and 3 are turned on, the sum of the cell currents Ic is the expected value 3 × Ie.

The cell current Ic in the fourth column (column of column number 1) becomes Is-ΔIc, and the fifth column (column number 2)
Cell current Ic is Ic [9, j] = Is + ΔIc
When the power supply voltage is set so as to be as follows, the cell current Ic output from the constant current cells in the first to eighth columns (column numbers 8, 6, 4, 2, 1, 3, 5, and 7). Are Ie-7ΔIc, Ie-5ΔIc, and Ie-3ΔI, respectively.
c, Ie−ΔIc, Ie + ΔIc, Ie + 3ΔIc, I
e + 5ΔIc and Ie + 7ΔIc. For example, when only the constant current cells in the columns of column numbers 1, 2, 3, and 4 are turned on, the sum of the cell currents is the expected value 4 × Ie. Similarly, when the constant current cells up to the odd-numbered column number are turned on, the sum of the cell currents is as expected. Further, when all the constant current cells in the same row are turned on, the sum of the cell currents Ic from the row becomes the expected value 8 × I
e.

[0018]

However, in the above-mentioned conventional D / A converter, the power supply voltage is set so that the cell current Ic in the fourth column (the column of column number 1) becomes (the expected value of) the step current Is. When set, when the constant current cells up to the even-numbered column numbers are turned on, the sum of the cell currents Ic becomes higher than the expected value. For example, when only the constant current cells in the columns of the column numbers 1 and 2 are turned on, the sum of the cell currents Ic is 2 × Ie + ΔIc, which is different from the expected value 2 × Ie by ΔIc. When all the constant current cells are turned on, the sum of the cell currents Ic is
8 × Ie + 4ΔIc, which is 4ΔI from the expected value 8 × Ie.
c.

Conversely, the cell current Ic in the fourth column (column of column number 1) becomes Is-ΔIc, and the fifth column (column number 2)
Cell current Ic is Ic [9, j] = Is + ΔIc
When the constant current cells up to odd column numbers are turned on, the cell current I
The sum of c becomes lower than the expected value. For example, when only the constant current cells in the columns of the column numbers 1, 2, and 3 are turned on, the sum of the cell currents Ic is the expected value 3 × Ie−3Δ
Ic, which is 3ΔIc shifted from the expected value 3 × Ie. When the constant current cells in the columns 1 to 7 are turned on, the sum of the cell currents Ic is 7 × Ie−7ΔI
c, which is shifted from the expected value 7 × Ie by 7ΔIc.

As described above, in the above-mentioned conventional D / A converter, the cell current varies in the direction in which the power supply line extends, and the cell current variation cannot be canceled depending on the number of constant current cells to be turned on. Therefore, there is a problem that a non-linear error occurs in the converted output.

In general, when a large number of constant current cells are laid out in a matrix on a semiconductor substrate, the characteristics of the constant current cells themselves vary due to process variations caused by the semiconductor manufacturing process. The current value varies. This variation in the cell current value does not occur randomly in the layout of the constant current cell, but changes so that the cell current value at one end of the constant current cell matrix is low and the cell current value is sequentially increased from that position. It has been experimentally confirmed that such a variation is a variation having a slope in a certain direction. In the above-mentioned conventional D / A converter, there is a problem that the cell current variation (variation inclined in a certain direction) due to the characteristic variation of the constant current cell cannot be canceled, and the nonlinearity error of the conversion output increases. there were.

The present invention has been made to solve such a conventional problem, and has as its object to reduce a non-linear error of a converted output.

[0023]

In order to achieve the above object, a D / A converter according to a first aspect of the present invention is a current adding type D / A converter, comprising: a plurality of constant current cells; An output terminal to which the current from the turned on constant current cell is added, and a decoder circuit for selectively turning on the plurality of constant current cells in units of an even number according to input data.

According to a second aspect of the present invention, there is provided a D / A converter according to the first aspect, wherein the plurality of constant current cells are two or more.
.Times.M columns and N rows (M and N are positive integers) in a matrix, wherein the decoder circuit selectively turns on the constant current cells in units of two, Are arranged in different columns from each other.

According to a third aspect of the present invention, in the D / A converter according to the second aspect, the two constant current cells are arranged in the (M-i + 1) th column (i is an arbitrary number from 1 to M). Integer),
It is characterized by comprising a constant current cell laid out in the j-th row (j is an arbitrary integer from 1 to N) and a constant current cell laid out in the (M + i) -th column and the j-th row. Is what you do.

According to a fourth aspect of the present invention, there is provided a D / A converter according to the first aspect, wherein the plurality of constant current cells are two or more.
It is laid out in a matrix of × M columns and 2 × N rows (M and N are positive integers), and the decoder circuit selectively turns on the constant current cells in units of four. Things.

According to a fifth aspect of the present invention, there is provided a D / A converter according to the fourth aspect, wherein the four constant current cells are arranged in the (M-i + 1) th column (i is an arbitrary number from 1 to M). Integer),
(N-j + 1) th row (j is any integer from 1 to N)
, A constant current cell laid out in the (M + i) th column and the (N−j + 1) th row, and a constant current cell laid out in the (M−i + 1) th and the (N + j) th row. And a constant current cell laid out in the (M + i) th column and the (N + j) th row.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment FIG. 1 is a block diagram of a current addition type 6-bit D / A converter according to a first embodiment of the present invention. is there). The D / A converter of FIG. 1 has 126 constant current cells 1a to 63a and 1b to 63b.
, A row decoder (row decoder) 64, a column decoder (column decoder) 65, and an analog signal output terminal 66. Also, between the output terminal 66 and GND,
Usually, a resistor 67 for converting the current added to the output terminal 66 into a voltage is provided.

The D / A converter of FIG. 1 has d5, d4, d
Digital data DI consisting of 6 bits of 3, 3, d2, d1, and d0 is input. The lower three bits d2, d1, and d0 of the 6-bit input data DI are input to the column decoder 65, and the upper three bits d5, d4, and d3 are input to the row decoder 64. The lower three bits of the input data DI are denoted by DIw, and the upper three bits of data are denoted by DIh.

126 constant current cells 1a to 63a, 1b
63b are laid out in a matrix of 16 columns and 8 rows on a semiconductor substrate to form a constant current cell matrix. Row decoder 64 and column decoder 65
Are column decode signals x1 to x1 according to the input data DI.
x8 and the row decode signals ya1-ya8, yb1-
yb8 is generated, and the constant current cells are selectively turned on in units of two by these decode signals, and the number of constant current cells corresponding to the input data DI is turned on. That is, 2 × p (p is an arbitrary integer from 0 to 63) constant current cells are selectively turned on in accordance with the input data DI.

The constant current cells ka and kb (k is an arbitrary integer from 1 to 63) are laid out in different columns of the same row, and form a two-unit cell group which is always turned on at the same time. The turned on constant current cell is connected to the output terminal 66.
To the cell current Ic. The cell current Ic is
1/2 of (the expected value of) the step current Is of the D / A converter
Is set to That is, in the D / A converter of FIG. 1, the constant current cell in which the cell current Ic is set to に of the step current Is is turned on in units of two, so that the output terminal 6 is turned on.
6, the step current Is is added.

When 2 × p constant current cells are turned on in accordance with the input data DI, an output current IOUT = p × Is flows to the output terminal 66, and this output current IOUT becomes an analog output signal of the D / A converter. The D / A converter of FIG.
A 64-step analog output signal is generated for the bit digital input data DI.

The column decoder 65 outputs column input data DIw (lower 3 bit data d2, d of the input data DI).
In accordance with (1, d0), column decode signals x1 to x8 of 0 (GND level) or 1 (power supply Vd level) are generated. Note that the column decode signal x8 is always 0.

When DIw = 000, x1 to x8 = 0, and when DIw = 001 (d2 = d1 = 0, d0 = 1), x1 = 1 and x1 to x8 = 0. Similarly,
Every time the value of DIw increases, it changes from 0 to 1 in the order of x2, x3,... When DIw = 110, x1 to x6 = 1, x
7 = x8 = 0, and when DIw = 111, x1 to x
7 = 1, x8 = 0. Therefore, if xi = 1 (i is an arbitrary integer from 1 to 8), x1 to x (i-1) =
It is one.

The row decoder 64 receives the row input data DI
h (the upper three bits d5, d4 of the input data DI
According to d3), 0 (GND level) or 1 (power supply V
(d level) row decode signals ya1 to ya8, yb1
To yb8. Note that the row decode signal ybj
(J is an arbitrary integer from 1 to 8) and the row decode signal ya (j + 1) are the same signal. The row decode signal ya1 is always 1 and the row decode signal yb8 is always 0.

When DIh = 000, ya1 = 1, ya
2−ya8 = 0, yb1−yb7 = 0, y8 = 0, and when DIh = 001 (d5 = d4 = 0, d3 = 1), ya1 = ya2 = 1, ya3 to ya8 = 0, yb1
= 1, yb2 to yb8 = 0. Similarly, DIw
(Yb2, ya4... (Yb2, ya4)
3 ...) in order from 0 to 1, and when DIh = 110,
ya1 to ya7 = 1, ya8 = 0, yb1 to yb6 =
1, yb7 = yb8 = 0, and when DIh = 111, ya1 to ya8 = 1, yb1 to yb7 = 1, yb8
= 0. Therefore, if yaj = 1, ya1 to ya
(J-1) = 1 and yb1 to yb (j-1) = 1.

126 constant current cells 1a to 63a, 1b
Of the constant current cell matrix composed of
In the row, the constant current cells 8a to 1a and 1b to 8b are laid out, and in the second row, the constant current cells 16a to 9a, 9b to
16b is laid out. Similarly, in the seventh row, constant current cells 56a to 49a and 49b to 56b are laid out, and in the eighth row, constant current cells 63a to 57a,
57b to 63b are laid out.

In the first column of the constant current cell matrix, constant current cells 8a, 16a, 24a, 32a, 40
a, 48a, and 56a are laid out. In the second column, constant current cells 7a, 15a, 23a, 31a, 39a, 47
a, 55a and 63a are laid out. Similarly, in the eighth column, the constant current cells 1a, 9a, 17a, 25
a, 33a, 41a, 49a, and 57a are laid out, and the ninth column includes constant current cells 1b, 9b, 17b, and 25.
b, 33b, 41b, 49b, and 57b are laid out, and the 15th column includes constant current cells 7b, 15b, 23b,
31b, 39b, 47b, 55b and 63b are laid out, and the 16th column includes constant current cells 8b, 16b and 24b.
b, 32b, 40b, 48b, and 56b are laid out.

The column decode signal x1 is input to the constant current cells in the eighth and ninth columns, and the constant current cells in the seventh and tenth columns are input.
A column decode signal x2 is input to the constant current cells in the column. Similarly, a column decode signal x7 is input to the constant current cells in the second and fifteenth columns, and a column decode signal x8 is applied to the constant current cells in the first and sixteenth columns.
Is entered. That is, the (9-i) th column and the (8+
i) The column decode signal xi is input to the constant current cells in the column.

The row decode signals ya1 and yb1 are input to the constant current cells in the first row, and the row decode signals ya2 and yb2 are input to the constant current cells in the second row. Similarly, the row decode signals ya7 and yb7 are input to the constant current cells in the seventh row, and the row decode signals ya8 and yb8 are input to the constant current cells in the eighth row.
Is entered. That is, the row decode signals yaj and ybj are input to the j-th row constant current cell.

Here, for example, the constant current cell 1a laid out in the eighth column and the first row will be referred to as a constant current cell [8, 1]. According to this notation, the (9-i)
The constant current cell laid out in the column and the j-th row is a constant current cell [9-i, j], and the constant current cell laid out in the (8 + i) -th column and the j-th row is constant current cell [8 + i,
j].

Constant current cells ka and kb (k is 1 to 63) forming a two-unit cell group which is always turned on at the same time.
Are turned on / off by the same column decode signal and row decode signal according to the conditions of FIG. For example, the constant current cells 1a and 1b both have a column decode signal x1 and a row decode signal ya
It is turned on / off by 1 and yb1. That is, the constant current cells [9-
i, j] and the constant current cell [8 + i, j] are both a column decode signal xi and a row decode signal yaj, yb.
It is turned on / off by j.

FIG. 2 is a diagram showing an example of the internal configuration of the constant current cell ([9-i, j] or [8 + i, j]). In FIG. 2, the constant current cell is a pMOS transistor 8
1, 82, nMOS transistors 83 and 84, reference current source 85, OR gate 86, NAND gate 87
And an inverter 88.

The source electrodes of the pMOSs 81 and 82 are
The gate electrodes of the pMOSs 81 and 82 are connected to the drain electrode of the pMOS 82,
The drain electrode of the OS 82 is grounded via the reference current source 85. The drain electrodes of the nMOS 83 and 84 are connected to the drain electrode of the pMOS 81. n
The gate electrode of the MOS 83 is connected to the output terminal of the inverter 88, and the source electrode of the nMOS 83 is connected to the analog signal output terminal 66 of the D / A converter. nM
The gate electrode of the OS 84 is connected to the input electrode of the inverter 88, and the source electrode of the nMOS 84 is grounded. The first input terminal of the OR gate 86 receives the column decode signal xi, and the second input terminal receives the row decode signal ybj. First of NAND gate 87
The input terminal is connected to the output terminal of the OR gate 86, the second input terminal receives the row decode signal yaj,
The output terminal is connected to the input terminal of the inverter 87.

The reference current source 85 is a constant current source using, for example, a band gap reference circuit. pMOS81
Is a constant current source transistor for flowing the cell current Ic,
The nMOS 83 is a switch transistor that opens and closes a current path between the pMOS 81 and the output terminal 66 and turns on / off a constant current cell. pMOSs 81 and 82;
The reference current source 85 constitutes a current mirror circuit, and outputs a cell current Ic corresponding to the value of the reference current Ir flowing through the reference current source 85 to a pMOS8 which is a constant current source transistor.
Pour into 1. The cell current Ic is determined by the power supply voltage, pMO
Dimensions of S81 and pMOS82, source /
It fluctuates due to variations in characteristics such as the impurity concentration of the drain.

The constant current cell shown in FIG. 2 is turned on / off according to the conditions shown in FIG. 6 by the column decode signal xi and the row decode signals yai, ybi. First, ybi = 0
(GND level, L level), xi = yai =
If it is 1 (power level, H level), the output of the NAND gate 87 becomes L level, and the output of the inverter 88 becomes H level. This turns on the constant current cell (nMOS
83 is on, nMOS 84 is off), and the cell current Ic is added to the output terminal 66. If xi = 0 or yai = 0, the output of the NAND gate 87 goes high and the output of the inverter 88 goes low, turning off the constant current cell (the nMOS 83 is off and the nMOS 84 is on). Next, when ybi = 1, yai = 1 always holds, so
Regardless of xi, the output of the NAND gate 87 goes low and the output of the inverter 88 goes high, turning on the constant current cell.

In the layout area of one constant current cell, the area occupied by the constant current source transistor (pMOS 81) is the largest. The area of the constant current source transistor increases as the cell current Ic increases (the dimension increases). In the D / A converter according to the first embodiment, since the cell current Ic is set to の of the step current Is, the layout area of one constant current cell is reduced to the step current Is. Set the conventional D
/ A converter can be smaller.

The digital input data DI is, for example, 01
1110 (d0 = d5 = 0, d1 = d2 = d3 = d4 =
When 1), x1 to x6 = 1, x7 = x8 =
0, ya1 to ya4 = 1, ya5 to ya8 = 0, yb1
Yb3 = 1, yb4 to yb8 = 0, and all the constant current cells 1a to 24a and 1b to 2 in the first to third rows.
4b and the constant current cells 25a to 30a and 25b to 30b in the third to fourteenth columns of the fourth row are turned on.
The cell currents Ic from the current cells 1a to 30a and 1b to 30b are added to the output terminal 66. The other constant current cells 31a to 63a and 31b to 63b remain off. As described above, the reference numerals assigned to the constant current cells indicate the priority of turning on the constant current cells in the 126 constant current cells constituting the constant current cell matrix. Also, as shown in FIG. 1, column numbers 1a to 8a and 1b are provided in the first to sixteenth columns on the layout of the constant current cell matrix.
When “−8b” is added, this column number indicates the priority order of turning on the constant current cells among the 16 constant current cells laid out in the same row.

Although not shown in FIG. 1, a power supply pattern and a power supply line for supplying a power supply voltage to the constant current cells 1a to 63a and 1b to 63b are provided on the semiconductor substrate on which the above constant current cell matrix is laid out. It is laid out. The power supply patterns and power supply lines are laid out as shown in FIG. In other words, the power pattern
It is laid out outside the 16th column of the constant current cell matrix. In addition, power supply lines whose width cannot be made too large due to restrictions on the area of the constant current cell matrix are
A total of eight layouts are arranged in the horizontal direction (row direction) from the power supply pattern along the first to eighth rows of the constant current cell matrix. The constant current cells laid out in the same row are supplied with a power supply voltage from the same power supply line.

Due to the voltage drop in the power supply line, the power supply voltage supplied to the constant current cell varies (slope in the column direction), and the power supply voltage supplied to the constant current cell [16, j] becomes the highest. As the distance from the pattern increases, the power supply voltage decreases in the order of the constant current cells [15, j], [14, j], and the power supply voltage supplied to the constant current cell [1, j] becomes the lowest. As a result, the cell current Ic of the constant current cell set to の of the (expected value) of the step current Is also varies (in the column direction). The cell current Ic from the constant current cell [16, j] becomes the largest, and as the distance from the power supply pattern increases, the cell current Ic in the order of the constant current cells [15, j], [14, j].
Becomes smaller, and the cell current I from the constant current cell [1, j] becomes smaller.
c is the lowest.

Here, for example, the constant current cell [8, 1] (=
The cell current from the constant current cell 1a) will be denoted by Ic [8, 1]. According to this notation, the cell current from the constant current cell [9-i, j] is Ic [9-i, j], and the cell current from the constant current cell [8 + i, j] is Ic
[8 + i, j]. Further, the constant current cell [9-i, j] of the column number ia is separately described as a constant current cell <ia, j>, and the cell current Ic [9-i, j] is represented by Ic <ia, j>.
Will be described separately. Further, the constant current cell [8 + i, j] of the column number ib is separately described as a constant current cell <ib, j>, and the cell current Ic is separately described as Ic <ib, j>.

It is assumed that the difference in cell current Ic between constant current cells laid out in adjacent columns is 2ΔIc, and in a constant current cell matrix having such a cell current gradient variation, Ic <1a , J> = Ic [8, j] = 0.5 Is−Δ
Ic, Ic <1b, j> = Ic [9, j] 0.5Is + ΔI
When the power supply voltage is set to be c, the constant current cell <8
a, j> to <2a, j>, <2b, j> to <8b, j>
Are respectively Ic <8a, j> = Ic [1, j] = 0.5Is-1
5ΔIc, Ic <7a, j> = Ic [2, j] = 0.5 Is−1
3ΔIc, Ic <6a, j> = Ic [3, j] = 0.5 Is−1
1ΔIc, Ic <5a, j> = Ic [4, j] = 0.5Is−
9ΔIc, Ic <4a, j> = Ic [5, j] = 0.5Is−
7ΔIc, Ic <3a, j> = Ic [6, j] = 0.5 Is−
5ΔIc, Ic <2a, j> = Ic [7, j] = 0.5Is−
3ΔIc, Ic <2b, j> = Ic [10, j] = 0.5Is +
3ΔIc, Ic <3b, j> = Ic [11, j] = 0.5Is +
5ΔIc, Ic <4b, j> = Ic [12, j] = 0.5 Is +
7ΔIc, Ic <5b, j> = Ic [13, j] = 0.5 Is +
9ΔIc, Ic <6b, j> = Ic [14, j] = 0.5 Is + 1
1ΔIc, Ic <7b, j> = Ic [15, j] = 0.5Is + 1
3ΔIc, Ic <8b, j> = Ic [16, j] = 0.5Is + 1
5ΔIc.

Therefore, any of the constant current cells <ia, j>,
The cell current from <ib, j> is: Ic <ia, j> = Ic [9-i, j] = 0.5 Is−ΔIc− (i−1) × 2ΔIc Ic <ib, j> = Ic [8 + i , J] = 0.5Is + ΔIc + (i−1) × 2ΔIc, and the total Ic <ia, j> + Ic <ib, j>
Becomes the expected value Is of the step current.

As described above, in the D / A converter of FIG. 1, the constant current cell [9-i, j] of the column number ia and the constant current cell [9-i] of the column number ib which constitute the above-described two-unit cell group. 8 + i, j] are laid out at complementary positions where the cell current variation inclined in the column direction can be canceled. Therefore, even if there is a cell current variation inclined in the column direction and p is an odd number or an even number, the output current IOUT when 2 × p constant current cells are turned on according to the input data DI. Becomes p × Is, which is the expected value, so that the nonlinearity error of the converted output can be reduced.

As described above, according to the first embodiment, the constant current cells are turned on in units of two, and the constant current cells that are turned on in units of two are replaced with the (9-i) -th constant current cell matrix.
By laying out the column, the j-th row, and the (8 + i) -th column, the j-th row, the variation in the column direction of the cell current caused by the resistance component of the power supply line can be canceled for any input data. And a D / A converter excellent in the linearity of the conversion output can be provided.

Second Embodiment FIG. 3 is a layout diagram of a constant current cell in a current addition type 6-bit D / A converter according to a second embodiment of the present invention. The D / A converter according to the second embodiment includes 252 constant current cells 1a to 63a, 1b to 63b, 1c to 63c, 1
d to 63d and a row decoder (row decoder 6 in FIG. 1).
4) and a column decoder (column decoder 65 in FIG. 1)
And an analog signal output terminal (the output terminal 66 in FIG. 1).

252 constant current cells 1a to 63a, 1b
63b, 1c to 63c, and 1d to 63d are laid out in a matrix of 16 columns and 16 rows on a semiconductor substrate to form a constant current cell matrix. The row decoder and the column decoder generate column decode signals x1 to x8 and row decode signals ya1 to ya8, yb1 to yb8 in accordance with 6-bit input data, and selectively output constant current cells in units of four by these decode signals. It is turned on, and the number of constant current cells corresponding to the input data is turned on. That is, 4 × p (p is 0) according to the input data.
(Arbitrary integer from to 63) is selectively turned on.

The constant current cells ka, kb, kc, kd (k is an arbitrary integer from 1 to 63) constitute a cell group of four units which are always turned on at the same time. The turned on constant current cells add the cell current Ic to the output terminal 66, respectively. The cell current Ic is set to １ ／ of (the expected value of) the step current Is of the D / A converter. That is, in the D / A converter of the first embodiment, the constant current cell in which the cell current Ic is set to １ ／ of the step current Is is turned on in units of four, so that the step current Is is output to the output terminal 66. to add.

When 4 × p constant current cells are turned on according to 6-bit input data, output current IOUT = p × Is
Flows into the output terminal 66, and this output current IOUT
It becomes the analog output signal of the converter. D of the second embodiment
The / A converter generates a 64-step analog output signal for the 6-bit digital input data DI.

252 constant current cells 1a to 63a, 1b
To 63b, 1c to 63c, and 1d to 63d, the first row of the constant current cell matrix includes
c to 57c, 57d to 63d are laid out, constant current cells 8c to 1c, 1d to 8d are laid out in the eighth row, and constant current cells 8a to 1a, 1b to 8b are laid out in the ninth row.
Is laid out.

The first column of the constant current cell matrix includes constant current cells 56c, 48c, 40c, 32c, 24
c, 16c, 8c, 8a, 16a, 24a, 32a, 4
0a, 48a, and 56a are laid out.
The constant current cells 57c, 49c, 41c, 33c, 25c,
17c, 9c, 1c, 1a, 9a, 17a, 25a, 3
3a, 41a, 49a, and 57a are laid out,
The columns include constant current cells 57d, 49d, 41d, 33d,
25d, 17d, 9d, 1d, 1b, 9b, 17b, 2
5b, 33b, 41b, 49b, and 57b are laid out. In the fifteenth column, constant current cells 7b, 15b, 23b,
31b, 39b, 47b, 55b and 63b are laid out, and the 16th column includes constant current cells 56d, 48d and 40b.
d, 32d, 24d, 16d, 8d, 8b, 16b, 2
4b, 32b, 40b, 48b, and 56b are laid out.

The column decode signal xi is input to the (9-i) th column (i is an arbitrary integer from 1 to 8) and the (8 + i) th column of the constant current cells. Also, the (9-j)
Row (j is any integer from 1 to 8) and (8+
j) The row decode signals yaj, y
bj is input. Therefore, the constant current cells [9-i, 8+
j], [8 + i, 8 + j], [9-i, 9-j], [8
+ I, 9-j] are turned on / off by the column decode signal xi and the row decode signals yaj, ybj.

The internal configuration of the constant current cell of the second embodiment is the same as that of FIG. In the D / A converter according to the second embodiment, since the cell current Ic is set to １ ／ of the step current Is, the layout area of one constant current cell is
It can be smaller than the D / A converter of the first embodiment.

The digital input data DI is, for example, 01
When it is 1110, x1 to x6 = 1, x7 = x8
= 0, ya1 to ya4 = 1, ya5 to ya8 = 0, yb
1 to yb3 = 1, yb4 to yb8 = 0, and all the constant current cells 1a to 24a, 1b from the sixth row to the eleventh row
To 24b, 1c to 24c, 1d to 24d, and the constant current cells 25c to 30c, 2 in the third to fourteenth columns of the fifth row.
5d to 30d and the constant current cells 25a to 30a and 25b to 30b in the twelfth row from the third column to the fourteenth column are turned on, and these 1200 current cells 1a to 30a, 1b to
30b, 1c-30c, and cell current I from 1d-30d
c is added to the analog signal output terminal. Other constant current cells 31a-63a, 31b-63b, 31c-
63c, 31d to 63d remain off.

Here, for example, the cell current from the constant current cell 1a is expressed as Ic (1a). According to this notation, the cell currents from the constant current cells ka, kb, kc, kd are Ic (ka), Ic (kb), Ic, respectively.
(Kc) and Ic (kd).

Due to the resistance component of the power supply line and the process variation, the D / A converter according to the second embodiment has the constant current cell matrix (first column, first column, In the 16th row, there is no constant current cell, but it is assumed that there is one), the cell current value becomes the lowest, and the 16th column,
The cell current value of which the cell current value increases sequentially toward the constant current cell in the first row (there is no constant current cell in the first column and the sixteenth row, but it is assumed that there is one). Assume that it is manufactured with inclination variation. Further, the cell current variation in the column direction has a slope twice as large as the cell current variation in the row direction, and the difference in cell current Ic between the constant current cells laid out in adjacent columns is 4ΔIc, The difference in cell current Ic between the constant current cells laid out in adjacent rows is 2
It is assumed that ΔIc. In a constant current cell matrix having such a slope variation of the cell current Ic, Ic (1a) = Ic [8,9] = 0.25Is-3ΔI
c, Ic (1b) = Ic [9,9] = 0.25Is−ΔI
c, Ic (1c) = Ic [8,8] = 0.25Is + ΔI
c, Ic (1d) = Ic [9,8] = 0.25Is + 3ΔI
When the power supply voltage is set so as to be c, for example, the cell currents of the constant current cells 63a, 63b, 63c, and 63d constituting the above-described four-unit cell group are Ic (63a) = Ic [ 2,16] = 0.25 Is-
41ΔIc, Ic (63b) = Ic [15,16] = 0.25Is−
11ΔIc, Ic (63c) = Ic [2,1] = 0.25Is +
11ΔIc, Ic (63d) = Ic [15, 1] = 0.25Is +
41ΔIc, and the sum thereof becomes the expected value Is.

The same applies to the other cell groups forming the above-described four-unit cell group. The cell currents of the constant current cells ka, kb, kc, kd forming the cell group are respectively Ic (ka) = Ic [9-i, 8 + j] = 0.25Is
−3ΔIc− (i−1) × 4ΔIc− (j−1) × 2Δ
Ic, Ic (kb) = Ic [8 + i, 8 + j] = 0.25Is
−ΔIc− (i−1) × 4ΔIc + (j−1) × 2ΔI
c, Ic (kc) = Ic [9-i, 9-j] = 0.25Is
+ ΔIc + (i−1) × 4ΔIc− (j−1) × 2ΔI
c, Ic (kd) = Ic [8 + i, 9-j] = 0.25Is
+ 3ΔIc + (i−1) × 4ΔIc + (j−1) × 2Δ
Ic, and the sum Ic (ka) + Ic (kb) + Ic
(Kc) + Ic (kd) becomes the expected value Is of the step current.

As described above, the constant current cells ka ([9-i, 8 + j]), k
b ([8 + i, 8 + j]), kc ([9-i, 9-
j]) and kd ([8 + i, 9-j]) are laid out at complementary positions where cell current variations inclined in an arbitrary direction can be canceled. Therefore, even if there is a cell current variation inclined in an arbitrary direction and p is an odd number or an even number, the output current IOUT when 4 × p constant current cells are turned on according to the input data. Is p ×
Since Is is equal to the expected value, the nonlinearity error of the converted output can be reduced.

As described above, according to the second embodiment, the constant current cells are turned on in units of four, and the constant current cells ka, kb, kc, and kd that are turned on in units of four are replaced with a constant current cell matrix. (9-i) th column, (8 + j) th row, and (8-j) th
+ I) column, (8 + j) th row, and (9-i) th column, (9-j)
j), the (8 + i) -th column, and the (9-j) -th row are laid out, so that the cell current variation in an arbitrary direction caused by the resistance component of the power supply line and the process variation can be arbitrarily input. Can be canceled, so that a D / A converter excellent in the linearity of the conversion output can be provided.

[0070]

As described above, according to the present invention, a constant current cell is selectively turned on in units of an even number, and the even number of constant current cells serving as the selection unit can cancel the cell current variation. By laying them out at appropriate positions, it is possible to provide a D / A converter having excellent linearity of the conversion output.

[Brief description of the drawings]

FIG. 1 is a block diagram of a current addition type 6-bit D / A converter according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of an internal configuration of a constant current cell.

FIG. 3 is a layout diagram of a constant current cell in a current addition type 6-bit D / A converter according to a second embodiment of the present invention.

FIG. 4 is a block diagram of a conventional current addition type 6-bit D / A converter.

FIG. 5 is a layout diagram of power supply lines in the 6-bit D / A converter of FIG.

FIG. 6 is a diagram for explaining on / off conditions of a constant current cell based on a decode signal.

FIG. 7 is a diagram illustrating the operation of a conventional current addition type 6-bit D / A converter.

[Explanation of symbols]

1a to 63a, 1b to 63b, 1c to 63c, 1d to 6
3d constant current cell, 64 row decoder, 65 column decoder, 66 analog signal output terminal.

Claims (5)

[Claims] 1. A current adding type D / A converter, comprising: a plurality of constant current cells; an output terminal for adding current from a turned on constant current cell; and an even number of the plurality of constant current cells according to input data. And a decoder circuit for selectively turning on the unit. 2. The method according to claim 1, wherein the plurality of constant current cells are 2 × M columns, N
The decoder circuit is laid out in a matrix of rows (M and N are positive integers), and the decoder circuit selectively turns on the constant current cells in units of two, and the two units serving as selection units of the decoder circuit are selected. 2. The D / A converter according to claim 1, wherein the constant current cells are arranged in different columns. 3. The two constant current cells are arranged in the (M−i + 1) th column (i is an arbitrary integer from 1 to M) and the jth row (j is an arbitrary integer from 1 to N). 2. The D / A converter according to claim 1, comprising a laid-out constant current cell and a constant current cell laid out in the (M + i) -th column and the j-th row. 4. The method according to claim 1, wherein the plurality of constant current cells include 2 × M columns, 2 × M columns.
2. The layout according to claim 1, wherein the decoder circuit is laid out in a matrix of × N rows (M and N are positive integers), and the decoder circuit selectively turns on the constant current cells in units of four. D / A
converter. 5. The four constant current cells include a (M−i + 1) th column (i is an arbitrary integer from 1 to M) and a (N−j + 1) th row (j is an arbitrary number from 1 to N). ), A constant current cell laid out in the (M + i) th column and the (N−j + 1) th row, and a constant current cell laid out in the (M−i + 1) th and the (N + j) th row. 5. The D / A converter according to claim 4, wherein the D / A converter comprises a constant current cell and a constant current cell laid out in the (M + i) th column and the (N + j) th row.