JP2000228430A - Apparatus, system and method for inspecting circuit pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an image function of an inspecting apparatus and to thereby make the apparatus user-friendly by extracting the feature of a defect from an image of the defect obtained through injection of a charged particle beam, classifying the defect based on the feature, and re-obtaining an image of the defect based on the classification through injection of a charged particle beam. SOLUTION: After inspection conditions have been set and inspection has been performed, an extracted defect is recognized and classified in a defect recognition mode. First, whether or not an SEM image formed by irradiation is an automatically classifiable image is judged (301). In not, the SEM image is re-obtained manually and displayed. If so, the defect is classified through a classification judgment (303). This classification operation is performed on the basis of whether or not the position, size and the like of the displayed defect is larger than a preset value. If the defect matches the classification, the SEM image is automatically re-obtained and displayed (304). Next, the inspection result is outputted (305).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit pattern inspection apparatus and method for manufacturing a substrate having a fine circuit pattern such as a semiconductor device, a photomask, and a liquid crystal.

[0002]

2. Description of the Related Art An inspection of a semiconductor wafer will be described as an example. 2. Description of the Related Art A semiconductor device is manufactured by repeating a process of transferring a pattern formed in a photomask on a semiconductor wafer by lithography and etching. In the manufacturing process of a semiconductor device, the quality of a lithography process, an etching process, and the like, the occurrence of foreign matter, and the like greatly affect the yield of the semiconductor device. Conventionally, a method for inspecting a pattern on a wafer has been implemented.

As a method of inspecting a defect existing in a pattern on a semiconductor wafer, a defect inspection apparatus that irradiates a semiconductor wafer with white light and compares the same type of circuit patterns of a plurality of LSIs using an optical image has been commercialized. Have been. For an overview of the inspection method, see the magazine "Monthly Semiconductor World" 19
August 1995, pp. 96-99.
In addition, the inspection method using an optical image is disclosed in
As described in Japanese Patent No. 7456, an optically illuminated area on a substrate is imaged by a time delay integration sensor, and a defect is detected by comparing the image with a design characteristic input in advance. As described in Japanese Patent Publication No. 6-58220, there is disclosed a method for monitoring a deterioration of an image at the time of acquiring an image and correcting the deterioration at the time of detecting the image to perform a comparative inspection with a stable optical image. . When a semiconductor wafer in a manufacturing process is inspected by such an optical inspection method, no residue or defect of a pattern having a surface of a silicon oxide film or a photosensitive photoresist material through which light is transmitted cannot be detected. In addition, it was not possible to detect an etching residue or a non-opening defect of a minute conduction hole, which was lower than the resolution of the optical system. Furthermore, a defect generated at the bottom of the step of the wiring pattern could not be detected.

[0004] As described above, with the miniaturization of circuit patterns, the complexity of circuit pattern shapes, and the diversification of materials, it has become difficult to detect defects using optical images. There has been proposed a method of comparing and inspecting a circuit pattern by using the method. In order to obtain a practical inspection time when comparing and analyzing circuit patterns with electron beam images, a scanning electron microscope (Scanning Electron M
It is necessary to acquire an image at a very high speed as compared with observation by an icroscope (hereinafter abbreviated as SEM). Then, it is necessary to ensure the resolution of the image acquired at high speed and the SN ratio of the image.

As an apparatus for comparing and inspecting patterns using an electron beam, “Journal of Vacuum Science, Inc.
Technology Bee, Vol. 9, No. 6, pp. 3005-3009, 1991 (J. Vac. Sci. Tech. B, Vol.
9, No. 6, pp. 3005-3009 (1991)), "Journal of Vacuum Science Technology B", No. 1
Vol. 0, No. 6, pages 2804 to 2808, 1992
(J. Vac. Sci. Tech. B, Vol. 10, No. 6, pp. 2804-2
808 (1992)), and JP-A-5-258703,
U.S. Pat. No. 5,502,306 discloses one of the usual SEMs.
A conductive substrate (such as an X-ray mask) is irradiated with an electron beam having an electron beam current of 00 times or more (10 nA or more), and any of generated secondary electrons, reflected electrons, and transmitted electrons is detected, and its signal is detected. Discloses a method for automatically detecting a defect by comparing and inspecting an image formed from an image.

A method of inspecting or observing a circuit board having an insulator with an electron beam is disclosed in JP-A-59-15.
No. 5941 and “Electron and Ion Beam Handbook” (Nikkan Kogyo Shimbun), from pages 622 to 623,
A method for obtaining a stable image by irradiating a low-acceleration electron beam of 2 keV or less to reduce the influence of charging is disclosed. Further, JP-A-2-15546 discloses a method of irradiating ions from behind a semiconductor substrate, and JP-A-6-33.
No. 8280 discloses a method of irradiating the surface of a semiconductor substrate with light to cancel charge on an insulator.

On the other hand, with an electron beam having a large current and a low acceleration, it is difficult to obtain a high-resolution image due to the space charge effect.
Japanese Patent No. 58703 discloses a method of decelerating a high acceleration electron beam immediately before a sample and irradiating the sample with a substantially low acceleration electron beam.

As a method of acquiring an electron beam image at high speed, a method of continuously irradiating a semiconductor wafer on a sample stage with an electron beam while continuously moving the sample stage to acquire the image is disclosed in
160948 and JP-A-5-258703. In addition, as a secondary electron detection device used in a conventional SEM, a structure including a scintillator (a phosphor on which aluminum is deposited), a light guide, and a photomultiplier tube is used. The method has a poor frequency response because it detects light emission from a phosphor, and is not suitable for forming an electron beam image at high speed.
In order to solve this problem, Japanese Patent Application Laid-Open No. 5-258703 discloses a detecting device using a semiconductor detector as a detecting device for detecting a high-frequency secondary electron signal.

[0009]

In the conventional apparatus, the screen function of the circuit pattern inspection apparatus is not fully utilized in the conventional circuit pattern inspection apparatus.
Inspection of the appearance of the substrate is not always easy, and the usability is poor. Therefore, it has been difficult to find defects early in the inspection system and the inspection method, investigate the cause thereof, and improve the production yield of the semiconductor device by taking early measures.

The present invention has been made in view of the above points, and is intended to prevent defects in circuit patterns such as wafers, masks, and reticles, ie, thinning, chipping, defective formation, foreign matter, etc., such as linear or hole-shaped shapes. Inspection of circuit patterns that can improve the usability by improving the screen function of the inspection device of the circuit pattern to be inspected, improve the usability of the semiconductor device by early detection of the defect and investigation of its cause as a whole inspection system, and early measures It is an object to provide an apparatus, an inspection system, and an inspection method.

[0011]

According to the present invention, a feature of a defect is extracted from an image of a defect obtained by irradiation with a charged particle beam, a defect is classified based on the feature, and the defect is classified based on the classification. Is reacquired by the irradiation of the charged particle beam and displayed.

The circuit pattern inspection apparatus is configured to display an image signal transmitted from another apparatus.

Further, the circuit pattern inspection system includes an electron beam appearance inspection device having a monitor for displaying a defect on a map and an external appearance inspection device for storing an image of the defect. Are displayed simultaneously.

Further, the circuit pattern inspection system includes an inspection device for extracting a defect of the substrate at the end of a predetermined manufacturing process among a plurality of manufacturing processes for forming a circuit pattern on the substrate, and an inspection device using the inspection device. An observation device that observes the substrate or a part thereof based on the result, and an analysis device that is connected to the inspection device and analyzes an inspection result by the inspection device, wherein the analysis device specifies one of the manufacturing processes. The increase in the number of defects or foreign matter in the final step of the manufacturing process is calculated, and the correlation between the yield rate and the increase rate of the defect or foreign matter in the final step of the manufacturing process is calculated. The defect or the foreign substance is classified based on the history of the defect.

The inspection system for inspecting a substrate and extracting a defect at the end of a predetermined manufacturing process among a plurality of manufacturing processes for forming a circuit pattern on a substrate is provided. Based on an inspection result by the inspection device, a connection is made between an observation device for observing a defect present on the substrate or a part thereof, and transmission means for transmitting the inspection result is provided, and the inspection substrate executed by the inspection device is provided. And the coordinates of the substrate to be observed by the observation device or the coordinates of a part of the substrate are common or compatible.

The inspection system for inspecting a substrate and extracting a defect at the end of a predetermined manufacturing process among a plurality of manufacturing processes for forming a circuit pattern on the substrate is provided. Based on the inspection result by the inspection device, a connection is made with an observation device for observing a defect present on the substrate or a part thereof, and transmission means for sending the inspection result is provided. In addition, the position of the defect detected by the inspection device is detected based on a marking attached to a location where the position of the defect is known.

Further, the circuit pattern inspection system calculates a correlation between a yield rate generated in a final step of the manufacturing process and an increase rate of a defect or a foreign matter, and obtains the calculation result and the history of each processing apparatus in the manufacturing process. And a step of classifying the defect or the foreign matter based on the above.

The circuit pattern inspection method calculates a correlation between a yield rate and a defect or foreign matter increase rate generated in the final step of the manufacturing process, and calculates the calculation result and the history of each processing apparatus in the manufacturing process. And a step of classifying the defect or the foreign matter based on the above.

In this embodiment, the cell area means one unit of the area to be inspected.
It varies depending on the inspection requirements of the user, from the meaning of each chip on the wafer to the meaning of a specific process area in the chip. In this embodiment, each of the user's inspection request areas is collectively referred to as a cell area.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of an inspection apparatus, an inspection system, and an inspection method according to the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows the configuration of a circuit pattern inspection apparatus 1 according to an embodiment. The circuit pattern inspection apparatus 1 includes an inspection room 2 in which the inside of the room is evacuated, and a spare room (not shown in this embodiment) for transporting the substrate 9 to be inspected in the inspection room 2. The chamber is configured to be able to evacuate independently of the inspection room 2. The circuit pattern inspection apparatus 1 includes a control unit 6 and an image processing unit 5 in addition to the inspection room 2 and the spare room.

The inspection room 2 is roughly composed of an electron optical system 3, a secondary electron detection unit 7, a sample room 8, and an optical microscope unit 4. The electron optical system 3 includes an electron gun 10, an electron beam extraction electrode 11, a condenser lens 12, a blanking deflector 13, a scanning deflector 15, a diaphragm 14, an objective lens 16,
It comprises a reflector 17 and an E-cross B deflector 18.

The secondary electron detector 20 of the secondary electron detector 7 is disposed above the objective lens 16 in the inspection room 2. The output signal of the secondary electron detector 20 is amplified by a preamplifier 21 installed outside the inspection room 2 and is output by the AD converter 2
2 becomes digital data.

The sample chamber 8 includes a sample stage 30, an X stage 3,
1, a Y stage 32, a rotary stage 33, a position monitor length measuring device 34, and a substrate height measuring device 35 for inspection. The optical microscope unit 4 is provided near the electron optical system 3 in the inspection room 2 and at a position away from the electron optical system 3 so as not to affect each other. Is known. And X stage 31
Alternatively, the Y stage 32 includes the electron optical system 3 and the optical microscope unit 4
Reciprocate a known distance between the two. The optical microscope unit 4 includes a light source 40, an optical lens 41, and a CCD camera 42. The image processing unit 5 includes a first image storage unit 46, a second image storage unit 47, a calculation unit 48, and a defect determination unit 49. The captured electron beam image or optical image is displayed on the monitor 50.

An operation command and an operation condition of each section of the apparatus are input from the control section 6. In the control unit 6, conditions such as an acceleration voltage at the time of generation of an electron beam, an electron beam deflection width, a deflection speed, a signal capture timing of a secondary electron detection device, and a sample stage moving speed are arbitrarily or selected according to the purpose. It has been entered so that it can be set. The control unit 6 monitors the position and height deviations from the signals of the position monitor length measuring device 34 and the inspected substrate height measuring device 35 using the correction control circuit 43,
A correction signal is generated from the result, and the correction signal is sent to the objective lens power supply 45 and the scanning signal generator 44 so that the electron beam is always irradiated to a correct position.

In order to obtain an image of the substrate 9 to be inspected,
Irradiate the inspected substrate 9 with a narrowed primary electron beam 19,
Secondary electrons 51 are generated and detected in synchronization with the scanning of the primary electron beam 19 and the movement of the X stage 31 and the Y stage 32, thereby obtaining an image of the surface of the substrate 9 to be inspected.
As described in the subject of the present invention, in the automatic inspection of the present invention, a high inspection speed is essential. Therefore, normal SEM
As described above, an electron beam having an electron beam current of the order of pA is not scanned at a low speed, and a large number of scans and superposition of images are not performed. In addition, in order to suppress charging of the insulating material, it is necessary to perform electron beam scanning once or several times at high speed. Therefore, in the present embodiment, about 1 compared to the normal SEM.
An image is formed by scanning a high current electron beam of 100 times or more, for example, 100 nA only once. The scanning width is 100 μm, and one pixel is 0.1 μm square.
Each scan was performed in 1 μs.

The electron gun 10 uses a diffusion-supply type thermal field emission electron source. By using the electron gun 10, a stable electron beam current can be secured as compared with a conventional tungsten (W) filament electron source or a cold field emission electron source, for example. An image is obtained. Further, since the electron gun 10 can set a large electron beam current, a high-speed inspection as described later can be realized.

The primary electron beam 19 is extracted from the electron gun 10 by applying a voltage between the electron gun 10 and the extraction electrode 11. The primary electron beam 19 is accelerated by applying a high negative voltage to the electron gun 10. As a result, the primary electron beam 19 advances toward the sample stage 30 with energy corresponding to the potential, is converged by the condenser lens 12, is further narrowed down by the objective lens 16, and is then narrowed down by the X stage 31 and the Y stage on the sample stage 30. The substrate 9 to be inspected (a substrate having a fine circuit pattern such as a semiconductor wafer, a chip or a liquid crystal, a mask, etc.) mounted on the substrate 32 is irradiated. The blanking deflector 13 is connected to a scanning signal generator 44 for generating a scanning signal and a blanking signal.
Are connected to a lens power supply 45, respectively.

The substrate 9 to be inspected has a retarding power source 3
6 allows a negative voltage to be applied. By adjusting the voltage of the retarding power supply 36, the primary electron beam can be decelerated, and the irradiation energy of the electron beam to the substrate 9 to be inspected can be adjusted to an optimum value without changing the potential of the electron gun 10.

The secondary electrons 51 generated by irradiating the primary electron beam 19 on the substrate 9 to be inspected
Is accelerated by the negative voltage applied to Inspection substrate 9
An E-cross B deflector 18 is disposed above, and the accelerated secondary electrons 51 are deflected in a predetermined direction. E
Depending on the voltage applied to the cross B deflector 18 and the strength of the magnetic field,
The amount of deflection can be adjusted. Also, this electromagnetic field
It can be varied in conjunction with the negative voltage applied to the sample.

The secondary electrons 51 deflected by the E cross B deflector 18 collide with the reflector 17 under predetermined conditions. The reflector 17 has a conical shape integrally with a shield pipe of a deflector for an electron beam (hereinafter, referred to as a primary electron beam) for irradiating a sample. The secondary electrons 51 accelerated by the reflection plate 17
Collide with each other, a second secondary electron 52 having an energy of several volts to 50 eV is generated from the reflector 17.

The secondary electron detector 7 includes a secondary electron detector 20 inside the evacuated inspection room 2, and a preamplifier 21, an AD converter 22, a light conversion unit 23, It comprises a transmission means 24, an electric conversion means 25, a high voltage power supply 26, a preamplifier drive power supply 27, an AD converter drive power supply 28, and a reverse bias power supply 29.

As described above, the secondary electron detector 20 of the secondary electron detector 7 is connected to the objective lens 1 in the inspection room 2.
6 above. The secondary electron detector 20, preamplifier 21, AD converter 22, optical conversion means 23, preamplifier drive power supply 27, and AD converter drive power supply 28 are floated to a positive potential by the high voltage power supply 26. The second secondary electrons 52 generated by colliding with the reflection plate 17 are:
The suction electric field guides the secondary electron detector 20. The secondary electron detector 20 is configured to generate a secondary electron 51 generated while the primary electron beam 19 is irradiated on the substrate 9 to be inspected and then accelerated to collide with the reflection plate 17. 5
2 is configured to be detected in conjunction with the scanning timing of the primary electron beam 19.

The output signal of the secondary electron detector 20 is amplified by a preamplifier 21 installed outside the inspection room 2 and converted into digital data by an AD converter 22. AD converter 22
Is configured to convert the analog signal detected by the secondary electron detector 20 into a digital signal immediately after being amplified by the preamplifier 21 and to transmit the digital signal to the image processing unit 5. The detected analog signal can be digitized immediately after detection.

A substrate 9 to be inspected is mounted on the X stage 31 and the Y stage 32. When the inspection is performed, the X stage 31 and the Y stage 32 are stopped and the primary electron beam 19 is two-dimensionally scanned. X stage 3 when performing inspection
1. A method of scanning the primary electron beam 19 linearly in the X direction by moving the Y stage 32 continuously at a constant speed in the Y direction can be selected.

In the case of inspecting a specific relatively small area, the former stage is stationary and the inspection is carried out. In the case of inspecting a relatively large area, the stage is continuously moved at a constant speed for inspection. The method is effective. When the primary electron beam 19 needs to be blanked, the primary electron beam 19 is deflected by the blanking deflector 13 so that the electron beam can be controlled so as not to pass through the aperture 14.

In this embodiment, a length measuring device based on laser interference is used as the position monitor measuring device 34. The positions of the X stage 31 and the Y stage 32 can be monitored in real time and transferred to the control unit 6. Similarly, data such as the number of rotations of the motors of the X stage 31, the Y stage 32, and the rotary stage 33 are also transferred from the respective drivers to the control unit 6.
Based on these data, the region and position where the primary electron beam 19 is irradiated can be accurately grasped. The displacement of the irradiation position of the primary electron beam 19 is corrected by the correction control circuit 43 in real time as needed. In addition, an area irradiated with an electron beam can be stored for each substrate to be inspected.

As the substrate height measuring device 35 to be inspected, an optical measuring device other than the electron beam measuring method, for example, a laser interferometer or a reflected light measuring device for measuring a change in the position of reflected light is used. The height of the substrate 9 to be inspected mounted on the X stage 31 and the Y stage 32 is measured together with the actual operation, that is, measured in real time. In this embodiment, an elongated white light passing through the slit is irradiated onto the substrate 9 to be inspected through a transparent window, and the position of the reflected light is detected by a position detection monitor. The calculation method was used. The focal length of the objective lens 16 for narrowing down the primary electron beam 19 is dynamically corrected based on the measurement data of the substrate height measuring device 35 to be inspected, so that the primary electron beam 19 always focused on the non-inspection area. Can be irradiated. Further, it is also possible to configure such that the warpage and the height distortion of the substrate 9 to be inspected are measured in advance before the electron beam irradiation, and the correction conditions for each inspection area of the objective lens 16 are set based on the data. It is.

The image processing section 5 comprises a first image storage section 46, a second image storage section 47, an operation section 48, a defect determination section 49, and a monitor 50. An image signal of the substrate 9 to be inspected detected by the secondary electron detector 20 is transmitted to a preamplifier 21.
After being amplified by the A / D converter 22 and digitized by the A / D converter 22, it is converted to an optical signal by the optical conversion means 23, transmitted by the optical transmission means 24, and converted again into an electric signal by the electric conversion means 25, and then converted into a first image. It is stored in the storage unit 46 or the second image storage unit 47. The operation unit 48 aligns the stored image signal with the image signal of the other storage unit,
Signal level normalization and various image processing for removing noise signals are performed, and both image signals are compared and calculated. The defect judging unit 49 compares the absolute value of the difference image signal calculated by the operation unit 48 with a predetermined threshold value. If the difference image signal level is larger than the predetermined threshold value, the pixel is determined to be defective. The position is determined as a candidate, and the number of defects and the like are displayed on the monitor 50.

The overall configuration of the circuit pattern inspection apparatus 1 has been described above.
The configuration and operation of the detecting means will be described in more detail. When the primary electron beam 19 enters the solid, it enters the inside and excites electrons in the shell at each depth to lose energy. Also, there occurs a phenomenon in which the reflected electrons, in which the primary electron beam is scattered backward, travel toward the surface while also exciting the electrons in the solid. Through these multiple processes, the electrons in the shell cross the surface barrier from the solid surface to become secondary electrons and exit into the vacuum with energy of several V to 50 eV. As the angle between the primary electron beam and the solid surface becomes smaller, the ratio of the entrance distance of the primary electron beam to the distance from that position to the solid surface becomes smaller, and secondary electrons are more likely to be emitted from the surface. Therefore, the generation of secondary electrons depends on the angle between the primary electron beam and the solid surface, and the amount of secondary electrons generated is information indicating unevenness and material of the sample surface.

FIG. 2 shows a main configuration diagram of the electron optical system 3 for detecting the secondary electrons 51 and the secondary electron detector 7. The primary electron beam 19 is irradiated on the substrate 9 to be inspected, and generates secondary electrons 51 on the surface of the substrate 9 to be inspected. This secondary electron 51
Is accelerated by the negative high voltage applied to the substrate 9 to be inspected. The secondary electrons 51 are accelerated and converged and deflected by the objective lens 16 and the E-cross B deflector 18 and collide with the reflector 17. The reflector 17 has a tapered conical shape integrally with a shield pipe for preventing a voltage applied to the detector from affecting the primary electron beam. The secondary electron multiplying effect was provided as a configuration that emitted about five times as many secondary electrons as the number of irradiated electrons on average. The collision of the accelerated secondary electrons 51 generates second secondary electrons 52 having energy of several V to 50 eV from the reflection plate 17. This second secondary electron 52
Is attracted to the front surface of the secondary electron detector 20 by an attraction electric field generated by the secondary electron detector 20 and the attraction electrode 53 attached to the secondary electron detector 20.

The electromagnetic field of the E cross B deflector 18 can be variably set in conjunction with a high negative voltage applied to the substrate 9 to be inspected. With the above configuration, when the secondary electrons 51 generated on the surface of the substrate 9 to be inspected pass through the E-cross B deflector 18, 95% or more can be passed. Electrons 51 can be multiplied by about five times to generate second secondary electrons 52.

In this embodiment, a PIN semiconductor detector is used as the secondary electron detector 20. The PIN-type semiconductor detector has a faster response than a normal PN-type semiconductor detector, and can detect a high-frequency secondary electron signal having a sampling frequency of about 100 MHz by applying a reverse bias voltage from a reverse bias voltage power supply. it can. The secondary electron detector 20, the preamplifier 21, the AD converter 22, and the light conversion means 23, which are detection circuits, are floated to a positive voltage. Second secondary electrons 52 generated by the reflection plate 17
Is attracted to the secondary electron detector 20 by an attractive electric field, is incident on the secondary electron detector 20 in a high energy state, and loses a certain amount of energy in the surface layer. Is converted into an electric signal. The secondary electron detector 20 used in the present embodiment has a very high signal detection sensitivity, and considering the energy loss in the surface layer, the second secondary electrons 52 accelerated by the attraction electric field and incident are about 10%.
It becomes an electric signal amplified by 00 times. This electric signal is further amplified by the preamplifier 21, and the amplified signal (analog signal) is converted into a digital signal by the AD converter 22. The output of the AD converter 22 was transmitted in parallel by providing an optical conversion unit 23, an optical transmission unit 24, and an electric conversion unit 25 for each bit. According to this configuration, each transmission means only needs to have the same transmission speed as the clock frequency of the AD converter 22.

The signal converted into the optical digital signal by the optical conversion unit 23 is transmitted to the electric conversion unit 25 by the optical transmission unit 24, where it is converted from the optical digital signal into an electric signal again, and the image processing unit 5 Sent to The reason for transmitting the optical signal after converting it into an optical signal is that the components from the secondary electron detector 20 to the optical conversion means 23 are the high-voltage power supply 2.
This is because a signal of a high potential level can be converted into a signal of a ground level by the configuration of this embodiment.

In this embodiment, a light emitting element for converting an electric signal into an optical signal is used as the light converting means 23, an optical fiber cable for transmitting an optical signal is used as the light transmitting means 24, and an optical signal is used as the electric converting means 25. A light receiving element for converting into an electric signal was used. Since the optical fiber cable is formed of a highly insulating material, a signal at a high potential level can be easily converted to a signal at a ground potential level. Furthermore, since the digital signal is optically transmitted, there is no signal degradation at the time of optical transmission. As a result, it is possible to obtain an image less affected by noise as compared with the conventional technique of optically transmitting an analog signal.

In the above embodiment, the secondary electron detector 20 is applied with the reverse bias voltage by the reverse bias power supply 29. However, the secondary electron detector 20 may be configured not to apply the reverse bias voltage. In this embodiment, the secondary electron detector 20 is provided with PI
Although an N-type semiconductor detector is used, another type of semiconductor detector, for example, a Schottky semiconductor detector or an avalanche semiconductor detector may be used. If conditions such as responsiveness and sensitivity are satisfied, an MCP (micro channel plate) can be used as a detector.

Next, the operation in the case where the circuit pattern inspection apparatus 1 inspects a semiconductor wafer that has been subjected to pattern processing in the manufacturing process as the substrate 9 to be inspected will be described. First, although not shown in FIG.
The semiconductor wafer is loaded into the sample exchange chamber by the transfer means. Then, the substrate 9 to be inspected is mounted on a sample holder, held and fixed, and evacuated, and when the sample exchange chamber reaches a certain degree of vacuum, it is transferred to the inspection room 2 for inspection. In the inspection room 2, the sample stage 30, the X stage 31,
The sample holder is placed on the Y stage 32 and the rotary stage 33 together with the sample holder, and held and fixed.

The substrate 9 to be inspected is moved by moving the X stage 31 and the Y stage 32 in the X and Y directions on the basis of predetermined inspection conditions registered in advance.
Is located at a predetermined first coordinate under the optical pattern, an optical microscope image of a circuit pattern formed on the substrate 9 to be inspected is observed by the monitor 50, and a corresponding comparison of the same position stored in advance for position rotation correction is performed. The position correction value of the first coordinates is calculated by comparing the position correction value with the pattern image. Next, a certain distance from the first coordinates moves to the second coordinates where a circuit pattern equivalent to the first coordinates exists, and an optical microscope image is similarly observed,
Comparing with the circuit pattern image stored for the position rotation correction, the position correction value of the second coordinate and the rotation deviation amount with respect to the first coordinate are calculated. The rotation stage 33 rotates by the calculated rotation deviation amount, and corrects the rotation amount. In the present embodiment, the amount of rotation deviation is corrected by the rotation of the rotation stage 33. However, without using the rotation stage 33, a method of correcting the scanning deflection amount of the electron beam based on the calculated amount of rotation deviation can also be corrected. . In this optical microscope image observation, a circuit pattern that can be observed not only with an optical microscope image but also with an electron beam image is selected. Also, for future position correction, the first coordinate, the amount of displacement of the first circuit pattern by optical microscope image observation, the second coordinate,
The amount of displacement of the second circuit pattern by the optical microscope image observation is stored and sent to the control unit 6.

Further, the circuit pattern formed on the substrate 9 to be inspected is observed by using an image obtained by an optical microscope, and the position of the chip of the circuit pattern on the substrate 9 to be inspected, the distance between the chips, or the memory cell The repetition pitch or the like of the repetition pattern is measured in advance, and the measured value is input to the control unit 6. In addition, the chip to be inspected on the substrate to be inspected 9 and the region to be inspected in the chip are set from the image of the optical microscope, and input to the control unit 6 in the same manner as described above. The image of the optical microscope can be observed at a relatively low magnification, and when the surface of the substrate 9 to be inspected is covered with, for example, a silicon oxide film or the like, the image can be observed through the base. This is because the arrangement of the chips and the layout of the circuit patterns in the chips can be easily observed, and the setting of the inspection area can be facilitated.

When the preparatory work such as the predetermined correction work and the setting of the inspection area by the optical microscope section 4 is completed as described above, the substrate 9 to be inspected is moved by the movement of the X stage 31 and the Y stage 32. Moved down. When the substrate 9 to be inspected is placed below the electron optical system 3, the same operation as the correction operation and the setting of the inspection area performed by the optical microscope unit 4 is performed by the electron beam image. The acquisition of the electron beam image at this time is performed by the following method.

Based on the coordinate values stored and corrected in the alignment based on the optical microscope image, the optical microscope unit 4
In the same circuit pattern as that observed in
9 is two-dimensionally scanned in the X and Y directions by the scanning signal generator 44 and irradiated. By the two-dimensional scanning of the electron beam, the secondary electrons 51 generated from the observed region are detected by the configuration and operation of each unit for the secondary electron detection, and an electron beam image is obtained. Easy inspection position confirmation, position adjustment, and position adjustment have already been performed using the optical microscope image, and rotation correction has also been performed in advance, so the position resolution and position correction are higher in resolution and higher in magnification than optical images with higher precision. , Rotation correction can be performed.

When the primary electron beam 19 is irradiated on the sample 9 to be inspected, that portion is charged. In order to avoid the influence of the electrification at the time of inspection, the circuit pattern to be irradiated with the primary electron beam 19 in the pre-inspection preparation work such as the position rotation correction or the inspection area setting is a circuit pattern existing outside the inspection area in advance. Selection, or an equivalent circuit pattern in a chip other than the chip to be inspected can be automatically selected from the control unit 6. As a result, the influence of irradiating the primary electron beam 19 by the pre-inspection preparation work during the inspection does not affect the inspection image.

Next, an inspection is performed. The conditions of the primary electron beam 19 irradiating the substrate 9 to be inspected during the inspection were obtained by the following method. First, generally, the SN ratio in an electron beam image has a correlation with the square root of the number S of irradiated electrons per unit pixel of the electron beam irradiated on the sample. When comparing and inspecting images, the SN ratio of the electron beam image needs to be a value capable of detecting the signal amount of the normal portion and the defect portion, and the minimum SN ratio needs to be 10 or more, and preferably 50 or more. is necessary. As described above, the S / N ratio of the electron beam image is correlated with the square root of the number S of irradiated electrons per unit pixel of the electron beam irradiated on the sample. Or more electrons are required, and the SN ratio is 50
In order to obtain, at least 2500 or more electrons must be irradiated.

The purpose of applying this circuit pattern inspection method is to detect minute defects which cannot be detected by the optical pattern inspection method as described above, that is, to detect differences between images in minute pixels. I needed to recognize. In order to achieve this, in this embodiment, the pixel size is set to 0.1 μm square. Therefore, the required electron beam irradiation amount per unit area is 0.16 μC / cm 2 from the minimum required number of electrons per single pixel and the above pixel size.
And preferably 4 μC / cm 2. In order to obtain this amount of electron irradiation by a normal SEM electron beam current (about several pA to several hundred pA), for example, an electron beam current of 20 pA irradiates an area of 1 cm 2 square with 0.16 μC / cm 2 of electrons. Takes 8000 seconds, and 4 μC / cm2
It takes 200,000 seconds to irradiate the electrons. However, the inspection speed required for inspection of a circuit pattern, for example, inspection of a semiconductor wafer, is 600 s / cm 2 or less, preferably 300 s / cm 2 or less. Is extremely low. Therefore, satisfy these conditions,
In order to irradiate the sample with a necessary electron beam in a practical inspection time, the electron beam current must be at least 270 pA (1.6 μC / c
m2, 600 s / cm2) or more, preferably 13 nA (4
μC / cm2, 300 s / cm2) or more. Therefore, in the circuit pattern inspection method of the present embodiment,
An electron beam image is formed by one scan using a high current electron beam of 13 nA or more.

Forming an electron beam image by a single scan using an electron beam having a large current (at least 270 nA, preferably at least 13 nA), which is about 100 times or more that of a normal SEM, requires only an inspection speed. Not only is it necessary from the point of view, but it is necessary for inspecting a circuit pattern in which a base film or a surface pattern is formed of an insulating material for the following reasons.

When an electron beam image of a circuit pattern having an insulating material is acquired by a normal SEM, an electron beam image different from the actual shape is obtained due to the influence of charging, and the contrast often differs completely depending on the field magnification. This is because the weak electron beam current (several pA to several hundred pA) is repeatedly and locally scanned, or when the field magnification is changed, the electron dose exceeds the electron dose necessary for image formation for focus and astigmatism correction. This is because, by locally scanning the electron beam, the irradiation amount of the electron beam is intensively applied to a certain location, and the charging of that portion becomes uneven. As a result, the quality of an electron beam image of a pattern formed of an insulating material is completely different depending on the field of view, and such an image cannot be applied to an inspection for comparing electron beam images. Therefore, in order to inspect the circuit pattern having the insulating material similarly to the circuit pattern of the conductive material, the usual S
An electron beam image is formed by one scan using a large current electron beam which is about 100 times or more as large as EM.

That is, in the present embodiment, the amount of electron beam irradiation to the sample per unit area and per unit time is constant, and the electron dose required to form an image quality sufficient for performing the comparative inspection is obtained. In addition, an electron beam image is obtained by scanning the electron beam once at a scanning speed suitable for the practicality of the inspection method of a semiconductor wafer or the like. Then, as described above, an electron beam image of a circuit pattern having an insulating material was obtained by one scan using a high current electron beam that is about 100 times or more that of a normal SEM. It has been confirmed that the amount of charge and the contrast of the image are different depending on the constituent materials and structures of the various circuit patterns constituting, and that the same image contrast can be obtained between the same patterns of the same kind of material. In this embodiment, the scanning with the large current electron beam is performed only once. However, the scanning may be performed several times within a range in which the above-described operation is substantially realized.

Next, irradiation conditions which affect the contrast of an electron beam image will be described. The contrast of the electron beam image is formed by the amount of secondary electrons generated and detected by the electron beam irradiated on the sample. For example, the difference in the amount of secondary electrons generated due to a difference in material or the like results in a difference in brightness. .
FIG. 3 is a graph showing the effect of the electron beam irradiation condition on the contrast. FIG. 3A shows a case where the irradiation condition is appropriate, and FIG. 3B shows a case where the irradiation condition is inappropriate. I have. The vertical axis indicates the degree of charging, which has a large correlation with the brightness of the image, and the horizontal axis indicates the irradiation time of the electron beam. The solid line A indicates the case where photoresist was used for the sample, and the dotted line B indicates the case where wiring material was used for the sample.

As shown in FIG. 3A, in the time region C where the irradiation time is short, the brightness variation of each material is small, and in the time region D where the irradiation time is relatively long, the change in brightness due to the irradiation time is large. Finally, in the time region E where the irradiation time is long, the brightness variation due to the irradiation time is reduced again. According to FIG. 3B, when the irradiation conditions are not appropriate,
Even in the time region C where the irradiation time is short, the fluctuation in brightness with respect to the irradiation time is large, and it is difficult to obtain a stable image. Therefore, it is important to acquire an image under the irradiation conditions of FIG. 3A in order to acquire a stable and fast electron beam image.

The conditions for irradiating the sample with the electron beam are as follows.
The irradiation amount of the electron beam per unit area, the electron beam current value, the scanning speed of the electron beam, and the irradiation energy of the electron beam for irradiating the sample are exemplified. Therefore, it is necessary to determine the optimum values of these parameters for each circuit pattern shape and material.
For this purpose, it is necessary to freely adjust and control the irradiation energy of the electron beam irradiating the sample. Therefore, as described above, in this embodiment, a negative voltage for decelerating the primary electrons is applied to the substrate 9 to be inspected as the sample by the retarding power supply 36, and the voltage is adjusted to thereby adjust the primary electron beam 1.
The irradiation energy of No. 9 can be appropriately adjusted. As a result, when the acceleration voltage applied to the electron gun 10 is changed, a change in the axis of the primary electron beam 19 occurs, and various adjustments are required. In the present embodiment, the adjustment is performed without such adjustment. The effect of can be obtained.

Next, a method of scanning the primary electron beam 19 for forming an electron beam image for inspection will be described. In a normal SEM, an electron beam is two-dimensionally scanned while the stage is stationary, and an image of a certain area is formed. According to this method, when inspecting a wide area thoroughly, for each image acquisition area, in addition to the time for scanning the electron beam while standing still, the time for accelerating, decelerating, and setting the position of the stage as the moving time is added. It takes. Therefore, a long time is required for the entire inspection time. Therefore, in the present invention, while moving the stage continuously in one direction at a constant speed, the electron beam is scanned in one direction at a high speed in a direction orthogonal to or intersecting with the stage movement direction, so that the image of the inspection area is formed. The acquired inspection method was used. Accordingly, the electron beam acquisition time for one scanning width of the predetermined distance is only the time for the stage to move the predetermined distance.

FIG. 4 shows the primary electron beam 19 on the substrate 9 to be inspected.
FIG. 4 is a plan view showing a scanning direction of FIG. FIG. 4A shows an example of a direction in which the primary electron beam 19 scans when the Y stage 32 continuously moves in the Y direction at a constant speed by the above method. When the primary electron beam 19 is scanned by the scanning signal generator 44, an electron beam is irradiated to the substrate to be inspected 9 which is a sample in only one direction indicated by a solid line, and the electron beam is irradiated during the return of the electron beam indicated by a broken line. By blanking the inspection substrate 9 so that the primary electron beam 19 is not irradiated, the substrate 9 to be inspected is blanked.
The electron beam can be uniformly and spatially irradiated on the top. Blanking is performed by deflecting the primary electron beam 19 by the blanking deflector 13 so as not to pass through the aperture 14.

FIG. 4B shows a case where the primary electron beam 19 reciprocates at a constant speed as an example of another scanning direction. When the primary electron beam 19 is scanned at a constant speed from one end to the other end, the X stage 31 and the Y stage 32 are fed by one pitch, and the electron beam is scanned in the opposite direction to the original end at a constant speed. In the case of this method, the time for turning back the electron beam can be omitted.

The area or position where the electron beam is irradiated can be determined by transferring the measurement data of the position monitor length measuring device 34 installed on the X stage 31 and the Y stage 32 to the control unit 6 every moment. , Will be grasped in detail. In this embodiment, a laser interferometer is employed. Similarly, the fluctuation of the height of the region or position irradiated with the primary electron beam 19 is grasped in detail by transferring the measurement data of the substrate height measuring device 35 to the control unit 6 every moment. You.
Based on these data, the deviation of the irradiation position or the focal position of the electron beam is calculated, and the correction control circuit 43 automatically corrects these deviations. Therefore, a highly accurate and precise operation method of the electron beam is secured.

According to the scanning method of the primary electron beam 19 described above,
The entire surface of the substrate 9 to be inspected as a sample or an inspection region set in advance is irradiated with an electron beam, and secondary electrons 51 are generated by the above-described principle.
2 is detected. A high-quality image can be obtained by the configuration and operation of each unit described above. For example, by irradiating the reflector 17 with the above-described configuration and method, about 20
A double electron multiplication effect can be obtained, and the influence of aberration on the primary electron beam can be suppressed as compared with the conventional method.

The E-cross B deflector 18 has a similar configuration.
The reflected electron generated from the surface of the substrate 9 to be inspected is adjusted in the same manner as the secondary electron by adjusting the electromagnetic field applied to the substrate 17.
It is also possible to easily detect the second secondary electrons 52 obtained by irradiating. Further, by adjusting and controlling the electric field and the magnetic field of the E-cross B deflector 18 in conjunction with the negative high voltage applied to the sample, secondary electrons can be efficiently detected even under irradiation conditions different for each sample. In addition, the secondary electron detector 2
The method of detecting secondary electrons by using 0, digitizing the detected image signal immediately after detection, and transmitting the light, reduces the influence of noise generated in various conversions and transmissions, and provides an image signal with a high SN ratio. Data can be obtained.

In the process of forming an electron beam image from the detected signals, the image processing unit 5 outputs a detection signal every time corresponding to a desired pixel at the electron beam irradiation position designated by the control unit 6. The first image storage unit 46 or the second image storage unit 47 sequentially stores the brightness gradation value according to the level. By associating the electron beam irradiation position with the amount of secondary electrons associated with the detection time, an electron beam image of the sample circuit pattern is formed two-dimensionally. In this way, a high-quality electron beam image with high accuracy and a high SN ratio can be obtained.

When the image signal is transferred to the image processing unit 5,
The electron beam image of the first area is stored in the first image storage unit 46. The arithmetic unit 48 performs alignment of the stored image signal with the image signal of the other storage unit, normalization of the signal level, and various types of image processing for removing noise signals.
Subsequently, the electron beam image of the second area is stored in the second image storage unit 47.
And the same arithmetic processing is performed, and the image signals of the same circuit pattern and location of the electron beam image in the second area and the first electron beam image are compared and calculated. Defect judgment unit 4
Reference numeral 9 compares the absolute value of the difference image signal calculated by the calculation unit 48 with a predetermined threshold value, and when the difference image signal level is higher than the predetermined threshold value, determines the pixel as a defect candidate. Then, the position, the number of defects, and the like are displayed on the monitor 50. Then, thirdly, the electron beam image of the region is stored in the first image storage unit 46 and compared with the electron beam image of the second region previously stored in the second image storage unit 47 while performing the same operation. The calculation is performed and the defect is determined. Thereafter, by repeating this operation, image processing is performed on all inspection areas.

By obtaining a high-precision and high-quality electron beam image by the above-described inspection method and performing comparative inspection, a minute defect generated on a fine circuit pattern can be detected in an inspection time conforming to practicality. Can be. In addition, by acquiring an image using an electron beam, light is transmitted by the optical pattern inspection method, and the inspection cannot be performed. Defects can be inspected. Further, the inspection can be stably performed even when the material forming the circuit pattern is an insulator.

Next, an application example of inspecting a semiconductor wafer using the circuit pattern inspection apparatus 1 and the method will be described. FIG. 5 is a flowchart showing a semiconductor device manufacturing process. As shown in FIG. 5, the semiconductor device repeats a number of pattern forming steps from a wafer start / surface oxidation 61 to a step 2, a step 3, a step n, and a step n + 162. One pattern forming process is roughly as follows.
3, the steps of resist application 64, exposure to light 65, development 66, etching 67, removal of resist 68, and cleaning 69. In each of these steps, if the manufacturing conditions for processing are not optimized, the circuit pattern of the semiconductor device formed on the substrate will not be formed properly. Therefore, for example, by performing the automatic appearance inspections 60a and 60b after the steps of the development 66 and the resist removal 68, defects can be found early in the course of the process, and a decrease in the manufacturing yield can be prevented. .

FIG. 6 schematically shows a circuit pattern formed on a semiconductor wafer in a manufacturing process. FIG.
6A shows a normally processed circuit pattern, and FIG. 6B shows a pattern in which a processing failure has occurred. For example, when an abnormality occurs in the film forming process of FIG. 5, particles are generated and adhere to the surface of the semiconductor wafer, resulting in an isolated defect or the like in FIG. 6B. Further, if the conditions such as the focus of the exposure apparatus for exposure and the exposure time are not optimal at the time of exposure, there are places where the amount or intensity of light irradiated by the resist is too large or insufficient, and FIG.
(B) A short circuit, disconnection, and pattern narrowing in FIG. If there is a defect in the mask reticle at the time of exposure, a similar pattern shape abnormality occurs at the same location for each shot which is a unit of exposure. In addition, when the etching amount is not optimized and when a thin film or a particle is generated during the etching, a short circuit, a projection, an isolated defect, an opening defect, or the like occurs. At the time of cleaning, fine particles are generated due to re-adhesion of dirt, peeled film and foreign matter on the cleaning layer, and uneven thickness of the oxide film is easily generated on the surface due to the condition of drainage during drying.

Therefore, by applying the above-described circuit pattern inspection apparatus 1 shown in FIG. 1 to a semiconductor device manufacturing process, the occurrence of an abnormality can be detected with high accuracy and at an early stage. Can be taken,
The processing conditions can be optimized so that these defects do not occur. For example, if a circuit pattern inspection process is performed after the development process and a defect or disconnection of the photoresist pattern is detected, it is estimated that the exposure condition and the focus condition of the exposure apparatus in the exposure process are not optimal, Alternatively, these conditions are immediately improved by adjusting the exposure amount. In addition, by examining whether or not these defects are common among the shots from the defect distribution, the defects of the photomask and reticle used for pattern formation are estimated, and inspection and replacement of the photomask and reticle are performed. Will be implemented sooner. The same applies to other steps, and by applying the circuit pattern inspection method and apparatus of the present invention and performing the inspection step,
Various defects are detected, and the cause of the abnormality in each manufacturing process is estimated based on the content of the detected defects.

As described above, in the process of manufacturing a semiconductor device, by implementing the circuit pattern inspection apparatus or the inspection method according to the present invention, it is possible to detect fluctuations in various manufacturing conditions and occurrence of abnormalities within the inspection real time. In addition, it is possible to prevent a large amount of defects from occurring. In addition, by applying the circuit pattern inspection method and apparatus, it is possible to predict the non-defective product acquisition rate of the entire semiconductor device from the degree and frequency of occurrence of detected defects, and to improve the productivity of the semiconductor device. become.

Inspection of a semiconductor device is roughly divided into setting of inspection conditions, execution of inspection, confirmation and classification of extracted defects, and in this embodiment, these are called a recipe creation mode, an inspection mode, and a defect confirmation mode. In. Further, it has a utility mode for managing the obtained defect data file.

After setting the inspection conditions and executing the inspection, the extracted defects are confirmed and classified in the defect confirmation mode.

FIG. 7 is a flowchart showing an execution procedure in the defect confirmation mode. It is determined whether the SEM image acquired and displayed in step 300 and formed by irradiation only once can be automatically classified by the automatic classification mode in step 301. If NO, a manual SEM image is reacquired and displayed in step 302. If the mode is the classification mode (YES), classification of a defect (abnormal) is determined in step 303,
Classify. In this classification, the position (y-coordinate, x-coordinate), size, brightness, or shape of the displayed defect, or the value of another defect characteristic is larger or smaller than the value of a predetermined attribute. It depends on. This judgment,
Confirmation can be automatic or manual, ie, automatic or manual. When the classification can be performed according to the predetermined classification in this way (when the classification matches), in step 304, the SEM image is automatically reacquired and displayed. Next, an inspection result is output in step 305. If the classification is unmatched, or if the SEM image is manually reacquired and displayed, the inspection result is output at this stage. When the output of the inspection result is completed, the process proceeds to the next step 306 to unload the wafer.

With the above procedure, a specific defect can be extracted. Further, the SEM image acquired at the time of the inspection is stored in a file, and the operator can judge the defect again by displaying the filed SEM image again.

FIG. 8 shows a screen at the end of the automatic inspection in the inspection mode. At the top of the screen, an area 201 for displaying time, apparatus ID, board name to be inspected, operator name, etc.
A message area 202 for displaying various messages is arranged. In the lower part of the screen, an “inspection” button 203 for specifying an inspection mode for instructing execution of automatic inspection, a “defect confirmation” button 204 for specifying a defect confirmation mode for instructing defect confirmation, and a recipe for setting inspection conditions in advance. A “recipe creation” button 205 for designating a recipe creation mode for instructing creation, a “utility” button 206 for designating a utility mode for instructing the calling of auxiliary functions, and a “system end” button 207 for instructing system termination are arranged. I have.

On the left side of the center, a cassette display area 208 for displaying the position of the substrate mounted on the apparatus in the cassette.
However, on the right side of the center, a board display area 209 for displaying data of the corresponding board is arranged. When the operator selects an operation condition change in the option area 210 in the substrate display area 209, an operation condition change box 211 is displayed, and in the defect confirmation mode, the reacquisition of the SEM image of the defect is performed automatically or manually. Whether to execute or not to execute can be selected by clicking the mouse pointer.

In the case of automatic, an image of the automatically selected defective portion is automatically obtained. In the case of manual operation, the defect is checked manually after the inspection is completed. In the case of "none", the defect is not confirmed after the completion of the inspection, but is specified later when the inspection is performed manually.

FIG. 9 is a screen view at the end of the automatic inspection in the inspection mode as in FIG. A wafer map 212 is arranged on the center left side, and an inspection result display area 213 is arranged on the center right side. If the automatic operation is set under the optional operation conditions described with reference to FIG. 8, a preset time is waited on this screen, and the screen is switched to the defect confirmation screen. If manually,
"Defect confirmation" button 204 is clicked on with a mouse.

FIG. 10 is a screen view in the defect confirmation mode. On this screen, in the case of the automatic operation, defect information for the maximum number of defects is extracted from the defect data, and the defect information is displayed while sequentially taking images of the corresponding defects. The acquired images and information are output to a file as data for a higher system.

In FIG. 10, a “defect confirmation” button 20
4 is color-coded and distinguished from the others. An image display area 214 in which a reacquired image of a defect is displayed on the right side of the center.
Is arranged. A defect information display area 215 is arranged below the wafer map 212, and displays a defect ID, a defect cluster ID, a defect classification code, coordinates, a size, and the like. In FIG. 10, a mark of a color-coded defect on the wafer map 212 is clicked with a mouse, or the defect I
By inputting D, the SEM high magnification image of the corresponding portion is displayed in the right image display area 214.

The defect confirmation screen can be displayed by selecting either an image taken by an optical microscope or an SEM image. The “light microscope” button 216 for an optical microscope, the “SEM low magnification” button 217 for a low magnification of an SEM image, and the “SEM high magnification” button 21 for a high magnification.
Click 8. As a result, a defect image is simultaneously displayed on the side of the defect area information of the inspected wafer, so that it is easy to predict the cause of the defect.

The display of the wafer map 212 and the defect information display area 215 are linked, and the ID of the defect specified on the wafer map 212 is automatically set in the defect information display area 2.
15 is displayed. Conversely, if a defect ID is input in the defect information display area 215, a corresponding position on the wafer map 212 is marked and displayed. If the classification code of the corresponding defect is known, the defect code is input.

Instead of displaying all the extracted defects, it is also possible to display only the defects satisfying arbitrary conditions. Clicking a “display filter setting” button 219 can limit the display of defects. The condition is, for example, a defect area, a projection length, coordinates, a classification code, a range of coordinates in a chip, a classification code, and the like.

When the "Sort" button 220 is clicked, for example, the defects are sorted in the order of size or area, and the defect sort ID is set as a sub ID in that order.
Can be provided.

When the “cluster classification” button 221 is clicked, the defect is classified into clusters, the result is displayed, and the defect can be saved. In addition, the defect cluster I
D can be provided.

Further, by pressing each button in the option area, SE
The M image can be adjusted and the defect can be observed.
When the "irradiation condition" button 222 is clicked, the screen shown in FIG. 11 is displayed overlapping the screen shown in FIG. FIG. 11 is a screen diagram of the irradiation condition box. In the electron beam irradiation condition input area 223, an acceleration voltage and a beam current can be designated. The signal acquisition input area 224 includes a signal addition number,
Pixel dimensions can be specified. Here, the signal addition number is the number of times the wafer is scanned with an electron beam. Here, the pixel size is a size of a pixel of an image formed from a signal acquired by the secondary electron detector 20, that is, a length of one side. Pixels smaller than the electron beam diameter can also be selected. Therefore, even if the width of the circuit pattern is different on one chip, the size of the pixel can be designated according to the width of the circuit pattern, so that the inspection time can be made more efficient.

FIG. 12 is a screen view in the utility mode. "Utility" button 20 in FIG.
Clicking on 6 brings up the screen shown in FIG.

In the file menu display area 225, file functions such as electro-optical adjustment, load / unload, file management, image management, and time setting are provided as utility functions. For example, when a “file management” button 226 is clicked, a file management display area 227 is displayed. This file management display area 2
Reference numeral 27 indicates a type file and a process file, as well as an image file of a stored inspection result with a name. When the image of the inspection result is clicked and a “copy” button 228 is clicked, a copy display area 229 is displayed. In this copy display area 229,
The destination of the specified image file can be specified. Also,
When the “PC input” mark 230 is designated, an image file from an external PC can be downloaded.

According to the above embodiment, a specific defect can be extracted, and the defect can be reconfirmed based on the reacquisition and display of the filed SEM image at the discretion of the operator. . Since a defect image is simultaneously displayed on the side next to the information on the defect area of the inspected wafer, it is easy to predict the cause of the defect. As a result, the defect of the circuit pattern such as a wafer, a mask, and a reticle, that is, a line shape, a thin shape such as a hole shape, a chip, a formation defect, and a screen function of a circuit pattern inspection device for inspecting a foreign substance are improved. An easy-to-use circuit pattern inspection apparatus and inspection method can be obtained.

As described above, the chip inspection and the wafer sampling frequency inspection can be performed quickly while looking at the screen, so that a defect covering the entire product or a defect in a specific area can be quickly detected, and a change in process conditions can be achieved. Can be reliably detected and fed back to the process, and at the same time, can be fed back to the adjustment of the difference man-hour and the payout budget.

Further, inspection defects after the fine pattern formation step / resist development, the fine pattern formation step / etching, the hole pattern formation step, and the cleaning can be quickly detected by screen display.

Next, an example of a system for collecting and analyzing data detected by the inspection apparatus will be described below. 13 to 15 show examples of a circuit pattern inspection system for collecting and analyzing data.

FIG. 13 is an overall process diagram showing the steps of forming a semiconductor circuit pattern, the accompanying inspection steps, and the purpose of the inspection. In the figure, the steps flow from left to right. As shown in FIG. 7, to form a semiconductor pattern, “input” 71, “step 1” 72, “step 2”,..., “Step n”, and “completion (electric test)”
73 steps are assumed. In the “step 2” or the “step 3”, a case where a specific “apparatus 2” or “apparatus 3” is used instead of the “apparatus 1” is also assumed. "Inspection" between processes or every few processes
74 is performed. The “inspection” 74 is assumed to be “inspection step 1”, “inspection step 2”,..., “Inspection step n” corresponding to each step. As a result of these inspections, regarding the number of defects such as foreign particles and pattern defects, "whether foreign particles and defects in specific processes have not increased" 75, "correlation between yield (electric test) and defects (control level setting)""76" is executed, and "Search by processing device history (is there any abnormality in the group passing through the specific device?") 77 is executed.

FIG. 14 is a configuration diagram showing an entire system including various measuring devices, a data collection / analysis system, and a data transmission / storage device. The overall system 80 includes a measuring device group 81, a data collection and analysis system 82, a bus 83 as a communication line, a QC data collection system 84, a tester 85,
It comprises a server 86 and a personal computer 87 in the office.

The measuring device group 81 includes, for example, a review SEM 91, a review station 92, a foreign material inspection device 93, a semiconductor wafer appearance inspection device 94 using light or laser light, a length measurement SEM 95, an alignment accuracy measurement device 96, a film It comprises a thickness measuring device 97 and others.

[0099] Foreign matter / appearance / classification results 98 are output from the review SEM 91, review station 92, foreign matter inspection device 93 and appearance inspection device 94, and are input to the data collection / analysis system 82 via the bus 83. Measurement S
Other QC data 99 is output from the EM 95, the alignment accuracy measuring device 96, and the film thickness measuring device 97, and is input to the QC data collecting system 84 via the bus 83 together with the tester result from the tester 85.

The data collection / analysis system 82 is composed of a computer 101 and an accompanying foreign matter / appearance storage file 1
02 and an image file 103. The output data is stored in the server 86. The server will store data for a certain period. The QC data collection system 84 comprises a computer 104 and an FBM data file 105 for FBM (fail bit map) analysis and a QC data file 106 for electrical tests.

The server 86 stores “yield electric test category processing apparatus history size film thickness foreign material (mirror surface) alignment accuracy withstand voltage foreign material / appearance” 107 as data. The office personal computer 87 takes in data from the server 86 and is used for various searches, analysis, and report creation processing.

FIG. 15 is a block diagram of a system showing a part of FIG. 14 in detail. If there is no inspection device in the semiconductor device manufacturing process, the tester 85 is used when the semiconductor device is completed.
To inspect the electrical characteristics. If there is any abnormality, the high-resolution SE of the system of “Need to cut out observation unit / analysis unit” 111
The M, AES analysis, and TEM observation devices will be used to investigate the cause of the abnormality. In this case, an abnormality can be found only when the semiconductor device is completed, and then the cause is checked. Therefore, it takes a long time from one month to two months to investigate the cause and start countermeasures. In contrast, in the present embodiment,
Appropriate inspections are performed between each process, abnormalities are found early in each process, and countermeasures are taken. This has a great effect on improving the production yield of semiconductor devices.

The foreign matter / appearance inspection result 98a is obtained by measuring conditions,
The number of foreign substances / defects, size, coordinates, and the like are input to the data collection and analysis system 82. From the QC data collection system 84, the yield and FBM coordinates are
Is input to

Here, for example, the position of the foreign matter or defect in the foreign matter / appearance / classification result 98 detected by the appearance inspection apparatus 94 shown in FIG.
When searching for the foreign matter or defect with EM91, SIM / SE
This is very useful when processing the FIB cross section for observation with the M observation device 91a. If the common coordinates or the coordinates are compatible between the two devices, the position of the foreign matter or the defect can be easily searched. In addition, it is also useful to search for a position when review SEM 91 or FIB cross-section processing is performed by attaching a marking indicating the position of a foreign substance or defect by the appearance inspection device 94 to a location such as a neighborhood where the position of the foreign substance or defect is known. .

As a result of using the review SEM 91, if it is determined that the observation section / analysis section needs to be cut out 111, the detected high-resolution SEM, AES analysis, and TEM observation results together with the foreign matter / defect coordinates and the image / classification results The analysis result is input to the data collection / analysis system 82, and the collected / analyzed data is fed back to be used for the determination of the above-described observation unit / analysis unit extraction.

FIG. 16 is a block diagram of a system similar to FIG. 14 showing another example. Appearance inspection device 9 shown in FIG.
4 is divided into an external visual inspection device 94a such as an optical inspection device and an SEM visual inspection device 94b used in the present invention. With this configuration, the information from the external appearance inspection device 94a and the information from the upper system are stored in the SE.
Both the external information obtained by inputting to the M-type appearance inspection device 94b and the result of the SEM-type appearance inspection device 94b can be compared on the screen. As a result, defect information that was not found only with the external appearance inspection device 94a such as an optical inspection device or defect information that was not obvious only with the SEM type appearance inspection device 94b was displayed on the screen or obtained from both. By superimposing and displaying the obtained defect information on the screen, a more accurate circuit pattern inspection can be expected.
In such a case, color-coding each information,
Alternatively, if the defect information obtained by which device can be easily visually recognized by displaying the image in a different shape, the identification can be further facilitated.

Also in this example, the external appearance inspection device 94a such as an optical inspection device or the SE used in the present invention is used.
The coordinates of the M-type visual inspection device 94b and the review SEM9
If the coordinates of the coordinate No. 1 are shared or the coordinate conversion is made easy, the position of a defect such as a foreign substance or a pattern defect in the review SEM 91 can be easily searched. Also, an external appearance inspection device 94a such as an optical inspection device or an SEM type appearance inspection device 94b used in the present invention.
In the review SEM, marking is performed so that the position of a defect such as a foreign substance or a pattern defect can be identified.
At 91, the position of a defect such as a foreign substance or a pattern defect can be easily searched.

FIG. 17 is a screen diagram of an inspection result displayed on the monitor 50 of the inspection apparatus 1 for circuit patterns. Defect 1
08 and the number of defective chips are displayed. By taking in the defect information of the external device, it is possible to display the wafer map 109 with a change in color or shape.

According to the present embodiment described above, by applying the inspection apparatus according to the present invention to a product process of a semiconductor device, defects which cannot be detected by the prior art, that is, abnormalities in the product device, conditions, and the like can be obtained. By referring to the screen formed by the screen forming and displaying means, it is possible to find the image early and with high accuracy. Since the analysis can be performed by using an appropriate device in the host system, an abnormality countermeasure process can be immediately performed in the semiconductor device manufacturing process, and as a result, the defect rate of the semiconductor device can be reduced and the productivity can be increased. Further, since the occurrence of an abnormality can be detected quickly, it is possible to prevent a large number of defects from occurring. Further, as a result, the occurrence of defects can be reduced, so that the reliability of the semiconductor device and the like can be improved. Therefore, the development efficiency of new products etc. is improved,
In addition, manufacturing costs can be reduced. Further, it is possible to greatly reduce the waiting time of the product until the investigation of the cause of the defect in the manufacturing process, and to significantly reduce the time for detecting the occurrence of the defect.

Further, by applying the inspection apparatus according to the present invention to a process for manufacturing a semiconductor device such as a semiconductor element, not only can defects be detected with high sensitivity, but also an inspection application step is set, and the wafer in the step is used. Setting efficiency when setting inspection conditions can be improved. As a result, the waiting time of the in-process wafer in the inspection process is eliminated, and the occurrence of a serious abnormality can be detected at an early stage. Then, an abnormality countermeasure can be taken at an early stage in the defect generation step, and the processing conditions can be optimized so that these defects do not occur.

For example, if a defect or disconnection of the photoresist pattern is detected in the circuit pattern inspection step after the development step, a situation may occur in which the exposure condition and the focus condition of the exposure apparatus in the exposure step before the development step are not optimal. Since it is estimated, measures such as adjustment of the focus condition or the exposure amount can be taken promptly.

Further, by examining from the defect distribution whether or not the detected defect occurs in common among the shots, the defect of the photomask and reticle used for pattern formation can be estimated. Inspection and replacement of the reticle can be performed quickly.

As described above, the method and the apparatus for inspecting a circuit pattern according to the present invention are applied to the manufacturing process of a substrate such as a semiconductor device, and the inspection process is performed in the course of the manufacturing process to detect various defects. Thus, the cause of the abnormality in each manufacturing process can be quickly estimated based on the content of the detected defect.

As an application example of the above inspection, the inspection can be applied to a wafer manufacturing line by the following method.

The frequency with which wafers of a plurality of products and processes requiring inspection are inspected is, for example, determined as follows.
In the development of a semiconductor product, it is considered that optimization is performed while changing various process conditions. Therefore, it is desirable to inspect each time the conditions are changed.

On the other hand, when the process conditions are almost fixed, it is desirable to inspect about several wafers per week for products and processes that need to be inspected, and to inspect when the process conditions are changed.

Further, in a production line where the process is stable, it is possible to grasp the variation and the level of the production process by performing an inspection of “one sheet / week, product, process”. However, other wafer sampling inspections may be performed according to the purpose.

As described above, in the semiconductor device manufacturing process, by performing the circuit pattern inspection apparatus according to the present invention in-line, it is possible to detect fluctuations in various manufacturing conditions and occurrence of abnormalities in the inspection real time. In addition, it is possible to prevent a large amount of defects from occurring. Also, by applying the circuit pattern inspection device according to the present invention,
It is possible to efficiently and accurately determine the inspection condition of the inspection target wafer in a short time. As a result, a more accurate inspection can be applied, so that occurrence of a defect can be detected with high sensitivity. Further, the time for determining the inspection conditions can be greatly reduced, so that the waiting time of the product and the occupation time of the operator can be reduced. Since the defect can be detected earlier than the conventional inspection method and inspection apparatus, the productivity of the semiconductor device can be improved.

Further, in the circuit pattern inspection apparatus according to the present invention, the inspection results can be matched and the correlation evaluation can be performed as necessary, and the data search can be performed from an individual terminal (a personal computer or the like). Can be. Further, when a defect is detected, information on the location of occurrence can be searched, various analyzes can be performed by the failure analysis device, and the analysis results can be further stored as analysis results.

In addition, it is possible to connect an inspection device and an analysis device other than those described in this embodiment to the data collection / analysis system, and it is assumed that the inspection device described in this embodiment is also connected. ing.

As described above, with regard to the configuration of the typical apparatus of the present invention and the method of inspecting a circuit pattern, a method of irradiating an electron beam to acquire an electron beam image at a high speed and perform a comparative inspection, a specific inspection flow and each part Of operation, a flow for determining inspection conditions, an operation screen and an operation method for inspection and inspection condition setting, a hierarchy of inspection condition setting screens, a semiconductor device and other circuit patterns by performing the circuit pattern inspection of the present invention. Although some embodiments such as a method of improving the productivity of the manufacturing process of the substrate having have been described,
Without departing from the scope of the present invention, an inspection method and an inspection apparatus combining a plurality of features recited in the claims are also possible.

[0122]

As described above, according to the present invention, defects in circuit patterns such as wafers, masks, reticles, etc., that is, thin lines, holes, etc., chipping, defective formation, foreign matter, etc., are eliminated. Inspection of circuit patterns that can improve the usability by improving the screen function of the inspection device of the circuit pattern to be inspected, improve the usability of the semiconductor device by early detection of the defect and investigation of its cause as a whole inspection system, and early measures An apparatus, an inspection system, and an inspection method can be provided.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a circuit pattern inspection apparatus.

FIG. 2 is a main configuration diagram of an electron optical system and a secondary electron detection unit.

FIG. 3 is a graph showing the effect of electron beam irradiation conditions on contrast.

FIG. 4 is a plan view showing a scanning direction of a primary electron beam on a substrate to be inspected.

FIG. 5 is a flowchart showing a manufacturing process of the semiconductor device.

FIG. 6 is a schematic diagram of a circuit pattern formed on a semiconductor wafer in a manufacturing process.

FIG. 7 is a flowchart showing an execution procedure in a defect confirmation mode.

FIG. 8 is a screen view at the end of an automatic inspection in the inspection mode.

FIG. 9 is a screen view at the end of an automatic inspection in the inspection mode.

FIG. 10 is a screen view in a defect confirmation mode.

FIG. 11 is a screen view of an irradiation condition box.

FIG. 12 is a screen view in a utility mode.

FIG. 13 is an overall process diagram showing an inspection process and the purpose of the inspection.

FIG. 14 is a configuration diagram showing an entire system including various measurement devices, a data collection / analysis system, and a data transmission / storage device.

FIG. 15 is a configuration diagram of a system showing a part of the details of FIG. 14;

FIG. 16 is a configuration diagram of a system similar to FIG. 14 showing another example.

FIG. 17 is a screen view of an inspection result displayed on a monitor of a circuit pattern inspection apparatus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Circuit pattern inspection apparatus, 2 ... Inspection room, 3 ... Electronic optical system, 4 ... Optical microscope unit, 5 ... Image processing unit, 6 ... Control unit, 7 ... Secondary electron detection unit, 8 ... Sample room, 9 ... substrate to be inspected, 10 ... electron gun, 15 ... scanning deflector, 18 ... E-cross B deflector, 19 ... primary electron beam, 20 ... secondary electron detector,
30 ... sample stage, 31 ... X stage, 32 ... Y stage,
33: rotating stage, 36: retarding power supply, 46
... First image storage unit, 47 ... Second image storage unit, 48 ... Calculation unit, 49 ... Defect determination unit, 50 ... Monitor, 74 ... Inspection, 8
0: Overall system, 81: Measuring device group, 82: Data collection / analysis system, 83: Bus, 84: QC data collection system, 85: Tester, 86: Server, 87: Office PC, 91: Review SEM, 92 ... Review station, 93: Foreign material inspection device, 94: Appearance inspection device,
95: side length SEM, 96: alignment accuracy measuring device, 97: film thickness measuring device, 101: computer, 104: computer, 108: defect, 109: wafer map, 204:
"Defect confirmation" button, 211 ... operation condition change box,
212: wafer map, 214: image display area, 215
... Defect information display area.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G01N 23/225 G01R 1/06 F G01R 1/06 31/02 31/02 G01B 11/24 A 31/302 G01R 31/28 L G06T 7/00 G06F 15/62 405A (72) Inventor Kazuhisa Machida 1-280 Higashi-Koikekubo, Kokubunji-shi, Tokyo Inside the Hitachi, Ltd.Design Research Laboratory Co., Ltd. 280-chome, Hitachi, Ltd.Central Research Laboratory Co., Ltd. (72) Inventor Hiroshi Morioka 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In-house Semiconductor Business Division, Hitachi, Ltd. 882 Ma, Hitachinaka City, Hitachi, Ltd.Measurement Instruments Division (72) Inventor Takashi Hiroi Totsuka-ku, Yokohama-shi, Kanagawa 292 Yoshidacho Inside Hitachi, Ltd. Production Engineering Laboratory

Claims (13)

[Claims] An irradiation device configured to irradiate a surface of a substrate on which a circuit pattern is formed with light, a laser beam, or a charged particle beam, and detecting a signal generated from the substrate by the irradiation. A detector, a memory for storing an imaged signal obtained by the detector, a comparison device for comparing the signal stored in the memory with a signal formed from a corresponding comparison pattern in another area, In a circuit pattern inspection apparatus, comprising: a monitor that displays a defect on the circuit pattern from a result of the comparison apparatus; wherein the memory is configured such that the irradiation of the charged particle beam is performed for one region of the surface of the substrate. A defect classification device for storing a signal corresponding to the image which is the number of times, extracting a feature of the defect on the circuit pattern included in the signal, and classifying the defect; Based on the classification result in the classification device, an image of the defect on the circuit pattern obtained from the result in the comparison device, or an image obtained by re-irradiating the defect with the charged particle beam is displayed. A circuit pattern inspection apparatus, characterized in that: 2. A surface of a substrate on which a circuit pattern is formed is irradiated with light, a laser beam, or a charged particle beam, and a signal generated from the substrate due to the irradiation is detected. A method for inspecting a circuit pattern, comprising: storing a signal; comparing the stored signal with a signal formed from a corresponding comparison pattern in another region; and displaying a defect on the circuit pattern from the comparison result. Forming an image in which the irradiation of the line is performed once for one region of the surface of the substrate, extracting a feature of the defect on the circuit pattern based on the image, classifying the defect from the feature, Based on the classification, an image of a defect on the circuit pattern obtained from the result of the comparison device, or an image of the defect is reacquired by irradiation with the charged particle beam and displayed. Inspection method of the circuit pattern. 3. The circuit pattern according to claim 2, wherein the defect classification is performed by comparing defect characteristics including position, size, brightness, and shape with predetermined attributes. Inspection methods. 4. The method according to claim 2, wherein the step of reacquiring the image of the defect by irradiating the charged particle beam determines whether or not the defect can be classified by an automatic classification mode, and is executed when it is determined that the classification is possible. Inspection method of circuit pattern, characterized in that: 5. A circuit pattern comprising: an electron optical device for irradiating a plurality of regions on a surface of a substrate on which a circuit pattern is formed with an electron beam; and a monitor for detecting and displaying a defect in the circuit pattern by the irradiation. In the inspection apparatus, the monitor displays an image signal transmitted from another apparatus, and the circuit pattern inspection apparatus. 6. A means for irradiating a plurality of regions on a surface of a substrate formed of a plurality of lenses on which a circuit pattern is formed with an electron beam, and detecting a signal secondary generated from the plurality of regions by the irradiation. A secondary signal detecting unit, an electron beam image forming unit that forms an electron beam image of the plurality of regions from the detected signals, an image storage unit that stores the electron beam image, and a display device that displays the electron beam image. In a circuit pattern inspection system comprising an electron beam appearance inspection device provided and an external appearance inspection device provided with a defect image storage unit storing a defect image of the circuit pattern, the display device of the electron beam appearance inspection device includes: The map display screen and the electron beam image display screen of the substrate are stored in the defect image storage unit of the external appearance inspection device relating to the electron beam image stored in the image storage unit. Recessed inspection system of a circuit pattern and displaying the images simultaneously. 7. A defect display according to claim 6, wherein the defect is displayed by an image stored in an image storage means for recording the electron beam image.
A circuit pattern inspection system, wherein a defect display by an image stored in the defect image storage means is identified and displayed by color or the like. 8. A circuit pattern inspection system according to claim 6, further comprising a classification file for classifying and storing both defects displayed on the screen. 9. At the end of a predetermined manufacturing process among a plurality of manufacturing processes of a substrate on which a circuit pattern is formed, the substrate is inspected to extract a defect or a foreign substance, and based on a result of the inspection, Observing the defect or foreign matter present on the inspected substrate or a part thereof, determining a defect or an increase in foreign matter in a specific step of the manufacturing process, and a yield generated in a final step of the manufacturing process. Rate and the defect, or a correlation between the increase rate of foreign matter, the defect, based on the calculation result and the history of each processing apparatus in the manufacturing process,
Alternatively, a method for inspecting a circuit pattern, comprising a step of classifying foreign matter. 10. A method of inspecting a substrate at the end of a predetermined manufacturing process among a plurality of manufacturing processes of a substrate on which a circuit pattern is formed, extracting a defect or a foreign substance, and based on a result of the inspection, Observing the defect or foreign matter present on the inspected substrate or a part thereof, determining a defect or an increase in foreign matter in a specific step of the manufacturing process, and a yield generated in a final step of the manufacturing process. Calculating the correlation between the rate and the rate of increase of the defect or foreign matter, and classifying the defect or foreign matter based on the calculation result and the history of each processing apparatus in the manufacturing process. Circuit pattern inspection system. 11. An irradiation device comprising a plurality of lenses for irradiating a substrate with light, laser light, or a charged particle beam, a detector for detecting a signal generated from the substrate by the irradiation, and a detector for detecting a signal generated by the detector. A defect extracting device for extracting a defect of the substrate based on the signal obtained from the signal, and performing inspection of the substrate at the end of a predetermined manufacturing process among a plurality of manufacturing processes for forming a circuit pattern on the substrate. An irradiation device configured to irradiate the substrate with a charged particle beam, including a plurality of electron lenses, a detector that detects a signal generated from the substrate by the irradiation, and a detector that detects a signal generated by the substrate. An image display device that displays an image of the substrate based on the signal that has been provided, and at least the substrate or a part thereof is observed based on an inspection result by the inspection device. One observation device, and at least one analysis device connected to the inspection device and analyzing an inspection result by the inspection device, wherein the analysis device has a defect or a foreign matter in a specific process of the manufacturing process. Is determined, and the correlation between the yield rate generated in the final step of the manufacturing process and the increase rate of the defect or foreign matter is calculated, and based on the calculation result and the history of each processing apparatus in the manufacturing process. And inspecting the circuit pattern for the defect or the foreign matter. 12. An irradiation apparatus comprising a plurality of lenses for irradiating a substrate with light, laser light, or a charged particle beam, a detector for detecting a signal generated from the substrate by the irradiation, and a detector for detecting a signal generated by the detector. A defect extracting device for extracting a defect of the substrate based on the signal obtained from the signal, and performing inspection of the substrate at the end of a predetermined manufacturing process among a plurality of manufacturing processes for forming a circuit pattern on the substrate. An irradiation device for irradiating the substrate with a charged particle beam, a detector for detecting a signal generated from the substrate by the irradiation, and a signal detected by the detector An image display device that displays an image of the substrate based on the observation device, based on the inspection result by the inspection device, to observe the defect present in the substrate or a part thereof, Along with connecting between, comprises a transmission means for sending the inspection result, the coordinates of the substrate of the inspection performed by the inspection device, the coordinates of the substrate or a part thereof of the observation performed by the observation device and Is a circuit pattern inspection system which is common or has compatibility. 13. An irradiation device comprising a plurality of lenses for irradiating a substrate with light, laser light, or a charged particle beam, a detector for detecting a signal generated from the substrate by the irradiation, and a detector for detecting a signal generated by the detector. A defect extracting device for extracting a defect of the substrate based on the signal obtained from the signal, and performing inspection of the substrate at the end of a predetermined manufacturing process among a plurality of manufacturing processes for forming a circuit pattern on the substrate. An irradiation device for irradiating the substrate with a charged particle beam, a detector for detecting a signal generated from the substrate by the irradiation, and a signal detected by the detector An image display device that displays an image of the substrate based on the observation device, based on the inspection result by the inspection device, to observe the defect present in the substrate or a part thereof, And a transmission unit for transmitting the inspection result, and attaching a position of the defect detected by the inspection device to a position where the position of the defect is known at the time of observation performed by the observation device. A circuit pattern inspection system, wherein detection is performed based on a given marking.