JP2000228087A - Dual port ram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a dual port random access memory(RAM) using a symmetrical layout in which performance is improved to increase recording density. SOLUTION: A dual port random access memory comprises four NMOS transistors NM11-14 and four PMOS transistors PM11-14. The NMOS transistors NM11-14 and the PMOS transistors PM11-14 both are used as a pass gate. In more detail, two NMOS transistors are used as a pass gate of one group of bit line, two PMOS transistors are used as a pass gate of another group of bit line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a memory device, and more particularly, to a dual-port static random access memory (SRAM).

[0002]

2. Description of the Related Art As the functions of microprocessors have become more general and complex, larger programs and calculations can be executed by the microprocessors. Therefore, a large-capacity memory is urgently required. Satisfying memory capacity requirements and producing memories at low cost is a major topic for semiconductor manufacturers.

Depending on the functions used, the memory can be a read only memory (ROM) or a random access memory (R).
AM). A read-only memory performs only read operations, while a random access memory can perform both write and read operations. In terms of data access, read-only memory is
Further, a mask read only memory, a programmable read only memory (PROM), an erasable programmable read only memory (EPROM), and an electrically erasable programmable read only memory (EEPRO)
M). On the other hand, random access memories can be further classified into static random access memories and dynamic random access memories (DRAMs).

An SRAM is a memory device having the highest operation speed among semiconductor memory devices, and therefore has a wide range of applications. For example, the SRAM can be applied as a cache memory for data access of a computer. A typical SRAM cell consists of four transistors and two resistors, or six transistors. Compared with other memory devices, the degree of integration is poor.

Another dual port SRAM is:
It was developed as having a more powerful data input / output (I / O) function than the single-port SRAM described above. A dual-port SRAM generally includes eight transistors, including six N-type metal oxide semiconductors (NMOS) NM1 to NM6 and two P-type MOSs (PMOSs).
MOS) PM1, PM2, which is shown in FIG. In addition, two word lines WL1, W12 and four bit lines BL1, -BL1, BL2, -BL2 are required for the write and read operations. 6 NMOS and P
The MOS layout is very asymmetric and affects the performance of the dual-port SRAM.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to provide a dual-port SRAM using a symmetrical layout for improving performance in order to increase recording density.

[0007]

SUMMARY OF THE INVENTION To achieve the above objects and advantages, a dual port SRAM is provided. A dual port SRAM has two inverters and two NMs
It includes an OS and two PMOSs. The inverter includes a first inverter having a first input terminal and a first output terminal, and a second inverter having a second input terminal and a second output terminal. The second input terminal is connected to a first output terminal, while the first input terminal is connected to a second output terminal. The first N-type MOS transistor has a gate connected to a first word line, a source / drain region connected to a first bit line, and another source / drain connected to a first output terminal. Including the region. Second N-type M
The OS transistor includes a gate connected to a first word line, a source / drain region connected to a second bit line, and another source / drain region connected to a first input terminal. The first P-type MOS transistor is connected to the second
, A source / drain region connected to the third bit line, and another source / drain region connected to the second input terminal. The second P-type MOS transistor has a gate connected to a second word line, a source / drain region connected to a fourth bit line, and another source / drain connected to a second output terminal. Including the region.

[0008] Further, the present invention provides another dual-port static random access memory. The dual-port static random access memory has four P-type MOS transistors and four N-type MOs.
S transistor. The first N-type MOS transistor has a gate connected to a first word line, a source / drain region connected to a first bit line, and another source / drain connected to a first node. Including the region. The second N-type MOS transistor has a gate connected to the first word line, a source / drain region connected to the second bit line, and another source / drain region connected to the second node including. The third N-type MOS transistor includes a gate connected to the second node, a source / drain region connected to the ground potential, and another source / drain region connected to the first node. The fourth N-type MOS transistor includes a gate connected to the first node, a source / drain region connected to the ground potential, and another source / drain region connected to the second node. The first P-type MOS transistor has a gate connected to the second word line, a source / drain region connected to the third bit line, and another source / drain connected to the first node. Including the region. Second P-type MO
The S transistor includes a gate connected to the second word line, a source / drain region connected to the fourth bit line, and another source / drain region connected to the second node. The third P-type MOS transistor has a gate connected to the second node and a source /
A drain region and another source / drain region connected to the first node. The fourth P-type MOS transistor includes a gate connected to a first node, a source / drain region connected to a power supply, and another source / drain region connected to a second node.

The foregoing general description and the following detailed description are both representative and explanatory only and are not restrictive of the invention, as set forth in the following claims.

[0010]

FIG. 1 is a circuit diagram of a conventional dual-port SRAM. FIG. 2 is a circuit diagram of a dual port SRAM according to one embodiment of the present invention. FIG. 3 is a circuit diagram of a dual port SRAM according to another embodiment of the present invention.

Referring to FIG. 2, a dual port SRAM
Are four NMOS transistors NM11 to NM14
And four PMOS transistors PM11 to PM14. Two NMOSs and two PMOSs are used as pass gates in a dual-port SRAM in the present invention. In this example, the NMOS transistors NM13, NM
14, and the PMOS transistors PM13 and PM14
Used as a pass gate.

As shown in FIG.
M13 has a gate connected to the word line WL11,
There is one source / drain region connected to bit line BL11 and another source / drain region connected to node N11. The NMOS (NM14) has a gate connected to the word line WL11 and another bit line -BL1.
There is one source / drain region connected to node 1 and another source / drain region connected to node N2.
The NMOS (NM11) has a gate connected to the node N2, one source / drain region connected to the ground potential, and another source / drain region connected to the node N1. The NMOS (NM12) has a node N1
, One source / drain region connected to the ground potential, and another source / drain region connected to the node N2. The PMOS (PM13) has a gate connected to the word line WL12, one source / drain region connected to the bit line BL12,
There is another source / drain region connected to node N1. The PMOS (PM14) has a gate connected to the word line WL12, one source / drain region connected to the bit line -BL12, and another source / drain region connected to the node N2. PMOS (PM
11) has a gate connected to the node N2, one source / drain region connected to the power supply potential Vcc,
There is another source / drain region connected to node N1. The PMOS (PM12) has a gate connected to the node N1, one source / drain region connected to the power supply potential Vcc, and another source / drain region connected to the node N2. The bit line -BL11 is complementary to the bit line BL11, while the bit line -BL12 is complementary to the bit line BL12.

At the time of writing data to the bit lines BL12 and -BL12 and reading data from them,
The word line WL12 is biased at a low voltage to
The transistors PM13 and PM14 are turned on. On the other hand, when writing data to the bit lines BL11 and -BL11 and reading data from them, the NMOS
A high voltage sufficient to turn on the transistors NM13 and NM14 is applied.

In addition to the same numbers of the NMOS transistor and the PMOS transistor, the word lines WL11, WL1
2, bit lines BL11 and BL12, bit line -BL1
1, -BL12 are symmetric to each other.

FIG. 3 shows another embodiment of the present invention. In this embodiment, in addition to two NMOS transistors NM21 and NM22 and two PMOS transistors PM21 and PM22, two inverters INV
1, INV2 are added.

In FIG. 3, the inverter INV1 includes:
Although there is a first input terminal I1 and a first output terminal O1, the inverter INV2 has a second input terminal I2 and a second output terminal O2. The input terminal I2 is connected to the output terminal O1, and the input terminal I1 is connected to the second output terminal O2. The NMOS (NM21) has a word line WL21
, A source / drain region connected to the bit line BL21, and another source / drain region connected to the first output terminal O1. NMOS (N
M22) includes a gate connected to the word line WL21, a source / drain region connected to the bit line -BL21, and another source / drain connected to the first input terminal I1.
There is a drain region. The PMOS (PM21) has a gate connected to the word line WL22 and a bit line BL2.
2 and another source / drain region connected to the second input terminal I2. The PMOS (PM22) has a gate connected to the word line WL22, a source / drain region connected to the bit line -BL22, and another source / drain region connected to the second output terminal O2. .

Each element in the circuit shown in FIG. 3 functionally corresponds to the element in the circuit shown in FIG. For example,
The inverter INV1 includes an NMOS (NM11) and a PMO
This is equivalent to a combination with S (PM11). The inverter INV2 includes an NMOS (NM12) and a PMOS (PM
This is equivalent to the combination with 12). NMOS (NM2
1, NM22) and PMOS (PM21, PM22)
NMOS (NM13, NM14) and PMOS respectively
(PM13, PM14). In addition, node N
1 is equivalent to the first output terminal O1 and the second input terminal I2, while the node N2 is connected to the second output terminal O2.
And the first input terminal I1. Bit line BL2
1, -BL21, BL22, -BL22 correspond to bit lines BL11, -BL11, BL12, -BL12, respectively, and word lines WL21, WL22 correspond to word lines WL.
11, WL12. Therefore, the operation of the circuit shown in FIG.

In the dual port SRAM shown in FIG. 3, an NMOS (NM21, NM22) and a PMOS
(PM21, PM22) are used as pass gates. Further, the symmetrical layout of the dual port SRAM is compatible with the demand for high density and large capacity memory for high recording density.

[0019] Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary, with a true scope and spirit of the invention being indicated by the following claims.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a conventional dual-port SRAM.

FIG. 2 is a circuit diagram of a dual port SRAM according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of a dual port SRAM according to another embodiment of the present invention.

[Explanation of symbols]

NM1, NM2, NM3, NM4, NM5, NM6, N
M11, NM12, NM13, NM14, NM21, N
M22: N-type MOS transistor PM1, PM2, PM3, PM4, PM5, PM6, P
M11, PM12, PM13, PM14, PM21, P
M22: P-type MOS transistor BL1, BL2, BL11, BL12, BL21, BL
22, -BL1, -BL2, -BL11, -BL12,
-BL21, -BL22 ... bit lines WL1, WL2, WL11, WL12, WL21, WL
22, -WL1, -WL2, -WL11, -WL12,
-WL21, -WL22 ... word lines I1, I2 ... input terminals O1, O2 ... output terminals N1, N2 ... nodes

Claims (6)

[Claims] A first inverter having a first input terminal and a first output terminal, a second input terminal connected to the first output terminal, and a first input terminal connected to the first input terminal. A second inverter having a second output terminal connected thereto, a gate connected to a first word line, a source / drain region connected to a first bit line, and the first output. A first N-type MOS transistor having another source / drain region connected to a terminal, a gate connected to the first word line, and a source / drain region connected to a second bit line A second N-type MOS transistor comprising: a source / drain region connected to the first input terminal; a gate connected to a second word line; and a gate connected to a third bit line. Source / drain region and the second input A first P-type MOS transistor having another source / drain region connected to a second word line; a gate connected to the second word line; and a source / drain region connected to a fourth bit line. And a second P-type MOS transistor having another source / drain region connected to the second output terminal. 2. The first inverter, comprising: a gate connected to the first input terminal; a source / drain region connected to a power supply; and another source / drain connected to the first output terminal. A third P-type MOS transistor having a drain region, a gate connected to the first input terminal, a source / drain region connected to the ground potential, and a first output terminal connected to the first output terminal. 2. The dual port static random access memory according to claim 1, further comprising a third N-type MOS transistor having another source / drain region. 3. The second inverter, comprising: a gate connected to the second input terminal; a source / drain region connected to a power supply; and another source / drain connected to the second output terminal. A fourth P-type MOS transistor having a drain region, a gate connected to the second input terminal, a source / drain region connected to ground potential, and a second output terminal connected to the second output terminal. The dual port static random access memory according to claim 1, further comprising: a fourth N-type MOS transistor having another source / drain region. 4. A gate connected to a first word line;
Source / drain regions connected to the first bit line;
A first N-type MOS transistor having another source / drain region connected to a first node; a gate connected to the first word line; and a source connected to a second bit line A second N-type MOS transistor having a drain / drain region and another source / drain region connected to a second node; a gate connected to the second node; and a ground potential. A third N-type MOS transistor having a source / drain region and another source / drain region connected to the first node; a gate connected to the first node; and a connection to a ground potential A fourth N-type MOS transistor including a source / drain region connected to the second node and another source / drain region connected to the second node; a gate connected to a second word line; of A first P-type MOS transistor including a source / drain region connected to a bit line and another source / drain region connected to the first node; and a first MOS transistor connected to the second word line. A second P-type MOS transistor having a gate, a source / drain region connected to a fourth bit line, and another source / drain region connected to the second node; A third P-type MOS transistor including a gate connected to a node, a source / drain region connected to the power supply, and another source / drain region connected to the first node; A fourth P-type MOS transistor having a gate connected to one node, a source / drain region connected to the power supply, and another source / drain region connected to the second node. Dual-port static random access memory and a register. 5. An N-type MOS transistor selected from the first to fourth N-type MOS transistors and a same number of P-type MOS transistors selected from the first to fourth P-type MOS transistors.
5. The dual port static random access memory according to claim 4, further comprising a pass gate including a transistor. 6. The two N-type MOS transistors are selected to have one of first to fourth bit lines as a pass gate, and the two P-type MOS transistors are first to fourth bit lines. 6. The dual-port static random access memory according to claim 5, wherein one of the four bit lines is selected to have a pass gate.