CN113724753A - Memory cell of dual-port SRAM - Google Patents

Memory cell of dual-port SRAM Download PDF

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Publication number
CN113724753A
CN113724753A CN202110925185.7A CN202110925185A CN113724753A CN 113724753 A CN113724753 A CN 113724753A CN 202110925185 A CN202110925185 A CN 202110925185A CN 113724753 A CN113724753 A CN 113724753A
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pull
tube
threshold voltage
selection
pipe
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李勇
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention relates to a memory cell of a dual-port SRAM, which relates to the design of a semiconductor integrated circuit.A selection tube corresponding to WLA and WLB is changed from only an N-type standard threshold voltage (NSVT) to an N-type standard threshold voltage (NSVT) and a combination of an N-type high threshold voltage (NHVT), so that the voltage coupled to a node from BL is restrained, thus the read interference is restrained, and the process is simple.

Description

Memory cell of dual-port SRAM
Technical Field
The invention relates to semiconductor integrated circuit design, in particular to a memory cell of a dual-port SRAM.
Background
With the development of computers and smart phones, the frequency of an internal core processor is higher and higher, and the functions are stronger and stronger. Static Random-Access Memory (SRAM) is one type of Random Access Memory. At present, more than half of the area of a CPU and a system on chip (SoC) is occupied by an SRAM, which is mainly benefited by the fact that the SRAM has higher speed and smaller leakage current and can meet the requirements of the CPU/SoC on the capacity, the bandwidth and the speed of a buffer. There are many performance metrics for semiconductor memories, the most important of which is the access speed and stability of the memory. The Dual-port SRAM (Dual-port SRAM) is used as a first-level cache memory (cache) of the CPU, the read-write speed and the stability of the Dual-port SRAM are more important parameters, and the actual operation speed of the CPU is directly influenced
Disclosure of Invention
The invention provides a memory cell of a dual-port SRAM, which comprises: the first CMOS inverter consists of a first pull-up tube PU1 and a first pull-down tube PD 1; the second CMOS inverter is composed of a second pull-up tube PU2 and a second pull-down tube PD2, the output end of the second CMOS inverter is connected with the input end of the first CMOS inverter to form a first storage node Q, the output end of the first CMOS inverter is connected with the input end of the second CMOS inverter to form a second storage node Qb, and the first storage node Q and the second storage node Qb are mutually opposite in phase and are mutually latched; PG1-A, PG1-B, PG2-A and PG2-B four selection transistors, two WLs of WLA and WLB and two sets of BL/BLB// BLA and BLB// BLB, wherein selection pipe PG1-B corresponds to/BLA, selection pipe PG2-B corresponds to BLB, selection pipe PG1-A corresponds to BLA, selection pipe PG2-A corresponds to/BLB, WLA controls selection pipe PG1-B and selection pipe PG1-A, WLB controls selection pipe PG2-B and selection pipe PG2-A, the sources of first pull-up pipe PU1 and second pull-up pipe PU2 are both connected to a supply voltage Vdd, the sources of first pull-down pipe PD1 and second pull-down pipe PD2 are both grounded, selection pipe PG1-A and selection pipe PG2-B are also connected to a first storage node Q, selection pipe PG1-B and selection pipe PG2-B are also connected to a second storage node QQ, the metal grids of one of the WLA-controlled selection tube PG1-B and PG1-a and one of the WLB-controlled selection tube PG2-B and PG2-a have a first work function layer that makes the threshold voltages of one of the selection tube PG1-B and PG1-a and one of the selection tube PG2-B and PG2-a first threshold voltage, and the first threshold voltage is a high threshold voltage of N-type.
Furthermore, the four selection transistors PG1-A, PG1-B, PG2-A and PG2-B are NMOS transistors.
Further, the first pull-up tube PU1 and the second pull-up tube PU2 are both PMOS tubes.
Further, the first pull-down tube PD1 and the second pull-down tube PD2 are both NMOS tubes.
Furthermore, the gate structures of the first pull-up tube PU1, the second pull-up tube PU2, the first pull-down tube PD1, the second pull-down tube PD2, the selection transistor PG1-A, the selection transistor PG1-B, the selection transistor PG2-A and the selection transistor PG2-B are all metal gates.
Further, the metal grids of the other of the WLA-controlled selection tube PG1-B and PG1-a and the other of the WLB-controlled selection tube PG2-B and PG2-a have a second work function layer that makes the threshold voltages of the other of the selection tube PG1-B and PG1-a and the other of the selection tube PG2-B and PG2-a second threshold voltage, and the second threshold voltage is a standard threshold voltage of N type.
Furthermore, the metal grids of the first pull-up tube PU1 and the second pull-up tube PU2 have a third work function layer, and the third work function layer enables the threshold voltages of the first pull-up tube PU1 and the second pull-up tube PU2 to be a third threshold voltage, and the third threshold voltage is a P-type standard threshold voltage.
Further, the metal gates of the first and second pull-down tubes PD1 and PD2 have a fourth work function layer, which makes the threshold voltages of the first and second pull-down tubes PD1 and PD2 be fourth threshold voltages, and the fourth threshold voltages are N-type standard threshold voltages.
Further, the high threshold voltage of the N-type is realized by an implantation process in a well process or a Pocket process.
Furthermore, a high threshold voltage of N-type is achieved by a work function adjustment process.
Drawings
Fig. 1 is an ideal circuit diagram corresponding to a typical 8T-type dual port SRAM.
Fig. 2 is a layout diagram of a memory cell of a dual-port SRAM according to an embodiment of the present invention.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 1, fig. 1 is an ideal circuit diagram corresponding to a typical 8T-type dual port SRAM. 8T represents that the memory unit has 8 transistors, as shown in FIG. 1, the dual-port SRAM is composed of two P-type pull-up transistors of PU1 and PU2, two N-type pull-down transistors of PD1 and PD2, and four selection transistors of PG1-A, PG1-B, PG2-A and PG2-B, two WLs of WLA and WLB and two groups of BL/BLB of BLA// BLA and BLB// BLB exist, and the function of simultaneous reading can be realized. In the unit design of the dual-port SRAM, a selection pipe PG1-B corresponds to/BLA, a selection pipe PG2-A corresponds to/BLB, a selection pipe PG1-A corresponds to BLA, and a selection pipe PG2-B corresponds to BLB. WLA controls selection tubes PG1-B and PG1-A, and WLB controls selection tubes PG2-B and PG 2-A. The P-type pull-up tube PU1 and the N-type pull-down tube PD1 form a CMOS phase inverter, the P-type pull-up tube PU2 and the N-type pull-down tube PD2 also form a CMOS phase inverter, the two CMOS phase inverters are connected end to form a latch, and the latch comprises a first storage node Q and a second storage node Qb which are mutually opposite in phase and are interlocked. The sources of the P-type pull-up transistors PU1 and PU2 are both connected to a power supply voltage Vdd, and the sources of the N-type pull-down transistors PD1 and PD2 are both grounded Vss.
For example, when Q is "0" and Qb is "1", the read current Iread at the BLA terminal reaches Vss through PG1-a and PD1, and the read current Iread at the/BLB terminal reaches Vss through PG2-B and PD1, thereby realizing read-out.
However, if WLA or WLB is turned on during a read operation, the BL voltage is coupled to the node, which may cause the node voltage to increase, and if the node voltage changes too much, the bit cell may be inverted, resulting in a fatal error. Read disturb is an important consideration for dual port SRAM.
An embodiment of the invention provides a memory cell of a dual-port SRAM, please refer to fig. 1, and refer to fig. 2, which is a layout diagram of the memory cell of the dual-port SRAM according to an embodiment of the invention. The invention relates to a memory cell of a dual-port SRAM, which comprises:
the first CMOS inverter consists of a first pull-up tube PU1 and a first pull-down tube PD 1;
the second CMOS inverter is composed of a second pull-up tube PU2 and a second pull-down tube PD2, the output end of the second CMOS inverter is connected with the input end of the first CMOS inverter to form a first storage node Q, the output end of the first CMOS inverter is connected with the input end of the second CMOS inverter to form a second storage node Qb, and the first storage node Q and the second storage node Qb are mutually opposite in phase and are mutually latched;
PG1-A, PG1-B, PG2-A and PG2-B four selection transistors, two WLs of WLA and WLB, and two sets of BL/BLB// BLA and BLB// BLB, realizing the function of simultaneous reading, wherein selection pipe PG1-B corresponds to/BLA, selection pipe PG2-B corresponds to BLB, selection pipe PG1-A corresponds to BLA, selection pipe PG2-A corresponds to/BLB, WLA controls selection pipe PG1-B and selection pipe PG1-A, WLB controls selection pipe PG2-B and selection pipe PG2-A, the sources of first pull-up pipe PU1 and second pull-up pipe PU2 are both connected with a power supply voltage Vdd, the sources of first pull-down pipe PD1 and second pull-down pipe PD2 are both grounded Vss, selection pipe PG 6-A and selection pipe PG2-B are also connected with a first storage node Q, selection pipe PG 3527-B and selection pipe PG 73727-B are also connected with a second storage node QPG 73727-B, the metal grids of one of the WLA-controlled selection tube PG1-B and PG1-a and one of the WLB-controlled selection tube PG2-B and PG2-a have a first work function layer that makes the threshold voltage of one of the selection tube PG1-B and PG1-a and one of the selection tube PG2-B and PG2-a first threshold voltage, and the first threshold voltage is a high threshold voltage of N-type, that is, NHVT.
In one embodiment, the PG1-A, PG1-B, PG2-A and PG2-B four select transistors are NMOS transistors.
In one embodiment, the first pull-up tube PU1 and the second pull-up tube PU2 are both PMOS tubes.
In one embodiment, the first pull-down tube PD1 and the second pull-down tube PD2 are both NMOS tubes.
In an embodiment, the gate structures of the first pull-up tube PU1, the second pull-up tube PU2, the first pull-down tube PD1, the second pull-down tube PD2, the select transistor PG1-a, the select transistor PG1-B, the select transistor PG2-a, and the select transistor PG2-B all use metal gates and are finfets.
In one embodiment, the metal grids of the other of the WLA-controlled selection tube PG1-B and PG1-a and the other of the WLB-controlled selection tube PG2-B and PG2-a have a second work function layer that causes the threshold voltages of the other of the WLA-controlled selection tube PG1-B and PG1-a and the other of the WLB-controlled selection tube PG2-B and PG2-a to be second threshold voltages, and the second threshold voltages are N-type standard threshold voltages, i.e., NSVT.
In an embodiment, the metal grids of the first pull-up tube PU1 and the second pull-up tube PU2 have a third work function layer, and the third work function layer makes the threshold voltages of the first pull-up tube PU1 and the second pull-up tube PU2 be a third threshold voltage, and the third threshold voltage is a P-type standard threshold voltage, PSVT.
In an embodiment, the metal gates of the first pull-down tube PD1 and the second pull-down tube PD2 have a fourth work function layer, and the fourth work function layer makes the threshold voltages of the first pull-down tube PD1 and the second pull-down tube PD2 be a fourth threshold voltage, and the fourth threshold voltage is an N-type standard threshold voltage, that is, NSVT.
In one embodiment, the high threshold voltage of N-type, i.e., NHVT, may be achieved by a well process or an implantation process in a Pocket process.
In one embodiment, the high threshold voltage of N-type, NHVT, described above, may be achieved by a work function adjustment process.
As shown in fig. 2, BLA and/BLA are both represented by BLA, BLB and/BLB are both represented by BLB, and the layout of the memory cell of the dual port SRAM includes: the fin bodies 102 are arranged in parallel, and the grid structures of the first pull-up tube PU1, the second pull-up tube PU2, the first pull-down tube PD1, the second pull-down tube PD2, the selection transistor PG1-A, the selection transistor PG1-B, the selection transistor PG2-A and the selection transistor PG2-B cover the side surfaces and the top surface of the fin bodies 102. In addition, the layout structure has a region where the gate structure is not required to be formed, so that a portion of the fin 102 is cut off, as indicated by a mark 102a in fig. 2. And a plurality of metal grids 103, wherein the metal grids 103 are arranged in parallel and are arranged in a crossed manner on the fin body 102, a metal grid is formed in a crossed region of the fin body 102 and the metal grids 103, and each metal grid comprises a work function layer and a metal conductive material layer. Vias 104, which are typically layer zero vias, are designated as M0 PO. Metal layer 105, metal layer 205, and typically the zeroth metal layer are denoted as M0D.
As shown in fig. 2, the pull-up tube is formed on a fin 202, as shown by the region 106, which is a P-type standard threshold voltage PSVT. The pull-down tubes are formed on the six fins 202, as shown in the region 107, which is the standard threshold voltage of N-type, NSVT. One of the WLA controlled selection tube PG1-B and PG1-A and one of the WLB controlled selection tube PG2-B and PG2-A are formed on the two fins 202, as in the region indicated by reference numeral 108, which is a high threshold voltage of N-type, NHVT. The other of the WLA controlled selection tube PG1-B and PG1-A and the other of the WLB controlled selection tube PG2-B and PG2-A are formed on three fins 202, as in the regions indicated by reference numerals 109 and 110, which are N-type standard threshold voltages, i.e., NSVT.
Therefore, the voltage coupled from the BL to the node is inhibited by changing the selection tubes corresponding to the WLA and the WLB from the combination of the N-type standard threshold voltage, namely NSVT, to the N-type standard threshold voltage, namely NSVT, and the N-type high threshold voltage NHVT, so that the read interference is inhibited, and the process is simple.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims (10)

1. A memory cell of a dual port SRAM, comprising:
the first CMOS inverter consists of a first pull-up tube PU1 and a first pull-down tube PD 1;
the second CMOS inverter is composed of a second pull-up tube PU2 and a second pull-down tube PD2, the output end of the second CMOS inverter is connected with the input end of the first CMOS inverter to form a first storage node Q, the output end of the first CMOS inverter is connected with the input end of the second CMOS inverter to form a second storage node Qb, and the first storage node Q and the second storage node Qb are mutually opposite in phase and are mutually latched;
PG1-A, PG1-B, PG2-A and PG2-B four selection transistors, two WLs of WLA and WLB and two sets of BL/BLB// BLA and BLB// BLB, wherein selection pipe PG1-B corresponds to/BLA, selection pipe PG2-B corresponds to BLB, selection pipe PG1-A corresponds to BLA, selection pipe PG2-A corresponds to/BLB, WLA controls selection pipe PG1-B and selection pipe PG1-A, WLB controls selection pipe PG2-B and selection pipe PG2-A, the sources of first pull-up pipe PU1 and second pull-up pipe PU2 are both connected to a supply voltage Vdd, the sources of first pull-down pipe PD1 and second pull-down pipe PD2 are both grounded, selection pipe PG1-A and selection pipe PG2-B are also connected to a first storage node Q, selection pipe PG1-B and selection pipe PG2-B are also connected to a second storage node QQ, the metal grids of one of the WLA-controlled selection tube PG1-B and PG1-a and one of the WLB-controlled selection tube PG2-B and PG2-a have a first work function layer that makes the threshold voltages of one of the selection tube PG1-B and PG1-a and one of the selection tube PG2-B and PG2-a first threshold voltage, and the first threshold voltage is a high threshold voltage of N-type.
2. The memory cell of the dual-port SRAM of claim 1, wherein the four select transistors PG1-A, PG1-B, PG2-A and PG2-B are NMOS transistors.
3. The memory cell of the dual-port SRAM of claim 1, wherein the first pull-up PU1 and the second pull-up PU2 are both PMOS transistors.
4. The memory cell of the dual-port SRAM of claim 1, wherein the first pull-down tube PD1 and the second pull-down tube PD2 are NMOS tubes.
5. The memory cell of the dual-port SRAM of claim 1, wherein the gate structures of the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, the second pull-down transistor PD2, the select transistor PG1-A, the select transistor PG1-B, the select transistor PG2-A and the select transistor PG2-B all employ metal gates.
6. The memory cell of the two-port SRAM of claim 1, wherein the metal gates of the other of the WLA controlled select tube PG1-B and PG1-A and the other of the WLB controlled select tube PG2-B and PG2-A have a second work function layer that makes the threshold voltage of the other of the select tube PG1-B and PG1-A and the other of the select tube PG2-B and PG2-A a second threshold voltage, and the second threshold voltage is a standard threshold voltage of the N-type.
7. The memory cell of the dual-port SRAM of claim 1, wherein the metal gates of the first pull-up transistor PU1 and the second pull-up transistor PU2 have a third work function layer, the third work function layer enables the threshold voltages of the first pull-up transistor PU1 and the second pull-up transistor PU2 to be a third threshold voltage, and the third threshold voltage is a standard threshold voltage of P-type.
8. The memory cell of the dual port SRAM of claim 1, wherein the metal gates of the first pull-down tube PD1 and the second pull-down tube PD2 have a fourth work function layer, the fourth work function layer enables the threshold voltages of the first pull-down tube PD1 and the second pull-down tube PD2 to be a fourth threshold voltage, and the fourth threshold voltage is a standard threshold voltage of N type.
9. The memory cell of the dual-port SRAM of claim 1, wherein the high threshold voltage of N-type is achieved by an implantation process in a well process or a Pocket process.
10. The memory cell of the two-port SRAM of claim 1, wherein the high threshold voltage of N-type is achieved by a work function adjustment process.
CN202110925185.7A 2021-08-12 2021-08-12 Memory cell of dual-port SRAM Pending CN113724753A (en)

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Application Number Priority Date Filing Date Title
CN202110925185.7A CN113724753A (en) 2021-08-12 2021-08-12 Memory cell of dual-port SRAM

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CN113724753A true CN113724753A (en) 2021-11-30

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