KR100237011B1 - Memory cell array - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an array of memory cells, in which two adjacent memory cells share one load resistance to prevent an increase in the size of the device due to the size of the load resistance. Relates to an array.

Description

Memory cell array

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory cell array, and more particularly, to a memory cell array capable of improving the integration degree of static random access memory (SRAM) devices.

In general, an SRAM device is a volatile memory device having a function of writing information to or reading information from a memory cell formed of a flip-flop circuit. Such a memory device includes a memory cell array and peripheral circuits in which a plurality of memory cells are connected in a matrix manner between a word line and a bit line, and then a conventional memory cell array is formed into a first circuit. When described with reference to Figure 2 and as follows.

As shown in FIG. 1, a memory cell array of a conventional SRAM device includes a first transfer transistor having a gate terminal connected to a word line WL between a first bit line BL and a first node N1. A second transfer transistor T2 having a T1 connected thereto and a gate terminal connected to the word line WL is connected between the second bit line / BL and the second node N2. In addition, a memory cell MC configured as a flip-flop circuit is connected between the first node N1 and the second node N2, and a first load resistor (V1) is connected between the first node N1 and the power supply voltage Vcc. R1) is connected, and a second load resistor R2 is connected between the second node N2 and the power supply voltage Vcc. In addition, each of the memory cells MC is connected between the first node N1 and the ground, and the first transistor Q1, the second node N2, and the ground having a gate terminal connected to the second node N2. The second transistor Q2 is connected to the gate terminal and is connected to the first node N1.

The memory cell array is operated according to signals input through the word line WL and the first and second bit lines BL and / BL. That is, when a high potential signal is input through the word line WL, the first and second transfer transistors T1 and T2 are turned on, and the first and second bit lines BL and Information is written into or read from the memory cell MC according to a signal input through / BL). Here, the write operation is such that the first and second nodes N1 and N2 maintain the same potential as the power supply voltage Vcc and the ground voltage. In this case, the first node N1 and the second node N2 are maintained. Always maintains the opposite potential state. However, the first and second load resistors R1 and R2 for applying a power supply voltage Vcc to the first and second nodes N1 and N2 are undoped polysilicon on a silicon substrate. It takes a large area because it is formed as), which acts as a difficult factor to improve the degree of integration of the device. Recently, the first and second load resistors R1 and R2 are replaced by P-type MOS thin film transistors (TFTs) having excellent operating characteristics. The explanation is as follows.

A first transfer transistor T11 having a gate terminal connected to the word line WL is connected between the first bit line BL and the first node N11, and the second bit line / BL and the second node N12 are connected. Is connected to the second transfer transistor T12 having its gate terminal connected to the word line WL. A memory cell MC configured as a flip-flop circuit is connected between the first node N11 and the second node N12, and a first transistor Q11 is connected between the first node N11 and the power supply voltage Vcc. ) Is connected and a third transistor Q13 is connected between the second node N12 and the power supply voltage Vcc. The P-type MOS thin film transistor operates as a resistor in the first and third transistors Q11 and Q13. It is configured to be. In addition, each of the memory cells MC is connected between the first node N11 and the ground, and the second transistor Q12 and the second node N12 and the ground whose gate terminal is connected to the second node N12 are grounded. The fourth transistor Q14 is connected to the gate terminal and is connected to the first node N11.

However, since the memory cell array includes two load resistors in one memory cell, each memory cell occupies a large area on the silicon substrate, thereby limiting device integration.

Accordingly, an object of the present invention is to provide an array of memory cells that can solve the above disadvantages by allowing two adjacent memory cells to share one load resistance.

According to an aspect of the present invention, a first transfer transistor is connected between a first bit line and a first node, and a gate terminal is connected to a word line, and a second bit line is connected between a second node and a gate terminal. A second transfer transistor connected to a word line, a memory cell connected between the first node and the second node and configured as a flip-flop circuit, and a second node of another memory cell adjacent to one side of the first node and the second node; And a second load resistor connected between the connection point of the first node and the power supply voltage of the first node of another memory cell adjacent to the other side of the second node. The memory cell is connected between the first node and ground, and a first transistor having a gate terminal connected to the second node, and between the second node and ground, and a gate terminal is connected to the first node. Characterized by comprising a second transistor connected to the de-and the first and second load resistance it is characterized by consisting of a P-MOS thin film transistor.

1 and 2 are circuit diagrams for explaining a conventional memory cell array.

3 is a circuit diagram illustrating a memory cell array according to the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

The present invention provides a method of reducing the size of a memory cell array in which a plurality of memory cells are connected in a matrix manner between a plurality of word lines and a plurality of first and second bit lines through transfer transistors. The load resistance is to be shared. That is, in the memory cell array according to the present invention, as illustrated in FIG. 3, a first transfer transistor T21 having a gate terminal connected to a word line WL between a first bit line BL and a first node N21. ) Is connected, and a second transfer transistor T22 having a gate terminal connected to the word line WL is connected between the second bit line / BL and the second node N22. In addition, a memory cell MCB configured as a flip-flop circuit is connected between the first node N21 and the second node N22, and is adjacent to one side of the first node N21 of the memory cell MCB. The first load resistor Q21 is connected between the connection point of the second node N22 of the other memory cell MCA and the power supply voltage Vcc, and the memory cell MCB is different from the second node N22. The second load resistor Q23 is connected between the connection point of the first node N21 of the other memory cell MCC adjacent to the side and the power supply voltage Vcc. In addition, each of the memory cells is connected between the first node (N21) and the ground, the gate terminal is connected between the first transistor (Q22) and the second node (N22) and ground connected to the second node (N22). A gate terminal includes a second transistor Q24 connected to the first node N21, and the first and second load resistors Q21 and Q23 are configured such that the P-type MOS thin film transistor is operated as a resistor, respectively.

The memory cell array is operated according to signals input through the word line WL and the first and second bit lines BL and / BL. That is, when a high potential signal is input through the word line WL, the first and second transfer transistors T21 and T22 are turned on, and the first and second bit lines BL and / BL are turned on. Information is written into or read from the memory cell MC according to a signal input through the readout. Here, the write operation is such that the first and second nodes N21 and N22 maintain the same potential as the power supply voltage Vcc and the ground voltage, respectively. In this case, the first node N21 and the second node N22 ) Always maintains the opposite potential state.

For example, when writing information into a memory cell MCB, a high potential signal is input through the word line WL and the first bit line BL, respectively. In this case, the second bit line / BL ), A low potential signal is input. Then, the first and second transfer transistors T21 and T22 are turned on, whereby the first transistor Q22 is turned on so that the first node N21 is in a ground potential state. In this case, since the second transistor Q24 maintains a turn off state, power is supplied to the second node N22 through the first load resistor Q21 connected to an adjacent memory cell MCC. Voltage Vcc is applied. As a result, the first node N21 and the second node N22 maintain opposite potentials.

In addition, when the information written in the memory cell MCB is to be read, the high potential signal is input through the word line WL to turn on the first and second transfer transistors T21 and T22. Then, the voltage applied to the first node N21 is applied to the second bit line / BL and the voltage applied to the second node N22 is applied to the first bit line BL. The state of information is sensed by the state of current flowing through the first and second bit lines BL and / BL.

As described above, according to the present invention, two adjacent memory cells share one load resistance, thereby reducing the total number of load resistors. Therefore, the size of the memory cell array is reduced, and thus there is an excellent effect that the degree of integration of the device can be improved.

Claims (4)

A memory cell array consisting of memory cells connected between a plurality of bit lines and word lines, comprising: a first transfer transistor connected between a first bit line and a first node and having a gate terminal connected to a word line; A second transfer transistor connected between two nodes and having a gate terminal connected to the word line, a plurality of memory cells connected between the first node and the second node and having a flip-flop circuit, and on one side of the first node; A first load resistor connected between a connection point and a power supply terminal of a second node of an adjacent memory cell, and a second load resistor connected between a connection point and a power supply terminal of a first node of a memory cell adjacent to one side of the second node Memory cell array, characterized in that consisting of. 2. The memory device of claim 1, wherein the memory cell is connected between the first node and a ground terminal, a gate terminal is connected between the second node, and the second node and the ground terminal, and a gate terminal is connected to the first node. And a second transistor connected to one node. 2. The memory cell array of claim 1, wherein the first and second load resistors are P-type MOS transistors. 4. The memory cell array of claim 3, wherein the transistor is a thin film transistor.