JP2000224127A - Signalling processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To flexibly cope with a signalling processing for the portion of an optional highway number with a simple circuit configuration by processing extraction data from plural highways at high speed, through the means of a time division multiplex mode through the use of a single data processing means. SOLUTION: A signalling processing circuit executes a data processing, such as monitoring, working and converting with respect to specified time division multiplex data on highways. That is, a data extracting means 1 extracts plural kinds of data ai to di from plural input highways CHa to CHd. An ID adding means 2 adds different identifying ID (a/ti to d/ti or the like) to each output data of the means 1. A data processing means 3 data-processes each output data (ai to di) of the means 2 by time division. A data distributing means 4 distributes the respective kinds of output data ai' to di' of the means 3 to corresponding output highways CHa' to CHd' according to the identifying ID (a/ti to d/ti). Thus, multiple kinds of data are efficiently processed with the simple configuration.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signaling processing circuit, and more particularly, to monitoring, processing, and conversion of predetermined time-division multiplexed data on a highway, which is mounted on an exchange, a transmission device, a repeater or the like in a network system. The present invention relates to a signaling processing circuit that performs data processing of (1). In recent years, with the increase in the number of subscribers and communication (call) traffic,
It is desired to efficiently process a large number of such data with a simple circuit configuration.

[0002]

2. Description of the Related Art FIG. 6 is a diagram for explaining the prior art, and shows a block diagram of a conventional signaling processing circuit. In the figure, the signaling processing circuit composed of the LSI or the like 50, 51 input highways CH _a serial converts the serial signal according to the clock signal SCK of the input highways to the 8-bit parallel data - parallel converter (S
/ P), 52 is a register (REG) holding the output data of the S / P 51, and 53 is a logical operation unit that performs data processing such as monitoring, processing, conversion, etc. on the processing target data (generated at t _i ) of the output of the REG 52 (ALU) and 54 store output data of the ALU 53 in a FIFO mode, and an output buffer (OBF) for absorbing a time delay between input and output frames, and 55 store the output data of the OBF 54 as a clock signal SCK 'of an output highway. , A parallel-serial converter (P /
S) and 56 are input / output highway frame synchronization signals F
A timing control unit for generating a timing signal (clock signal SCK / SCK ', data transfer activation signal TXE / TXE', etc.) of the digital synchronous system based on P / FP ' (MEM) for storing related data, previous processing result data, etc.). It should be noted that the ALU 54 allows data that is not to be processed (such as call data) to pass through as it is.

[0003] In the frame signal of the input highway (port) CH _a, t ₁ ~t each data signal a1~a3 according to the signaling processing subscriber a1~a3 Each slot timing _3, also slot timing t ₄ Are time-division multiplexed with data signals a4 related to network monitoring signaling processing. Although the slot timings t _{1 to} t ₄ normally occur in one frame, they are drawn continuously to save space. Under the digital synchronization system, the slot timings t _{1 to} t ₄ are properly managed by the timing control unit 56 synchronized with the frame synchronization signal FP.

[0004] Data signals a1 of the input is converted to a section of the slot timing t ₁ into parallel data by S / P51, it is latched into REG52 to the timing of the subsequent data transfer energizing signal TXE = 1. This data a1 is ALU5
3 receives predetermined data processing. At this time, if necessary,
Reference data RD from 57 is used for the processing operation. The data a1 'of the processing result thus obtained is temporarily stored in the OBF5
4 and is read out in synchronization with the slot timing t ₁ 'of the output frame, converted into a serial signal by the P / S 55, and output highway (port) C
It is output to Ha '. The same applies to other data a2 to a4.

[0005] In this case, in the above-mentioned conventional method, even when the processing target data of the highway (channel) CHa is the shortest, the data is generated at eight clock intervals of SCK.
Has been configured to process data per data within eight clocks of SCK. That is, in the conventional signaling processing circuit, the arithmetic processing in the ALU 53 is restricted by the system clock signal SCK.

[0006]

[0006] However, the above by conventional signaling processing circuit, for example, and that processes the data of 4 highway (port) min CH _a to CH _d inputs, two clock cycles of SCK to per data Had to be processed, making it virtually impossible to process. So when trying to process a lot of data,
In the conventional method, it is necessary to provide a plurality of signaling processing circuits for the number of highways (ports) in parallel, and there is a disadvantage that the circuit scale becomes enormous.

[0007] The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide a signaling circuit capable of flexibly coping with a signaling process for an arbitrary number of highways (ports) with a simple circuit configuration. It is to provide a processing circuit.

[0008]

The above-mentioned problem is solved, for example, by referring to FIG.
Is solved. That is, the signaling processing circuit of the present invention (1) is a signaling processing circuit that performs data processing such as monitoring, processing, conversion, and the like for predetermined time-division multiplexed data on the highway,
_a from to CH _d and data extraction unit 1 for extracting a plurality of data a _i to d _i, adds different identification ID to the output data of the data extracting means _{1 (a / t i ~d /} t i , etc.) ID
Adding means 2 and each output data _{ai to} d of ID adding means 2
_i and the data processing means 3 for data processing in a time division output highway CH corresponding to the output data a _{i'~d i} 'of the data processing unit 3 in accordance with the identification _{ID (a / t i ~d /} t i) data distribution means for distributing to _{a'~CH d} '4
Is provided.

In the present invention (1), a large amount of data can be efficiently processed with a simple configuration by processing data extracted from a plurality of highways at high speed in a time division multiplex mode by a single data processing means. . In this case, the data extracted from the plurality of highways have different identification IDs.
With the configuration in which D is added, multiplexing, data processing, and distribution of each data can be performed efficiently and accurately.

[0010] Preferably, in the present invention (2), in the present invention (1), ID adding unit 2 identifies the highway corresponding to each output data a _i to d _i of the data extraction means 1 IDa～d Is added. Therefore, the data processing unit 3 can efficiently and appropriately perform data processing for each highway (for example, unique to each highway). In addition, the up / down highway signals can be efficiently processed by the common signaling circuit.

[0011] Preferably, in the present invention (3), in the present invention (2), ID adding unit 2 further identification of the time slot corresponding to each output data a _i to d _i of the data extraction unit 1 adding IDt _i. Therefore,
The data processing means 3 can efficiently and accurately perform data processing for each time slot (for example, unique to each time slot). Further, even _if the data processing in a certain time slot t _n of the system is prolonged and shifted to the time slot t _{n + 1} , the identification ID at the time of extraction (= t _n ) is added to the data to be processed. The data can be properly processed and distributed.

[0012] Preferably, in the present invention (4), above in the present invention (1), each output data a _i to d _i the identification ID of the ID adding unit _{2 (a, t i ~d,} t
_i ) and an input buffer 5 for storing in time series.
Therefore, even if the number of data to be processed temporarily exceeds the processing capacity of the data processing means 3, each data can be processed without omission. In other words, even if the number of highways to be processed or the number of subscribers (data) multiplexed for each highway increases / decreases, it can be easily absorbed by increasing / decreasing the capacity of the input buffer 5.

Preferably, in the present invention (5),
In the present invention (1), each of the data processing means 3
Output data a_i'~ D_i′ With its identification ID (a, t_i~
d, t _i) And an output buffer 6 that stores the data in time series.
I can. Therefore, the output highway CH_a´ ~ CH_d´ no
Even if there is a delay in the data read phase,_i
'~ D_i′ Can be held without leakage.

Further, the signaling processing circuit of the present invention (6) is a signaling processing circuit for performing data processing such as monitoring, processing, conversion and the like for predetermined time-division multiplexed data on a highway, and a plurality of data from a plurality of input highways. Data extraction means to be extracted, each output data of the data extraction means are selected in a time-division manner, and data selection means for holding highway information of the data until the processing of the selected data is completed; Data processing means for performing data processing in a time series, and data distribution means for distributing each output data of the data processing means to corresponding output highways in accordance with highway information held by the data selection means.

In the present invention (6), a large number of data can be efficiently processed with a simple configuration by processing the extracted data from a plurality of highways at a high speed in a time division multiplex mode by a single data processing means. . In such a case, each extracted data from a plurality of highways is selected in a time-division manner, and the highway information of the data is retained until the processing of the selected data is completed.
Even if D is not added, multiplexing, data processing, and distribution of each data can be performed efficiently and accurately. Further, the circuit configuration and wiring patterns are significantly reduced.

[0016]

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings.

FIG. 2 is a block diagram of a signaling processing circuit according to the first embodiment. By adding a different identification ID to each processing target data for each highway and each slot timing, each processing data can be processed by a digital synchronous system. This figure shows a case in which each processing data can be processed at high speed and flexibly asynchronously with the system, regardless of the time slot to be managed.

In the figure, S / P is a serial-parallel converter, REG is a register, A is an AND gate circuit, B
Is a buffer circuit having three outputs, O is an OR gate circuit, 11 and 12 are data buses, 13 is a priority unit (PRU) for performing priority reception control of processing data,
Numeral 14 denotes a logical operation unit (ALU) for performing signaling processing of processing data, 15 an output buffer (OBF) for temporarily holding the operation result of the ALU 14 and absorbing a frame delay between input / output highways, 16 Is OBF
Reference numeral 15 denotes a buffer control unit (BC) for performing reading control, reference numeral 17 denotes a decoder (DEC) for decoding an identification ID, and reference numeral 18 stores various data (operation method, previous processing result data, subscriber data, etc.) relating to signaling processing. Memory (M
EM) and P / S are parallel-serial converters.

[0019] Note that the data other than the processing target among the respective input highways CH _a ~CH _d (audio data), for example as shown in FIG. 1, the input highways CH _a ~
Each output highway CH _a ′ from CH _d via respective main signal lines To CH _d ′.

This signaling processing circuit (LSI)
For example, it has four input / output ports and a single AL
In U14, signaling processing for up to four highways (ports) can be executed. The following is described mainly a signaling process for highway CH _a, it is performed in substantially parallel with the same signaling process for the other highway CH _b ~CH _d.

Slot timing t₁In the section of
Elephant signal a1 is converted to parallel data by S / P1
At the timing of the subsequent data transfer energizing signal TXE.
Latched by EG1. In this case, the upper video of REG1
The highway (port) number = a and the digital
Timing slot number t managed by the synchronization system _i
(= T₁) Are input, and these are the data a1 and
Both are latched by REG1. That is, the original data a1
On the other hand, a unique name (identification ID) is added. Other high
Way CH_b~ CH_dTo each extracted data b1 to d1 from
The same applies to the case.

As a result, REG1 to RE
Priority request signals PRQ1 to PR from G4
Q4 is input. This priority request signal PRQ
1 to PRQ4 are signals indicating that data is latched in REG1 to REG4.
Bit signals that do not become "0" in a to d can be used. The PRU 13 outputs priority permission signals PAK1 to PAK4 in accordance with a predetermined priority order with respect to the input priority request signals PRQ1 to PRQ4.
An example priority is PRQ1>PRQ2>PRQ3> PR
It decreases in the order of Q4. Therefore, when PRQ1 to PRQ4 simultaneously become “1”, PAK1 = 1 is output first.

The buffer circuit B1 is activated by PAK1 = 1, and the output data a, t _i (= t ₁ ), a of REG1
1 is placed on the data bus 11. On the other hand, ALU14
The signal is activated by PAK = 1 (the occurrence of an event indicating the occurrence of processing target data) of the output of the R gate circuit O1, and starts the signaling processing operation regarding the input data a1. This processing operation is preferably performed at the maximum speed achievable by the LSI using the extremely high-speed clock signal HCK. At that time, according to the identification ID (= a, t ₁ ) of the input data a1, various methods corresponding to the identification ID (for example, a: for a down highway, b: for an up highway, t ₁ : for a subscriber, t ₄ : network monitoring etc.) can be executed. In that case, MEM1
8, the corresponding reference data RD is read, and the necessary logical operation is performed using this. Thus, the input output data a1' from the data a1 is generated, the output data a1' is buffered in the identification ID (= a, t ₁₎ with OBF15.

An example of the OBF 15 is a FIFO type buffer, and the buffer control unit 16 outputs the output data of the ALU 14 in synchronization with the processing end signal EOP of the ALU 14.
Write to 15. The processing end signal EOP is set to AN
The signals are also input to the D gate circuits A1 to A5, whereby the processing is completed this time (that is, corresponding to PAK1 = 1).
The data (a, t ₁ , a1) of REG1 is reset. Therefore, until the next data a, t ₂ , and a 2 are set in REG 1, the output = 0 of REG ₁ is not a contention target for the priority request at the slot timing t ₁ . As a result, next, the output data (b,
t ₁ , b1) is processed at high speed. The same applies to RE
G3, REG4 output data (c, t ₁ , c1),
(D, t ₁ , d1) is processed at high speed and buffered in the OBF 15.

Thus, eventually, the output highway,
At the slot timing t ₁ ′ for reading the data a ₁ ′, the data (a, t ₁ , a ₁ ′) is read from the OBF 15 by the data read control signal RCK, and is loaded on the bus 12. On the other hand, the DEC 17 uses the identification ID (= a,
t ₁ ) is decoded, whereby REG5
Is set, and the data a1 'portion is set in REG5. Hereinafter, similarly, the data b1
'To d1' are set in REG6 to REG8. The data a1 'to d1' of REG5 to REG8 are respectively set to P / S1 to P / S at the timing of the data transfer activation signal TXE '.
/ S4 are transferred to, and serially outputted to the output highway CH _{a'~CH d} 'by the clock signal SCK' system.

FIG. 3 is a timing chart of the signaling processing circuit according to the first embodiment. In slot timing t _1, data a1~d1 to be processed is latched simultaneously in REG1-REG4, thereby A
The operation energizing (event occurrence) signal EN of the LU 14 becomes EN = 1. The ALU 14 performs high-speed signaling processing of the data a1, and stores the data a1 in the OBF 15. Hereinafter, signaling processing of data b1 to d1 is sequentially performed at high speed, and OBF1
5 is stored. In this example, the slot timing t of the system at the point where the signaling processing of the data d1 has been completed is completed.
_1, but it is being finished, so that the process ends with a margin in the slot timing t ₁ when Maze the operation speed of the ALU 14. The same applies to the subsequent slot timings t ₂ and t ₃ .

At the slot timing t ₄ , the signaling processing for the network monitoring data a _{4 to} d ₄ is a more complicated operation than the previous one (for the subscriber), so that the processing time for each data is somewhat longer (the number of clocks). Is larger). Since the back of the slot timing t ₄ is available in this example even if according (for example, a normal voice data), ALU 14 can be processed over a long time data a ₄ to d _4, respectively properly.

Note that such slot timing t ₄
In some cases followed by a slot timing t ₅ that require treatment immediately after the, in such a case, as shown in FIG. 2, it may be provided an input Baaffa (IBF) 19. This IBF
Reference numeral 19 denotes a FIFO type buffer, which has an identification ID (a, t).
₄ ) and data a4 is stored. Therefore, IBF19
In, the slot timing t ₄ is data (a,
t ₄ , a 4) to (d, t ₄ , d 4) are sequentially held, and data (a, t ₅ , a ₅ ) to (d, t ₅ , d ₅ ) are sequentially held at the subsequent slot timing t _5. Is done. The ALU 14 processes the output data of the IBF 19 in order. In this case, for example, data (a,
_{t 4, a4) ~ (d} , t 4, even slot timing system while processing d4) transits to t ₄ → t _5, the processed data _{(a, t 4, a4)} ~ (d, t ₄ , d4) is properly processed according to the identification ID (= t ₄ ).

Thus, a predetermined time φ from the input frame
, An output frame is activated. At the slot timing t ₁ ′, the processing result data a
₁ ′ to d ₁ ′ are read out, and these are identification IDs.
Are distributed to REG5 to REG8 by P / S1
ＰP / S4 to CHa'〜CHd '. The same applies to the subsequent data a ₂ ′ to d ₄ ′.

FIG. 4 is a block diagram of a signaling processing circuit according to the second embodiment, in which the information of the slot timing t _i is deleted from the identification ID of FIG. In the figure, information on slot timing t _i is provided directly from the system to ALU 14 and MEM 18.
In this case, the ALU 14 needs to end processing of all data corresponding to the slot timing t _{i in} the section of the slot timing t _i , but as a result of deleting the information of the slot timing t _i from the identification ID, the circuit ( (LSI) The entire wiring pattern is simplified.

FIG. 5 is a block diagram of a signaling processing circuit according to the third embodiment, in which the PRU 13 generates processing data (event) a1 to generate processing result data a1.
By holding the reception highway information (= a) up to the output of ',
The figure shows a case where processing data of all highways can be processed at high speed by a single ALU 14. In the figure, O
BF1 to OBF4 are FIFO type output buffers provided for each output highway (port).

[0032] are converted serial signal a1~d1 within parallel data in a section of slot timing t _1,
REG1 at the timing of the subsequent data transfer energizing signal TXE
REG4. At this time, 1-bit data indicating that the data has been latched is also latched. Thereby, REG1 to REG4 are stored in PRU13.
The PRU 13 receives the priority request signals PRQ1 to PRQ4, and outputs PAK1 = 1, for example, according to a predetermined priority. The buffer circuit B1 is activated by PAK1 = 1, and places the output data a1 of REG1 on the data bus 11.

On the other hand, the ALU 14 has an OR gate circuit O1.
Is activated by PAK = 1 (event occurrence) at the output of
Signaling operation for input data a1 is performed at high speed. At this time, if necessary, reference data is read from the MEM 18 based on the information of the input highway number (= a) held by the PRU 13 and the slot timing t _i (= t ₁ ) managed by the system, and used for logical operation. . Thus, the output data a1 'is generated from the input data a1, and the data a1' is buffered in the OBF1 by the output PAK1 = 1 of the PRU13 at the timing of the processing end signal EOP. The processing end signal EOP is also input to the AND gate circuits A1 to A5, thereby resetting the data 1 and a1 of the REG1 which has been processed this time (that is, corresponding to PAK1 = 1). If necessary, the data a1 of the processing result of the ALU 14 is
M18 is written. Hereinafter, REG2 is performed in the same manner as above.
REG4 are processed at high speed and buffered in OBF2 to OBF4, respectively.
As described above, also in the third embodiment, the ALU 14
For the various calculation methods and the presence / absence of writing of the processing result data to the MEM 18, the highway number (PAK
_i ) and for each slot timing (t _i ). However, each processing data slot timing t _i are processed within slot timing t _i to be managed by the system.

In this manner, at the timing t ₁ ′ at which the data a ₁ ′ to d ₁ ′ are read out for the output highway, the data a ₁ ′ to d ₁ ′ are read out from the OBF ₁ to OBF 4 and transferred to the P / S 1 to P / S 4. It is serially outputted to the output highway (port) CH _{a'~CH d} '. Thus, according to the third embodiment, data to be processed on all highways can be efficiently and accurately processed without adding an identification ID to the processed data.

In each of the above embodiments, the output buffer (OBF15, OBF15) for storing the data of the operation result is stored.
BF1 to OBF4) and the parallel-serial converter P
Although the case where / S1 to P / S4 are provided in the LSI has been described,
Not limited to this. For example, as shown in FIG. 1, the data of each processing result may be directly distributed and stored in an output buffer provided in the main signal line.

Also, in each of the above embodiments, a case has been described in which a frame signal for four highways (ports) is processed using a single-ring processing circuit having a processing capability for a maximum of four ports. However, the present invention is not limited to this. . For example, using a single-ring processing circuit having a processing capacity of 8 ports, 4
It is possible to process frame signals for highways (ports). In this case, for example, highways 1 to 4 may be connected to ports 1 to 4 of the single-ring processing circuit, and ports 5 to 8 may be left empty. Even in such a case, since no processing target data is generated for the empty ports 5 to 8, each data of the input ports 1 to 4 is processed with a margin and output to the output ports 1 to 4. Thus, the signaling processing circuit (LSI) according to the present invention can flexibly cope with the signaling processing of various system configurations.

The identification ID to be added to the processing data may be any ID information as long as it can correspond to the highway number and the slot timing.

Instead of using the PRU 13, a scanner means for sequentially receiving the processing of the processing data existing in the REG1 to REG4 may be used.

In each of the above embodiments, the case where data processing is performed in units of 8 bits has been described. However, for example, it is also possible to configure so that data in units of 8 bits is divided into data in units of 4 bits and processed. is there. This can greatly reduce the number of LSI wirings.

Although a plurality of preferred embodiments of the present invention have been described, it is needless to say that various changes can be made in the configuration, control, and combination of these components without departing from the spirit of the present invention. Not even.

[0041]

As described above, according to the present invention, it is possible to flexibly cope with the signaling processing for an arbitrary number of highways (ports) with a simple circuit configuration, and to handle the increase or decrease in the number of subscribers (traffic). Efficient handling can be achieved without changing the configuration.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram of a signaling processing circuit according to the first embodiment.

FIG. 3 is a timing chart of the signaling processing circuit according to the first embodiment.

FIG. 4 is a block diagram of a signaling processing circuit according to a second embodiment.

FIG. 5 is a block diagram of a signaling processing circuit according to a third embodiment.

FIG. 6 is a diagram illustrating a conventional technique.

[Explanation of symbols]

 11, 12 Data bus 13 Priority unit (PRU) 14 Logical operation unit (ALU) 15 Output buffer (OBF) 16 Buffer control unit (BC) 17 Decoder (DEC) 18 Memory (MEM) 19 Input buffer (IBF) A AND Gate circuit B Buffer circuit O OR gate circuit OBF Output buffer P / S Parallel-serial converter REG register S / P Serial-parallel converter

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Takahiro Kaito 2-25 Ichibancho, Aoba-ku, Sendai-shi, Miyagi F-term in Fujitsu Tohoku Digital Technology Co., Ltd. (Reference) 5K028 EE09 KK01 KK03 MM08 MM12 MM13 MM14 SS24

Claims (6)

[Claims] 1. A signaling processing circuit for performing data processing such as monitoring, processing, and conversion of predetermined time-division multiplexed data on a highway, a data extracting means for extracting a plurality of data from a plurality of input highways, and a data extracting means. ID adding means for adding a different identification ID to each output data, data processing means for processing each output data of the ID adding means in a time-division manner, and output corresponding to each output data of the data processing means according to the identification ID. A signaling processing circuit comprising: a data distribution unit that distributes data to a highway. 2. The signaling processing circuit according to claim 1, wherein the ID adding means adds an identification ID corresponding to a highway to each output data of the data extracting means. 3. The signaling processing circuit according to claim 2, wherein said ID adding means further adds an identification ID corresponding to a time slot to each output data of said data extracting means. 4. The signaling processing circuit according to claim 1, further comprising an input buffer for storing each output data of the ID adding means together with its identification ID in chronological order. 5. The signaling processing circuit according to claim 1, further comprising an output buffer for storing each output data of the data processing means in time series together with its identification ID. 6. A signal processing circuit for performing data processing such as monitoring, processing, and conversion of predetermined time-division multiplexed data on a highway, a data extracting means for extracting a plurality of data from a plurality of input highways, and a data extracting means. Data selection means for selecting each output data in a time-division manner and holding highway information of the data until the processing of the selected data is completed, and data processing means for processing each selected data of the data selection means in time series. And a data distribution unit that distributes each output data of the data processing unit to a corresponding output highway according to the highway information held by the data selection unit.