JP2000223818A - Manufacture of multi-layered wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To effectively prevent an electrolytic plating layer from swelling and electrolytic plating layers from short-circuiting by improving the adhesiveness between an electroless plating layer formed on a roughened surface of the organic resin insulating layer of a wiring substrate and a plating resist layer formed on the electroless plating layer. SOLUTION: The surface of the organic resin insulating layer is roughened to Rz=X μm 10-point mean roughness (Rz) prescribed by JIS-B-0601 and on the organic resin insulating layer which is thus roughened, an electroless plating layer 4 of Y μm in thickness is formed. At this time, the thickness of the electroless plating layer is so set that Y <= X/3 and then the surface roughness of the electroless plating layer is equalized to that of the organic resin insulating layer. Consequently, sufficient adhesion between the plating resist and electroless plating layer is obtained to effectively prevent the plating resist layer from floating or peeling.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer wiring board having a wiring layer composed of, for example, an electroless plating layer and an electrolytic plating layer on a substrate surface.

[0002]

2. Description of the Related Art Conventionally, there has been known a multilayer wiring board formed by alternately laminating organic resin insulating layers and wiring layers on an insulating substrate, for example. When forming a wiring layer on the surface of an organic resin insulating layer, a method of forming a wiring layer on the roughened surface of the organic resin insulating layer by a semi-additive method is known. The method of forming a wiring layer by the semi-additive method mainly includes the following steps. An electroless plating layer is formed on the surface of the organic resin insulating layer by electroless plating. A plating resist layer having a predetermined pattern of openings is formed on the electroless plating layer. An electrolytic plating layer is formed by electrolytic plating on the electroless plating layer corresponding to the opening of the pattern. The plating resist layer is removed. A wiring layer is formed by etching and removing an unnecessary electroless plating layer corresponding to a portion where the plating resist layer has been removed.

Further, in this conventional multilayer wiring board, the organic resin insulating layer and the wiring layer, in particular, in the above-described semi-additive method, the organic resin insulating layer is formed in order to improve the adhesiveness with the electroless plating layer. The surface must be sufficiently roughened. Therefore, a method is adopted in which the surface of the organic resin insulating layer is sufficiently roughened in advance before forming the electroless plating layer, and electroless plating is performed thereon.

[0004]

When the surface of the organic resin insulating layer is sufficiently roughened and the thickness of the electroless plating layer is small, the electroless plating layer is formed of the organic resin insulating layer. Since it is formed following the undulation of the surface, the surface roughness on the electroless plating layer can be made substantially equal to the surface roughness of the organic resin insulating layer. Therefore, the adhesion between the plating resist layer and the electroless plating layer when forming the electrolytic plating layer is improved, and swelling of the electrolytic plating layer can be prevented.

On the other hand, even if the surface of the organic resin insulating layer is sufficiently roughened, if the thickness of the electroless plating layer formed thereon is large, the electroless plating layer is Is formed so as to level the undulations, so that the surface roughness of the upper surface thereof is reduced. If the surface of such an electroless plating layer does not have a sufficient roughness, the adhesion between the electroless plating layer and the plating resist layer attached thereon becomes poor. In such a case, for example, during the transfer of the substrate or the like, when it comes into contact with a transfer roller or the like, partial lifting or peeling may occur between the plating resist layer and the electroless plating layer. is there.

[0006] If there is such a floating or peeling, the electrolytic plating layer is formed also in a portion where the electrolytic plating layer should not be formed. The electrolytic plating layer thus formed is not sufficiently removed in a later etching step, and causes insulation failure or short circuit between wiring layers.

The present invention has been made in view of the above-mentioned drawbacks, and has as its object to provide a multilayer wiring board comprising an organic resin insulating layer and a wiring layer alternately laminated in a multilayer. The surface roughness on the layer is made equal to the surface roughness of the organic resin insulation layer, preventing floating and peeling of the plating resist layer, preventing the formation of unnecessary electrolytic plating layers, and furthermore, short-circuiting between wiring layers, etc. It is an object of the present invention to provide a multilayer wiring board in which desired characteristics can be sufficiently exhibited by preventing the above problems.

[0008]

According to a first aspect of the present invention, there is provided a method of manufacturing a multilayer wiring board comprising an organic resin insulating layer and a wiring layer alternately laminated on an insulating substrate. The surface roughness of the organic resin insulating layer is JIS-B-06
A roughening step of roughening to Rz = X μm with a ten-point average roughness (Rz) specified in No. 01, and forming an electroless plating layer having a thickness of Y μm on the upper surface of the roughened organic resin insulating layer by electroless plating. Forming, a step of forming a plating resist layer having an opening of a predetermined pattern on the electroless plating layer, and forming an electrolytic plating layer on the electroless plating layer corresponding to the opening of the pattern by electrolytic plating. Forming a;
Including a step of removing the plating resist layer, and an etching step of forming a wiring layer by removing an extra electroless plating layer corresponding to a place where the plating resist layer is removed, after the roughening step. The surface roughness (Rz = X μm) of the organic resin insulator layer and the thickness Y (μm) of the electroless plating layer
m) is a summary of a method for manufacturing a multilayer wiring board, wherein Y ≦ X / 3.

According to the present invention, a sufficiently thin electroless plating layer is formed on the surface of the organic resin insulating layer after the surface of the organic resin insulating layer is sufficiently roughened. The roughness of the upper surface of the electroless plating layer can be made equal to the roughness of the roughened organic resin insulating layer. Therefore, since the adhesion strength between the electroless plating layer and the plating resist layer is not reduced, the electrolytic plating layer can be accurately formed in a desired pattern. Therefore, it is possible to reliably prevent a defect such as a defective insulation or a short circuit between wiring layers formed thereafter.

The surface of the organic resin insulating layer may be roughened in a semi-cured organic resin precursor layer state without being completely cured. In this case, the organic resin insulating layer is easily roughened, and the roughness of the surface can be easily increased. If it is a degree of semi-curing, the organic resin precursor layer may be cured to a degree that can withstand the roughening treatment to some extent, and may be heated at a predetermined temperature for a predetermined time depending on the material of the organic resin. However, for example, heating may be performed at 70 ° C. to 180 ° C. for 0.5 to 2 hours.

Further, the invention according to claim 2 is characterized in that the thickness (μm) of the electroless plating layer satisfies 0.3 ≦ Y ≦ X / 3. The gist is the manufacturing method of

[0012] In the present invention, the thickness of the electroless plating layer is 0.1 mm.
Since it is 3 μm or more, the substrate surface can be reliably covered by electroless plating. Therefore, even if electrolytic plating is performed later, a pinhole is formed in the formed wiring layer (see FIG. 8).
Does not occur.

The material of the insulating substrate of the present invention is, for example, a glass epoxy resin obtained by impregnating a glass fiber woven cloth with an epoxy resin, or an oxide-based material such as an aluminum oxide-based sintered product or a mullite-based sintered product. Ceramic, or aluminum nitride sintered body having an oxide film on the surface,
It is made of an electrically insulating material such as a non-oxide ceramic such as a silicon carbide sintered body. Alternatively, a metal substrate whose surface is coated with an insulating resin or the like can be used. Note that the invention is not limited thereto, and a known insulating material can be used as appropriate.

As a material of the plating resist layer of the present invention, for example, a photosensitive resin such as a photosensitive epoxy resin is preferable. That is, by performing a process such as exposure and development on the photosensitive resin, a resist pattern having a desired opening, that is, a so-called negative pattern that forms a periphery of a wiring pattern to be formed can be formed.

As a method of disposing the photosensitive resin on the substrate surface, a method of applying the photosensitive resin by screen printing or spin coating, or a method of attaching a photosensitive film made of the photosensitive resin can be adopted.

The type of the wiring layer includes a wiring layer made of a conductive metal such as copper, aluminum, nickel, gold, and silver. It is composed of the metal used. Further, it is also possible to form the wiring layer by changing the metal according to the application, such as using copper for the long distance wiring layer and aluminum for the short distance wiring layer. Further, for example, the metal can be changed depending on the layer, for example, a wiring layer is formed of copper as the uppermost layer and a wiring layer is formed of aluminum as the inner layer.

Further, when performing the electroless plating,
As a pretreatment, a method of attaching growth nuclei (Pd, Au, etc.) of electroless plating to a portion where an electroless plating layer is to be formed, that is, to the surface of the organic resin insulating layer can be adopted.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. In the method for manufacturing a multilayer wiring board according to the present embodiment, as shown in FIGS. 1 to 6, the wiring layer 7 is formed by a semi-additive method to manufacture the multilayer wiring board 1. First, the laminated substrate 2 shown in FIG. 1 is prepared in advance. The laminated substrate 2 first forms through holes that penetrate the front and back surfaces (upper and lower surfaces in the figure) of a substantially plate-shaped core substrate 11 made of glass epoxy. Subsequently, the wiring layer 12 is formed on the inner peripheral surface of the through hole and the front and back surfaces of the core substrate 11 by a known method, and then the resin is filled in the through hole. Then, on the wiring layer 12 and the core substrate 11,
The organic resin precursor layers 30 and 140 made of an epoxy resin (Provicoat: trade name, manufactured by Nippon Paint Co., Ltd.) previously formed in a film shape are attached to the film.

Next, the organic resin precursor layers 30, 14
After performing a heat treatment at 80 ° C. for 15 minutes, a mask (not shown) is provided for exposure, and then a further 45 ° C. at 80 ° C.
A heat treatment is performed for a minute to obtain a semi-cured state. Furthermore, the semi-cured organic resin precursor layers 30, 140 are developed to form a plurality of via holes 13 for forming via conductors in the organic resin insulating precursor layers 30, 140, and a drying step is performed. After that, the laminated substrate 2 is formed.

The development process for forming the via hole 13 is performed with the substrate held horizontally. In this case, for example, the via hole is not formed in an irregular shape unlike the case where the via hole is held vertically, but is formed well in the vertical direction (depth direction) with respect to the substrate surface. However, when the development is performed while being held horizontally, there is a slight difference in the progress of the development between the upper surface and the lower surface of the substrate. That is, the developer S, the melted-out resin and the like easily accumulate on the upper surface of the substrate,
It is difficult to supply a new developing solution S to the bottom of the via hole being formed (see FIG. 7).

On the other hand, on the lower surface, the old developing solution S, the melted resin and the like are immediately removed by gravity, and a new developing solution S is always supplied to the bottom surface of the via hole being formed. In order to prevent such a variation in the progress of development between the upper surface and the lower surface, at least one
It is preferable that the upper and lower surfaces of the round substrate are inverted. This upper and lower surface inversion step may be performed a plurality of times, but in order to uniformly develop the upper and lower surfaces, an odd number of inversions is preferable. Further, it is more preferable to change the left and right directions and the like at the same time as the inversion of the upper and lower surfaces because variation in the contact of the developer S can be prevented.

FIG. 2A is a partially enlarged view of the organic resin precursor layer 30 formed on the upper side in the drawing of the substrate 2 to be laminated. Next, as shown in FIG. 2B, in a roughening step, the surface 30A of the organic resin precursor layer 30 is roughened using a solution containing potassium permanganate. Since the organic resin precursor layer 30 is not completely cured and is in a semi-cured state, it can be roughened very well. The surface roughness of the surface 30A of the organic resin precursor layer 30 after roughening is determined according to JIS-
Rz = about 3 μm at a ten-point average roughness (Rz) specified in B-0601. Although not shown here, the inner wall of the via hole 13 is also roughened at the same time. Since the semi-cured organic resin precursor layer 30 is subjected to the roughening treatment in this manner, the adhesion strength to the wiring layer and the organic resin insulating layer disposed thereon due to the anchor effect is increased.

Next, electroless copper plating is performed, and FIG.
As shown in FIG. 1, an electroless plating layer 4 having a thickness of 0.7 μm is formed. The thickness of the electroless plating layer 4 is sufficiently smaller than the ten-point average roughness (Rz = 3 μm) of the surface 30A of the organic resin precursor layer 30. Asperities similar to the surface 30A of the layer 30 are obtained. Although not shown here, the electroless plating layer 4 is also formed on the inner wall of the via hole 13 and the surface of the wiring layer 12 exposed on the bottom surface of the via hole 13. Also,
The thickness of the electroless plating layer is 0.3 μm or more and 0.7
Since the thickness is set to μm, almost the entire surface of the organic resin precursor layer 30 can be covered, and there is no partial loss of the electroless plating layer (pinhole) unlike the case where the thickness is set to less than 0.3 μm.

Next, a dry film is adhered to the surface 4A of the electroless plating layer 4, exposed and developed using a predetermined pattern, and a resist film is formed at a place where no wiring layer is formed as shown in FIG. 5 is formed. Thereafter, electrolytic plating is performed to form an electrolytic plating layer 6 having a thickness of 20 μm on the surface 4A of the electroless plating layer 4 exposed from the resist film 5, as shown in FIG. After the formation of the electrolytic plating layer 6, the resist film 5 is peeled off with a strong alkali (NaOH aqueous solution).

Here, a heat treatment is performed at 150 ° C. for 120 minutes. By this heat treatment, the organic resin precursor layer 30 is completely cured and becomes the organic resin insulator layer 3 (complete curing step). Next, a sodium sulfate-based etchant is sprayed onto the exposed electroless plating layer 4 and the electrolytic plating layer 6 to perform etching for 90 seconds (quick etching step), and as shown in FIG. Unnecessary electroless plating layer 4 is removed to form wiring layers 7,7.

Since the thickness of the electroless plating layer 4 is sufficiently reduced to 0.7 μm, which is 0.9 μm or less, the time required for etching the electroless plating layer 4 can be shortened. There is no excessive etching. Therefore, the width and the thickness of the wiring layer 7 are not extremely reduced, so that the resistance value of the wiring layer 7 does not increase and the wiring layer 7 is not disconnected.

Since the heat treatment for completely curing the organic resin precursor layer 30 is performed after forming the electroless plating layer 6, the electroless plating layer 4 is also heat-treated. Thereby, the etching rate of the electroless plating layer 4 becomes substantially uniform in the laminated substrate 2. Therefore, insufficient etching does not occur locally. Further, since the heat treatment is performed after the electrolytic plating layer 6 is formed,
The electrolytic plating layer 6 is also heat-treated. Therefore, the electrolytic plating layer 6 is not locally over-etched. This is presumably because the heat treatment makes the arrangement of the metal particles (copper particles) of the electroless plating layer 4 and the electrolytic plating layer 6 uniform, thereby making the etching rate uniform.

However, during the step of etching the electroless plating layer 4, a residue 4B may remain on the organic resin insulating layer 3. This is subjected to resin etching at 80 ° C. for 1 minute with a resin etching solution containing potassium permanganate, and as shown in FIG. 4B, the surface layer of the organic resin insulating layer 3 exposed between the wiring layers 7, 7. The portion is resin etched to a depth of 4 μm. By this resin etching, the residue 4B of the electroless plating layer 4 can be removed.

Further, in the above description, since the resin etching depth is set to 1 μm or more and 4 μm, unnecessary residues 4 B of the electroless plating layer 4 which cause a leak failure can be surely removed. Further, since the resin is etched only by 4 μm of 7 μm or less, the organic resin insulating layer 3 is not greatly etched, so that the adhesion strength between the organic resin insulating layer 30 and the wiring layer 7 can be maintained high. Since the surface roughness of the organic resin insulating layer 3 between the wiring layers 7 and 7 does not significantly decrease, the adhesion strength between the organic resin insulating layer 3 and an organic resin insulating layer to be laminated thereon later is also kept high. be able to.

Further, since the resin etching solution containing potassium permanganate is used, the surface 3A of the organic resin insulating layer 3 can be appropriately etched with the resin, and the adjustment thereof is easy. The semi-cured organic resin precursor layer 30
Since the resin is etched using the same liquid as the roughened liquid, the roughened state after the resin etching is close to that before the resin etching, so that a good roughened state can be maintained.

Next, in the roughening step of the wiring layer, blackening treatment is performed with a mixed solution of sodium chlorite, sodium hydroxide and trisodium phosphate, and as shown in FIG. 7A is oxidized and roughened. By this roughening step (blackening treatment), the adhesion strength between the wiring layer 7 and an organic resin insulating layer to be laminated thereon later can be increased.

Next, as shown in FIG.
A film-like organic resin precursor made of the same resin as the organic resin insulating layer 3 is adhered on the organic resin insulating layer 3 and heated at 80 ° C. for 15 minutes to form the organic resin precursor layer 80. I do. In addition, if necessary, the organic resin precursor layer 80 is exposed to a predetermined pattern,
After the heat treatment for a minute, development is performed to form a via hole (not shown). A via conductor is formed in the via hole by plating or the like, and the wiring layer 7 and the wiring layer thereover can be electrically connected via the via conductor.

Next, the surface 80A of the organic resin precursor layer 80
Is roughened as shown in FIG. Thereafter, the above steps are repeated to form a wiring layer 9 as shown in FIG. 6, and further a solder resist layer 10 and the like are formed thereon to complete the multilayer wiring board 1. Although not described, the wiring layers 15, 17, the organic resin insulating layer 16, and the solder resist layer 18 shown in the lower part of the figure in the multilayer wiring board 1 are also formed in the same manner as described above.
Further, the organic resin precursor layer 80 becomes the organic resin insulating layer 8 by being completely cured in the above manufacturing process.

As described above, according to the manufacturing method of the present embodiment, the surface roughness of the organic resin precursor layer 30 (organic resin insulating layer 3) is Rz = 3 μm in ten-point average roughness (Rz). On the other hand, since the electroless plating layer 4 has a sufficiently thin thickness of 0.7 μm, the surface of the electroless plating layer has a ten-point average roughness (R
z) was equivalent to the ten-point average roughness (Rz) of the surface of the organic resin precursor layer 30 (organic resin insulating layer 3).
Therefore, the plating resist layer 5 formed on the electroless plating layer 4 later did not peel off or float. Therefore, the electrolytic plating layer 6 can be accurately formed in accordance with the pattern (opening) formed in the plating resist layer 5, and a desired wiring layer 7 can be formed.

The thickness of the electroless plating layer is 0.5 μm.
In the case of m and 0.9 μm, the plating resist layer 5 did not peel off or float as in the case of the above embodiment, and a desired wiring layer could be formed. On the other hand, the thickness of the electroless plating layer was set to 1.2 μm, 1.6 μm, 2.0 μm.
In the case of m, the plating resist layer was peeled or floated in the substrate transporting step, and the wiring layer was swollen or short-circuited.

Further, the surface roughness of the organic resin precursor layer (organic resin insulating layer) of the electroless plating layer is determined by calculating the ten-point average roughness (Rz).
When Rz = 5 μm, the thicknesses of the electroless plating layers are 0.5 μm, 0.7 μm and 0.9 μm, respectively.
In any of the cases of m, 1.2 μm, and 1.6 μm, the desired wiring layer could be formed without peeling or lifting of the plating resist layer as in the above embodiment. On the other hand, the thickness of the electroless plating layer was set to 1.
In the case of 8 μm and 2.0 μm, the plating resist layer was peeled or floated in the substrate transfer step, and the wiring layer was swollen or short-circuited.

As described above, the ten-point average roughness (Rz = X μm) of the surface of the organic resin insulator layer after the roughening step and the thickness Y (μm) of the electroless plating layer satisfy Y ≦ X / 3. In the case of, the desired wiring layer can be formed without peeling or floating of the plating resist layer in the substrate transfer step, but in the case of Y> X / 3, the plating resist layer is peeled. It can be seen that a floating occurs and a swelling or short circuit occurs in the wiring layer.

Further, since the organic resin precursor layer is roughened in a semi-cured state, it is sufficiently roughened, and the surface roughness in the substrate has little variation.
Sufficient adhesion strength to the wiring layer is obtained. Further, in the above embodiment, when the wiring layer is formed by the so-called semi-additive method, after forming the electroless plating layer, since the heat treatment for completely curing the organic resin precursor layer is performed, Variations in the etching rate within the substrate in the step of etching the electroless plating layer can be eliminated. This is presumed that the heat treatment makes the arrangement of the metal particles in the electroless plating layer uniform and also makes the etching rate uniform.

When the wiring layer is formed, quick etching is insufficient, and unnecessary residues 4B of the electroless plating layer 4 are completely removed on the organic resin insulating layer 3 between the wiring layers 7, 7. Even if it remains, it can be removed by a resin etching step thereafter. Therefore, it is possible to manufacture a highly reliable multilayer wiring board 1 in which no leak failure occurs between the wiring layers 7 (see FIG. 6).

In the above, the present invention has been described in accordance with the respective embodiments. However, it is needless to say that the present invention is not limited to the above embodiments, and can be appropriately modified and applied without departing from the gist thereof. Absent.

[0041]

According to the method for manufacturing a multilayer wiring board of the present invention, the organic resin insulation whose surface roughness is roughened to Rz = X μm with ten-point average roughness (Rz) specified in JIS-B-0601. On the upper surface of the layer, an electroless plating layer having a thickness of Y μm is formed by electroless plating, and when Y ≦ X / 3, the ten-point average roughness (Rz) of the surface of the electroless plating layer is also ,
Since the surface roughness of the organic resin insulating layer can be made equal to the ten-point average roughness (Rz), floating and peeling of the plating resist layer can be effectively prevented. Therefore, swelling of the wiring layer and short circuit between the wiring layers can be prevented.

Further, the thickness of the electroless plating layer is set to 0.3 μm.
Since it is set to m or more, defects such as pinholes do not occur, and the electrolytic plating layer is formed favorably.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a laminated substrate according to an embodiment of the present invention.

2A and 2B are diagrams illustrating a method for manufacturing a multilayer wiring board according to an embodiment of the present invention, wherein FIG. 2A is a partially enlarged view of an organic resin precursor layer of a substrate to be laminated, and FIG. 1 shows a state in which the surface of a body layer is roughened.

3A and 3B are diagrams illustrating a method for manufacturing a multilayer wiring board according to an embodiment of the present invention, wherein FIG. 3A illustrates a state in which an electroless plating layer is formed, and FIG. 3B illustrates a state in which a plating resist layer is formed. And (c) shows a state in which an electrolytic plating layer is formed.

4A and 4B are diagrams illustrating a method of manufacturing a multilayer wiring board according to an embodiment of the present invention, wherein FIG. 4A illustrates a state in which a wiring layer is formed, and FIG. 4B illustrates a surface portion of an organic resin insulating layer between wiring layers; And (c) shows a state where the surface of the wiring layer is roughened.

5A and 5B are diagrams showing a method for manufacturing a multilayer wiring board according to an embodiment of the present invention, wherein FIG. 5A shows a state in which organic resin insulating layers are stacked, and FIG. This shows a roughened state.

FIG. 6 is a sectional view of a multilayer wiring board according to the embodiment of the present invention.

FIG. 7 is an explanatory diagram illustrating a developing process in a state where the substrate is held horizontally.

FIG. 8 is an explanatory view showing a pinhole in a conventional substrate.

[Explanation of symbols]

 1: multilayer wiring board 2: laminated substrate 30, 80: organic resin precursor layer 3: organic resin insulating layer 4: electroless plating layer 5: plating resist layer 6: electrolytic plating layer 7: wiring layer

Continued on the front page (72) Inventor Naoki Kito 14-18, Takatsuji-cho, Mizuho-ku, Nagoya City, Aichi Prefecture Inside Japan Special Ceramics Co., Ltd. (72) Inventor Satoshi Hirano 14-18, Takatsuji-cho, Mizuho-ku, Nagoya City, Aichi Prefecture Sun F-term (reference) in this special ceramic company 5E343 AA07 AA15 AA17 AA22 AA24 BB14 BB23 BB24 BB25 BB28 BB44 CC73 DD33 DD43 ER16 ER18 ER26 GG02 5E346 AA12 AA32 AA54 CC32 CC34 CC37 CC39 CC54 DD23 DD24 EE33 H

Claims (2)

[Claims] 1. A method for manufacturing a multilayer wiring board comprising alternately laminating organic resin insulating layers and wiring layers on an insulating substrate, wherein the surface roughness of the organic resin insulating layer is specified in JIS-B-0601. And a step of forming an electroless plating layer having a thickness of Y μm on the upper surface of the roughened organic resin insulating layer by electroless plating. And forming a plating resist layer having an opening of a predetermined pattern on the electroless plating layer, and on the electroless plating layer corresponding to the opening of the pattern,
Forming a wiring layer by forming an electrolytic plating layer by electrolytic plating, removing the plating resist layer, and removing an extra electroless plating layer corresponding to a portion from which the plating resist layer has been removed. An etching step; and a surface roughness (Rz = Xμ) of the organic resin insulator layer after the roughening step.
m) and the thickness Y (μm) of the electroless plating layer, Y ≦ X /
3. A method for manufacturing a multilayer wiring board, which is characterized in that: 2. The thickness (μm) of the electroless plating layer is as follows:
2. The method according to claim 1, wherein 0.3 ≦ Y ≦ X / 3.