JP2000223814A - Mounting board for wiring board - Google Patents

Mounting board for wiring board

Info

Publication number
JP2000223814A
JP2000223814A JP11020707A JP2070799A JP2000223814A JP 2000223814 A JP2000223814 A JP 2000223814A JP 11020707 A JP11020707 A JP 11020707A JP 2070799 A JP2070799 A JP 2070799A JP 2000223814 A JP2000223814 A JP 2000223814A
Authority
JP
Japan
Prior art keywords
wiring
circuit board
package
board
external electric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11020707A
Other languages
Japanese (ja)
Inventor
Yasuhide Tami
保秀 民
Masahiko Azuma
昌彦 東
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP11020707A priority Critical patent/JP2000223814A/en
Publication of JP2000223814A publication Critical patent/JP2000223814A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To hold a secure and tight electric connection for a long period by eliminating a defect in connection between a wiring board and an external electric circuit board. SOLUTION: When a package A which has a container for storing a semiconductor element 5 on an insulating substrate 1 made of ceramic and connection terminals 4 formed on the reverse surface is mounted on a circuit board B, a wiring conductor 9 between wiring conductors 8 and 9 adhered onto the top surface of an insulator 7 made of a composite material of glass and synthetic resin is arranged in a recessed part 10 of the circuit board B.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はガラスと合成樹脂と
の複合材からなる絶縁板からなる外部電気回路基板の上
に配線基板、とくに大型の表面実装型の配線基板をロウ
付けし実装する場合に適した配線基板の実装構造に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a case where a wiring board, especially a large surface-mounting wiring board is brazed and mounted on an external electric circuit board made of an insulating plate made of a composite material of glass and synthetic resin. The present invention relates to a mounting structure of a wiring board suitable for the above.

【0002】[0002]

【従来の技術】配線基板は絶縁基板の表面あるいは内部
にメタライズ配線層が配設された構造であり、代表例と
して半導体素子、とくにLSI(大規模集積回路素子)
等の半導体集積回路素子を収容するための半導体素子収
納用パッケージがある。
2. Description of the Related Art A wiring board has a structure in which a metallized wiring layer is disposed on the surface or inside of an insulating substrate. A typical example is a semiconductor element, particularly an LSI (Large Scale Integrated Circuit Element).
There is a semiconductor device housing package for housing a semiconductor integrated circuit device such as the above.

【0003】この半導体素子収納用パッケージは、一般
にアルミナセラミックスからなる絶縁基板の表面に半導
体素子を収容するための穴部が形成され、さらに絶縁基
板の表面および内部には、タングステン、モリブデン等
の高融点金属粉末からなる複数のメタライズ配線層が配
設され、穴部内に収納される半導体素子と電気的に接続
される。また、絶縁基板の下面または側面には、外部電
気回路基板と電気的に接続するための接続端子が備えら
れ、この接続端子は、メタライズ配線層と電気的に接続
されている。
[0003] In this package for housing a semiconductor element, a hole for accommodating a semiconductor element is formed on the surface of an insulating substrate generally made of alumina ceramics, and the surface and the inside of the insulating substrate are made of tungsten, molybdenum or the like. A plurality of metallized wiring layers made of a melting metal powder are provided, and are electrically connected to a semiconductor element housed in the hole. In addition, a connection terminal for electrically connecting to an external electric circuit board is provided on a lower surface or a side surface of the insulating substrate, and the connection terminal is electrically connected to the metallized wiring layer.

【0004】かかる半導体素子収納用パッケージ(以
下、半導体素子収納用パッケージをパッケージと略す
る)は、絶縁基板下面または側面に設けられた接続端子
と、外部電気回路基板表面に形成された配線導体とを半
田等によりロウ付けし電気的に接続することで、実装さ
れる。
[0004] Such a semiconductor element storage package (hereinafter, the semiconductor element storage package is abbreviated as a package) includes connection terminals provided on the lower surface or side surfaces of the insulating substrate and wiring conductors formed on the surface of the external electric circuit substrate. Are mounted by soldering with solder or the like and electrically connecting them.

【0005】一般に、半導体素子の集積度が高まるほ
ど、半導体素子に形成される電極数も増大するが、これ
に伴いパッケージにおける端子数も増大する。さらにパ
ッケージ自体の寸法も大きくする必要がある。しかしな
がら、小型化も要求されるため接続端子の密度を高くし
ている。
In general, as the degree of integration of a semiconductor device increases, the number of electrodes formed on the semiconductor device also increases, and accordingly, the number of terminals in a package also increases. Further, the dimensions of the package itself must be increased. However, since miniaturization is also required, the density of connection terminals is increased.

【0006】これまでのパッケージにおける接続構造と
しては、パッケージの下面にコバールなどの金属ピンを
接続したピングリッドアレイ(PGA)が最も一般的で
あるが、表面実装型のパッケージとして、パッケージの
側面に導出されたメタライズ配線層にL字状の金属部材
がロウ付けされたクワッドフラットパッケージ(QF
P)、パッケージの4つの側面に電極パッドを備えたリ
ードピンのないリードレスチップキャリア(LCC)、
さらに絶縁基板の下面に半田からなる球状端子を配設し
たボールグリッドアレイ(BGA)等があり、これらの
中でもBGAがもっとも高密度化が可能である。
The most common connection structure in a conventional package is a pin grid array (PGA) in which metal pins such as Kovar are connected to the lower surface of the package. Quad flat package (QF) in which an L-shaped metal member is brazed to the derived metallized wiring layer
P), leadless leadless chip carrier (LCC) with electrode pads on four sides of the package,
Further, there is a ball grid array (BGA) or the like in which a spherical terminal made of solder is arranged on the lower surface of the insulating substrate. Among these, the BGA can achieve the highest density.

【0007】このBGAでは、接続端子に半田などのロ
ウ材からなる球状体をロウ付けした構成であって、この
球状体を外部電気回路基板の配線導体上に当接させ、し
かる後、約250〜400℃の温度にて加熱溶融し、球
状体を配線導体に接合させることで外部電気回路基板上
に実装している。
This BGA has a structure in which a spherical body made of a brazing material such as solder is brazed to a connection terminal, and this spherical body is brought into contact with a wiring conductor of an external electric circuit board, and then about 250 mm. It is mounted on an external electric circuit board by heating and melting at a temperature of about 400 ° C. and joining the spherical body to a wiring conductor.

【0008】このような実装構造においては、パッケー
ジの内部に収容されている半導体素子の各電極がメタラ
イズ配線層および接続端子を介して外部電気回路に電気
的に接続される。
In such a mounting structure, each electrode of the semiconductor element housed in the package is electrically connected to an external electric circuit via the metallized wiring layer and the connection terminal.

【0009】また、パッケージをなす絶縁基板には、低
温焼成化、低誘電率化および高電気伝導性の銅配線化と
いう点で、ガラスセラミックス焼結体により構成する技
術が提案されている。
[0009] Further, there has been proposed a technology for forming an insulating substrate of a package using a glass ceramic sintered body from the viewpoint of low-temperature firing, low dielectric constant, and high electrical conductivity copper wiring.

【0010】[0010]

【発明が解決しようとする課題】前記絶縁基板を構成す
るセラミックスとしてアルミナ、ムライトなどが多用さ
れ、これにより、200MPa以上の高強度が達成さ
れ、メタライズ配線層などとの多層化技術に対し高い信
頼性が得られる。
Alumina, mullite, and the like are frequently used as ceramics constituting the insulating substrate. As a result, a high strength of 200 MPa or more is achieved, and high reliability is obtained with respect to the technology of forming a multilayer with a metallized wiring layer. Property is obtained.

【0011】しかしながら、この絶縁基板をガラス−エ
ポキシ樹脂複合材料、ガラス−ポリイミド樹脂複合材料
などの有機樹脂を含むプリント基板などの外部電気回路
基板に実装した場合には、外部電気回路基板と絶縁基板
との熱膨張係数差が10×10-6/℃以上と大きくな
り、そのために半導体素子の作動時に発生する熱が絶縁
基板と外部電気回路基板の両方に繰り返し印加されるこ
とで、熱応力が生じる。
However, when this insulating substrate is mounted on an external electric circuit board such as a printed circuit board containing an organic resin such as a glass-epoxy resin composite material or a glass-polyimide resin composite material, the external electric circuit board and the insulating substrate Is larger than 10 × 10 −6 / ° C., and the heat generated during the operation of the semiconductor element is repeatedly applied to both the insulating substrate and the external electric circuit board, thereby reducing the thermal stress. Occurs.

【0012】パッケージに設けた接続端子が300個未
満程度に比較的少ない場合には、熱応力も小さいが、接
続端子が300個以上になる程度まで大型になると、熱
応力も増大し、そのため、半導体素子の作動/停止のサ
イクルによりパッケージの接続端子の外周部ならびにこ
の接続端子と外部電気回路基板の配線導体との接合界面
に応力が集中し、接続端子が絶縁基板より剥離したり、
接続端子が外部電気回路基板の配線導体から剥離し、そ
の結果、パッケージの接続端子を外部電極回路の配線導
体に長期にわたり安定して電気的接続できないという課
題があった。
When the number of connection terminals provided on the package is relatively small, such as less than about 300, the thermal stress is small. However, when the number of connection terminals is increased to about 300 or more, the thermal stress increases. Due to the cycle of operation / stop of the semiconductor element, stress concentrates on the outer peripheral portion of the connection terminal of the package and the bonding interface between the connection terminal and the wiring conductor of the external electric circuit board, and the connection terminal peels from the insulating substrate,
The connection terminal peels off from the wiring conductor of the external electric circuit board, and as a result, there is a problem that the connection terminal of the package cannot be stably and electrically connected to the wiring conductor of the external electrode circuit for a long time.

【0013】したがって、本発明の目的はパッケージ等
の配線基板を外部電気回路基板にロウ付けでもって表面
実装するに際し、長期間にわたって強固にかつ安定して
接続させ、これによって高信頼性の配線基板の実装構造
を提供することにある。
Accordingly, an object of the present invention is to provide a reliable and stable connection for a long period of time when a wiring board such as a package is surface-mounted by brazing to an external electric circuit board. The object of the present invention is to provide a mounting structure.

【0014】[0014]

【課題を解決するための手段】本発明は、メタライズ配
線層が配設されたセラミック絶縁基板の一面に接続端子
群を形成した配線基板を、ガラスと合成樹脂との複合材
からなる絶縁板上に配線導体群が被着形成された外部電
気回路基板上に載置するに当たって、配線基板の接続端
子群を外部電気回路基板の配線導体群に個別にロウ付け
した実装構造において、前記配線導体の一部を、絶縁板
に形成した凹部内に設けて、接続端子と配線導体との間
隔を他の配線導体に比べ長くしたことを特徴とする。
SUMMARY OF THE INVENTION The present invention is directed to a method of forming a wiring board having a connection terminal group formed on one surface of a ceramic insulating substrate provided with a metallized wiring layer on an insulating plate made of a composite material of glass and synthetic resin. In mounting the wiring conductors on the external electric circuit board on which the wiring conductors are attached, the connection terminals on the wiring board are individually brazed to the wiring conductors on the external electric circuit board. A part is provided in a concave portion formed in the insulating plate, and a distance between the connection terminal and the wiring conductor is made longer than other wiring conductors.

【0015】[0015]

【発明の実施の形態】以下、本発明を図1〜図5によっ
て詳細に説明する。図1は前記配線基板であるBGA型
半導体素子収納用パッケージAを外部電気回路基板Bに
実装した構造の断面図、図2は外部電気回路基板Bの配
線導体群の配列を示す平面図である。図3〜図5は他の
外部電気回路基板B1、B2、B3の配線導体群の配列
を示す平面図である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to FIGS. FIG. 1 is a cross-sectional view of a structure in which a BGA type semiconductor element housing package A as the wiring board is mounted on an external electric circuit board B, and FIG. 2 is a plan view showing an arrangement of wiring conductor groups of the external electric circuit board B. . 3 to 5 are plan views showing the arrangement of the wiring conductor groups of the other external electric circuit boards B1, B2, B3.

【0016】BGA型半導体素子収納用パッケージA
(以下、パッケージAと略記する)は、セラミックスか
らなる絶縁基板1の上に大きな穴部を設けて、半導体素
子5が収納される容器6をなし、その上に蓋体2を配設
して気密封止する。さらに絶縁基板1の内部もしくは表
面にメタライズ配線層3を形成し、その一端が絶縁基板
1の下面に形成されたほぼ円形状の接続端子4と通電さ
れる。接続端子4はCu、Au、Al、Ni、Pb−S
n等の金属からなる。a、bは球状体もしくはフットボ
ール状の高融点半田などのロウ材である。また、穴部で
もって半導体素子5が収納される容器6をなし、さらに
蓋体2により気密封止する。
BGA type semiconductor element storage package A
(Hereinafter, abbreviated as package A) is provided by forming a large hole on an insulating substrate 1 made of ceramics to form a container 6 in which a semiconductor element 5 is housed, and disposing a lid 2 thereon. Hermetically seal. Further, a metallized wiring layer 3 is formed inside or on the surface of the insulating substrate 1, and one end thereof is electrically connected to a substantially circular connection terminal 4 formed on the lower surface of the insulating substrate 1. The connection terminal 4 is made of Cu, Au, Al, Ni, Pb-S
n. a and b are brazing materials such as high-melting solders in the form of a ball or a football. The hole forms a container 6 in which the semiconductor element 5 is housed, and is hermetically sealed by the lid 2.

【0017】外部電気回路基板B(以下、回路基板Bと
略記する)については、プリント基板などで構成する。
すなわち、ガラス−エポキシ樹脂、ガラス−ポリイミド
樹脂複合体などのガラスと合成樹脂との複合材からなる
絶縁体7の表面にCu、Au、Al、Ni、Pb−Sn
等の金属からなるほぼ円板状の配線導体8、9を被着形
成し、配線導体9は回路基板Bの周囲付近に位置するほ
ぼ円筒状の凹部10内に配設したものであって、その他
の配線導体8に比べ、配設部位を低くしている。そし
て、ロウ材aは配線導体8に、ロウ材bは配線導体9に
配置する。
The external electric circuit board B (hereinafter abbreviated as circuit board B) is constituted by a printed board or the like.
That is, Cu, Au, Al, Ni, Pb-Sn are formed on the surface of the insulator 7 made of a composite material of glass and a synthetic resin such as a glass-epoxy resin or a glass-polyimide resin composite.
A substantially disk-shaped wiring conductor 8, 9 made of a metal such as a metal is adhered and formed, and the wiring conductor 9 is disposed in a substantially cylindrical concave portion 10 located near the periphery of the circuit board B. The arrangement portion is lower than the other wiring conductors 8. The brazing material a is arranged on the wiring conductor 8, and the brazing material b is arranged on the wiring conductor 9.

【0018】凹部10はその内径が接続端子4の外径
(パッド径)に対し60〜160%、さらには80〜1
40%の比率になるように構成するとよく、好適には9
0〜130%、最適には100〜120%にするとよ
く、これにより、ロウ付けによる接続強度がもっとも大
きくなる。この比率が60%未満である場合には、配線
導体8、9に対するロウ材a、bの接触面積が小さくな
り、双方間での熱膨張係数差に起因した断線が生じやす
い。他方、160%を超えると、隣接する配線導体8
間、あるいは配線導体8と配線導体9との間でのスペー
スが小さくなり、狭くなることで、配線の引き回しが困
難となりやすい。
The inner diameter of the recess 10 is 60% to 160% of the outer diameter (pad diameter) of the connection terminal 4, and more preferably 80% to 1%.
It may be configured to have a ratio of 40%, preferably 9%.
It is good to be 0-130%, optimally 100-120%, so that the connection strength by brazing becomes the largest. If this ratio is less than 60%, the contact areas of the brazing materials a and b with the wiring conductors 8 and 9 become small, and disconnection due to a difference in thermal expansion coefficient between the two tends to occur. On the other hand, if it exceeds 160%, the adjacent wiring conductors 8
Since the space between the wiring conductors or between the wiring conductor 8 and the wiring conductor 9 is reduced and narrowed, it is likely to be difficult to route the wiring.

【0019】また、凹部10の深さは接続端子4のパッ
ド径に対し5〜125%、さらには10〜100%の範
囲に設定するとよく、好適には20〜90%、最適には
30〜70%がよく、これにより、ロウ付けによる接続
強度がもっとも大きくなる。
The depth of the recess 10 may be set in the range of 5% to 125%, more preferably 10% to 100%, preferably 20% to 90%, and most preferably 30% to 100% of the pad diameter of the connection terminal 4. 70% is preferable, whereby the connection strength by brazing is maximized.

【0020】つぎにパッケージAの回路基板Bに対する
実装方法を記載する。回路基板Bの凹部10内に、さら
には絶縁体7の所定部位の上に配線導体8、9を形成
し、これら配線導体8、9上にクリーム状の低融点半田
を印刷により塗布し、他方のパッケージAにおいても絶
縁基板1上に接続端子4を形成し、その上にクリーム状
の低融点半田を印刷により塗布し、さらにその上に高融
点半田からなる球状半田を載置し、180〜250℃の
温度で加熱し、球状半田をパッケージA上に固定する。
ついでパッケージAを回路基板B上に載置する。この載
置に際し、個々の接続端子4を対応する配線導体8、9
の上に当接させながらも、ロウ材a、bを介して対向配
設する。しかる後、約250〜400℃の温度で加熱す
ることで、半田などのロウ材が溶融し、ロウ材a、bが
できる。このようなロー付けの工程でもってパッケージ
Aが回路基板Bに実装される。
Next, a method of mounting the package A on the circuit board B will be described. Wiring conductors 8 and 9 are formed in the recess 10 of the circuit board B and further on predetermined portions of the insulator 7, and cream-like low melting point solder is applied on these wiring conductors 8 and 9 by printing. Also in the package A, the connection terminals 4 are formed on the insulating substrate 1, cream-like low melting point solder is applied thereon by printing, and a spherical solder made of high melting point solder is placed thereon. Heating is performed at a temperature of 250 ° C. to fix the spherical solder on the package A.
Next, the package A is mounted on the circuit board B. At this time, the individual connection terminals 4 are connected to the corresponding wiring conductors 8 and 9.
, While being in contact with each other, are disposed to face each other with the brazing materials a and b interposed therebetween. Thereafter, by heating at a temperature of about 250 to 400 ° C., the brazing material such as solder is melted to form brazing materials a and b. The package A is mounted on the circuit board B by such a brazing process.

【0021】かくして本発明の実装構造においては、上
記構成のように配線導体9を凹部10内に配設したこと
で、ロウ材bの寸法が長くなり、さらにロウ材b付近に
てたわみ易くなり、そのために絶縁基板1と回路基板B
との双方での熱膨張の差によって生ずる熱応力が低減さ
れ、その結果、パッケージAと回路基板Bとの間にて接
続不良が生じなくなり、長期にわたり確実にかつ強固な
電気的接続が保持される。
Thus, in the mounting structure of the present invention, since the wiring conductors 9 are disposed in the recesses 10 as described above, the size of the brazing material b is increased, and the brazing material b is easily bent near the brazing material b. Therefore, the insulating substrate 1 and the circuit board B
The thermal stress caused by the difference in thermal expansion between the package A and the circuit board B is reduced. As a result, a poor connection does not occur between the package A and the circuit board B, and a reliable and strong electrical connection is maintained for a long time. You.

【0022】本発明の好適な態様として、セラミックス
からなる絶縁基板1の40〜400℃における熱膨張係
数を7〜25ppm/℃、最適には8〜25ppm/℃
にするとよい。すなわち、半導体素子5の熱膨張係数は
通常1〜3ppm/℃であり、回路基板Bの熱膨張係数
は10〜40ppm/℃であり、絶縁基板1の熱膨張係
数を半導体素子5および回路基板Bとの双方の間に規定
するとよく、その範囲を7〜25ppm/℃にすると、
半導体素子5を安定してパッケージA上に固定でき、し
かも、パッケージAと回路基板Bとの熱膨張係数差によ
り発生する熱応力が緩和され、その結果、信頼性に高い
実装構造を実現できる。
As a preferred embodiment of the present invention, the thermal expansion coefficient of the insulating substrate 1 made of ceramics at 40 to 400 ° C. is 7 to 25 ppm / ° C., optimally 8 to 25 ppm / ° C.
It is good to That is, the coefficient of thermal expansion of the semiconductor element 5 is usually 1 to 3 ppm / ° C., the coefficient of thermal expansion of the circuit board B is 10 to 40 ppm / ° C., and the coefficient of thermal expansion of the insulating substrate 1 is It is good to define between both, and when the range is 7 to 25 ppm / ° C,
The semiconductor element 5 can be stably fixed on the package A, and the thermal stress generated due to the difference in the thermal expansion coefficient between the package A and the circuit board B is alleviated. As a result, a highly reliable mounting structure can be realized.

【0023】また、パッケージAのメタライズ配線層3
を金や銅により形成し、さらに絶縁基板1とともに同時
焼成(焼成温度:1000℃以下)するとよい。そのた
めの好適な絶縁基板材料として、結晶性のリチウム珪酸
ガラス、ホウ珪酸ガラスなどを20〜80体積%の比率
で、そして、SiO2 (クオーツ、クリストバライ
ト)、Al2 3 、エンスタタイトなどのフィラー成分
を80〜20体積%の比率で混合し、その混合物を成形
し、そして、焼成することでガラスセラミック焼結体が
得られる。このような混合比率によって1000℃以下
の温度にて焼成できる。
The metallized wiring layer 3 of the package A
May be formed of gold or copper, and may be simultaneously fired with the insulating substrate 1 (a firing temperature: 1000 ° C. or less). As a suitable insulating substrate material therefor, crystalline lithium silicate glass, borosilicate glass or the like at a ratio of 20 to 80% by volume, and a filler such as SiO 2 (quartz, cristobalite), Al 2 O 3 , enstatite, etc. The components are mixed at a ratio of 80 to 20% by volume, the mixture is shaped and fired to obtain a glass ceramic sintered body. With such a mixing ratio, firing can be performed at a temperature of 1000 ° C. or less.

【0024】結晶性リチウム珪酸ガラスを用いる場合に
は、Li2 Oを5〜30重量%の割合で含有し、SiO
2 を60〜85重量%含み、Li2 OとSiO2 の合量
が65〜95重量%であって、残部がAl2 3 、アル
カリ土類酸化物、アルカリ金属酸化物、ZnO、P2
5 等から成るものが好適である。
When crystalline lithium silicate glass is used, Li 2 O is contained at a ratio of 5 to 30% by weight and SiO 2 is used.
2 comprises 60 to 85 wt%, the total amount of Li 2 O and SiO 2 is a 65 to 95 wt%, the balance being Al 2 O 3, alkaline earth oxides, alkali metal oxides, ZnO, P 2 O
Those composed of 5 or the like are preferred.

【0025】また、リチウム珪酸ガラスに対し、フィラ
ー成分としてクオーツ、フォルステライト、エンスタタ
イト、クリストバライトを含むと、熱膨張係数を容易に
7〜25ppm/℃に制御できる。加えて、その他のフ
ィラー成分として、トリジマイト、スピネル、ウォラス
ナイト、モンティセラナイト、ネフェィン、リチウムシ
リケート、ジオプサイド、メルビナイト、アケルマイ
ト、マグネシア、アルミナ、カーネギアイト、ホウ酸マ
グネシウム、セルシアン、ガーナイト、ペタライト等を
添加してもよい。
When quartz, forsterite, enstatite, and cristobalite are contained as filler components in lithium silicate glass, the coefficient of thermal expansion can be easily controlled to 7 to 25 ppm / ° C. In addition, as other filler components, tridymite, spinel, wollastonite, montiselanite, nephein, lithium silicate, diopside, merbinite, akermite, magnesia, alumina, carnegieite, magnesium borate, celsian, garnite, petalite, etc. You may.

【0026】上記のような結晶性ガラスとフィラーとの
混合物に対し、成形用有機樹脂バインダーを添加し、つ
いで所望の成形手段、たとえばドクターブレード、圧延
法、金型プレスなどによりシート状に成形してグリーン
シートを得る。このグリーンシートの表面に銅や金など
のメタライズペーストをスクリーン印刷法等によって印
刷し、しかも、適当な打抜き加工をおこなってスルーホ
ールを形成し、このスルーホール内にもメタライズペー
ストを充填し、これらのグリーンシートを複数枚積層
し、焼成する。
An organic resin binder for molding is added to the mixture of the crystalline glass and the filler as described above, and then formed into a sheet by a desired molding means, for example, a doctor blade, a rolling method, a die press or the like. To get a green sheet. A metallizing paste such as copper or gold is printed on the surface of the green sheet by a screen printing method or the like, and furthermore, an appropriate punching process is performed to form a through hole, and the metallizing paste is filled in the through hole. Are laminated and fired.

【0027】この焼成においては、成形のために配合し
たバインダー成分を700℃前後の大気雰囲気中にて除
去する。また、配線導体8、9を銅(Cu)にて形成す
る場合には、水蒸気を含有する100〜700℃の窒素
雰囲気中にておこなう。さらに成形体の収縮開始温度を
700〜850℃程度にするとよい。700℃未満の低
い温度になると、バインダー除去が困難となりやすい。
In this firing, the binder component blended for molding is removed in an atmosphere at about 700 ° C. When the wiring conductors 8 and 9 are formed of copper (Cu), the wiring conductors 8 and 9 are formed in a nitrogen atmosphere containing water vapor at 100 to 700 ° C. Further, the shrinkage start temperature of the molded body is preferably set to about 700 to 850 ° C. If the temperature is lower than 700 ° C., it becomes difficult to remove the binder.

【0028】焼成は850℃〜1050℃の酸化性雰囲
気中にておこなうとよく、これによって相対密度90%
以上にまで緻密化される。焼成温度が850℃未満では
緻密化されず、1050℃を超えるとメタライズ配線層
との同時焼成でメタライズ層が溶融する。
The firing is preferably performed in an oxidizing atmosphere at 850 ° C. to 1050 ° C., whereby the relative density is 90%.
It is densified up to the above. If the firing temperature is lower than 850 ° C., the metallized layer is not densified, and if it exceeds 1050 ° C., the metallized layer is melted by simultaneous firing with the metallized wiring layer.

【0029】このように作製された配線基板の絶縁基板
を構成するガラスセラミック焼結体によれば、フィラー
として添加したフォルステライト、クォーツ、クリスト
バライトなどの結晶相や、これらフィラー成分に基づく
エンスタタイト等の結晶相、さらには結晶性ガラスから
析出したリチウムシリケート結晶相が存在する。その
他、結晶性ガラスとフィラーとの反応により生成した結
晶相も存在する場合がある。さらにこれらの結晶相の粒
界には、微量のガラス相が存在する場合もある。これら
の熱膨張係数の大きい結晶相を析出させることにより、
高熱膨張係数を有するガラスセラミック焼結体が得られ
る。
According to the glass ceramic sintered body constituting the insulating substrate of the wiring board thus manufactured, the crystalline phase of forsterite, quartz, cristobalite or the like added as a filler, enstatite or the like based on these filler components, or the like is used. , And a lithium silicate crystal phase precipitated from crystalline glass. In addition, there may be a crystal phase generated by the reaction between the crystalline glass and the filler. Furthermore, a small amount of a glass phase may be present at the grain boundaries of these crystal phases. By precipitating these crystal phases with a large coefficient of thermal expansion,
A glass ceramic sintered body having a high coefficient of thermal expansion is obtained.

【0030】なお、本発明は上記の実施形態例に限定さ
れるものではなく、本発明の要旨を逸脱しない範囲内で
種々の変更や改良等は何ら差し支えない。たとえば、上
記の例では回路基板Bの凹部10(配線導体9)を配線
導体群の全周囲に設けたが、これに代えて図3の回路基
板B1のように配線導体群の周囲に複数列でもって配線
導体9を並べたり、図4の回路基板B2のように応力が
もっとも大きい4隅部に集中して設けたり、あるいは2
隅部や3隅部に設けたり、また、図5の回路基板B3の
ように配線導体群の周囲に非連続に配線導体9を並べて
もよい。
It should be noted that the present invention is not limited to the above-described embodiment, and various changes and improvements may be made without departing from the scope of the present invention. For example, in the above example, the concave portions 10 (wiring conductors 9) of the circuit board B are provided all around the group of wiring conductors. Thus, the wiring conductors 9 may be arranged, or may be provided at four corners where the stress is greatest as in the circuit board B2 in FIG.
The wiring conductors 9 may be provided at the corners or three corners, or the wiring conductors 9 may be discontinuously arranged around the wiring conductor group as in the circuit board B3 in FIG.

【0031】また、上述の場合は、凹部10(配線導体
9)を配線導体群の周囲に並べているが、その他に図6
〜図9に示すように配線導体群の内側に設けてもよい。
In the above case, the recesses 10 (wiring conductors 9) are arranged around the group of wiring conductors.
9 may be provided inside the wiring conductor group.

【0032】[0032]

【実施例】(例1)アルミナ92体積%と残部(Si
O、CaO、MgO)8体積%での混合比率の原料でも
って成形し、メタライズ配線層用にはタングステン
(W)材を用いてスルーホールを形成し、Wのメタライ
ズからなる接続端子も形成し、そして、1600℃の窒
素雰囲気にて同時焼成し、5×4×40mmサイズの絶
縁基板(配線基板)を作製した。
(Example 1) 92% by volume of alumina and the balance (Si
(O, CaO, MgO) molded with raw materials having a mixing ratio of 8% by volume, a through hole is formed using a tungsten (W) material for a metallized wiring layer, and a connection terminal formed of metallized W is also formed. Then, they were simultaneously fired in a nitrogen atmosphere at 1600 ° C. to produce an insulating substrate (wiring substrate) having a size of 5 × 4 × 40 mm.

【0033】この絶縁基板の40〜400℃における熱
膨張係数を測定したところ、7.0ppm/℃であっ
た。そして、接続端子にNiメッキを施した後に、この
端子に高融点半田(Pb90重量%−Sn10重量%)
からなる直径0.8mmのボール状ロウ材a、bを低融
点半田(Pb37重量%−Sn63重量%)でもって取
り付けた。接続端子のピッチは、1.27mm、端子数
は1225個、パッケージの1辺の長さは45mm、配
線基板の厚みは2mmである。
When the coefficient of thermal expansion of this insulating substrate at 40 to 400 ° C. was measured, it was 7.0 ppm / ° C. Then, after the connection terminal is plated with Ni, a high melting point solder (Pb 90% by weight-Sn 10% by weight) is applied to the terminal.
The ball-shaped brazing materials a and b having a diameter of 0.8 mm were attached with low melting point solder (Pb 37% by weight-Sn 63% by weight). The pitch of the connection terminals is 1.27 mm, the number of terminals is 1225, the length of one side of the package is 45 mm, and the thickness of the wiring board is 2 mm.

【0034】一方、回路基板Bとしてガラス−エポキシ
基板(40〜400℃における熱膨張係数:13ppm
/℃)である絶縁体の表面に銅箔からなる配線導体が形
成されたプリント基板を準備した。プリント基板の1辺
の長さは80mm、厚みは1.6mmとした。また、マ
トリックス状に配列された配線導体群において外周の2
列の配線導体については、絶縁体に設けた凹部内に配設
した。この凹部はドリルおよびレーザーにより所要どお
りの径および深さでもって表1に示すような径比率およ
び深さ比率に加工した。この径比率は凹部の内径の接続
端子の外径(パッド径)に対する比率であり、深さ比率
は凹部の深さの接続端子の外径(パッド径)に対する比
率である。
On the other hand, as a circuit board B, a glass-epoxy board (coefficient of thermal expansion at 40 to 400 ° C .: 13 ppm)
/ ° C) on a surface of an insulator on which a wiring conductor made of a copper foil was formed. The length of one side of the printed circuit board was 80 mm, and the thickness was 1.6 mm. In the wiring conductor group arranged in a matrix,
The wiring conductors in the columns were arranged in recesses provided in the insulator. This concave portion was machined to a diameter ratio and a depth ratio as shown in Table 1 with a required diameter and depth using a drill and a laser. The diameter ratio is a ratio of the inner diameter of the recess to the outer diameter (pad diameter) of the connection terminal, and the depth ratio is the ratio of the depth of the recess to the outer diameter (pad diameter) of the connection terminal.

【0035】そして、かかるプリント基板の配線導体
(パッド)上に低融点半田ペースト(Pb37重量%−
Sn63重量%)を印刷法により塗布し、その上に前記
接続端子を重ね、ピーク温度230℃のリフロー炉を使
用して硬化接続させ、凹部を形成しない従来の試料N
o.1ならびに径比率および深さ比率を幾とおりにも変
えた各種の試料No.2〜8を作製した。
Then, a low-melting-point solder paste (Pb 37% by weight) is formed on the wiring conductor (pad) of the printed circuit board.
Sn 63% by weight) is applied by a printing method, the connection terminal is superimposed thereon, and the connection is hardened and connected using a reflow furnace having a peak temperature of 230 ° C. to obtain a conventional sample N having no concave portion.
o. No. 1 and various sample Nos. With various diameter ratios and depth ratios. 2 to 8 were produced.

【0036】[0036]

【表1】 [Table 1]

【0037】つぎに各試料に対し熱サイクル試験をおこ
なった。大気の雰囲気にて−40℃と125℃の各温度
に制御した恒温槽に試料を30分/30分の保持を1サ
イクルとして最高1000サイクル繰り返した。そし
て、各サイクル毎にプリント基板の配線導体とパッケー
ジ用基板との電気抵抗を測定し、電気抵抗に変化が現れ
るまでの耐久サイクル数を表1に示す。
Next, each sample was subjected to a heat cycle test. The sample was held in a thermostat controlled at -40 ° C. and 125 ° C. in an atmosphere of air at 30 ° C./30 min. Then, the electrical resistance between the wiring conductor of the printed circuit board and the package substrate was measured for each cycle, and the number of endurance cycles until the electrical resistance changed was shown in Table 1.

【0038】この表から明らかなとおり、凹部を設けた
本発明の試料.2〜8であれば、熱サイクル試験に対し
良好な結果が得られ、その結果、長期間にわたって強固
にかつ安定した接続ができることがわかる。
As is clear from this table, the sample of the present invention provided with a concave portion. If it is 2 to 8, good results can be obtained for the heat cycle test, and as a result, it can be seen that a strong and stable connection can be obtained for a long period of time.

【0039】(例2)本例においては、絶縁基板につい
て、リチウム珪酸ガラス80体積%、フィラー成分とし
てクォーツ20体積%を原料にして作製した。その場
合、メタライズ配線層およびスルーホールは銅材でもっ
て形成し、900℃の窒素雰囲気にて同時焼成した。そ
の他は(例1)を同じである。この絶縁基板の40〜4
00℃における熱膨張係数を測定したところ、10.0
ppm/℃であった。そして、凹部は表2〜表7に示す
ような径比率および深さ比率に加工した。
(Example 2) In this example, an insulating substrate was manufactured using 80% by volume of lithium silicate glass and 20% by volume of quartz as a filler component as raw materials. In this case, the metallized wiring layer and the through-hole were formed of a copper material and fired simultaneously in a nitrogen atmosphere at 900 ° C. Others are the same as (Example 1). 40 to 4 of this insulating substrate
The coefficient of thermal expansion at 00 ° C. was determined to be 10.0
ppm / ° C. Then, the concave portion was processed into a diameter ratio and a depth ratio as shown in Tables 2 to 7.

【0040】径比率を60%にして、さらに深さ比率を
5〜125%の範囲内で幾とおりにも変えたところ、表
2に示すような結果が得られた。
When the diameter ratio was changed to 60% and the depth ratio was changed variously within the range of 5 to 125%, the results shown in Table 2 were obtained.

【0041】[0041]

【表2】 [Table 2]

【0042】径比率を80%にして、さらに深さ比率を
幾とおりにも変えたところ、表3に示すような結果が得
られた。
When the diameter ratio was changed to 80% and the depth ratio was changed in various ways, the results shown in Table 3 were obtained.

【0043】[0043]

【表3】 [Table 3]

【0044】径比率が100%である場合には、表4に
示すような結果が得られた。
When the diameter ratio was 100%, the results shown in Table 4 were obtained.

【0045】[0045]

【表4】 [Table 4]

【0046】径比率が120%の場合には、表5に示す
ような結果が得られた。
When the diameter ratio was 120%, the results shown in Table 5 were obtained.

【0047】[0047]

【表5】 [Table 5]

【0048】径比率が140%の場合には、表6に示す
ような結果が得られた。
When the diameter ratio was 140%, the results shown in Table 6 were obtained.

【0049】[0049]

【表6】 [Table 6]

【0050】径比率が160%の場合には、表7に示す
ような結果が得られた。
When the diameter ratio was 160%, the results shown in Table 7 were obtained.

【0051】[0051]

【表7】 [Table 7]

【0052】これらの表から明らかなように、回路基板
Bの周囲付近に設けた配線導体を、絶縁板に形成した凹
部内に設けたことで、パッケージAと回路基板Bとの間
を長期間にわたって強固にかつ安定して接続させ、これ
によって高信頼性の配線基板の実装構造が提供できた。
とくに径比率が60%もしくは160%の場合には深さ
比率が30〜75%にすることで、1000サイクルま
で抵抗変化はまったく認められず、きわめて良好な電気
的接続状態を維持できた。また、径比率が80〜140
%の場合に、深さ比率が10〜100%にすることで、
同様に1000サイクルまで抵抗変化はまったく認めら
れなった。
As is clear from these tables, since the wiring conductors provided near the periphery of the circuit board B are provided in the recesses formed in the insulating plate, the distance between the package A and the circuit board B can be extended. Thus, the connection structure was firmly and stably connected over a wide range, thereby providing a highly reliable wiring board mounting structure.
In particular, when the diameter ratio was 60% or 160%, by setting the depth ratio to 30 to 75%, no change in resistance was observed at all up to 1000 cycles, and an extremely good electrical connection state could be maintained. In addition, the diameter ratio is 80 to 140
%, By setting the depth ratio to 10 to 100%,
Similarly, no change in resistance was observed up to 1000 cycles.

【0053】[0053]

【発明の効果】以上のとおり、本発明によれば、配線基
板の接続端子群を外部電気回路基板の配線導体群に個別
にロウ付けした実装構造において、外部電気回路基板に
設けた配線導体の一部を、絶縁板に形成した凹部内に設
けたことで、凹部内のロウ材の寸法が長くなり、さらに
ロウ材付近にてたわみ易くなり、そのために配線基板と
外部電気回路基板との間での熱膨張の差によって生ずる
熱応力が低減され、これにより、配線基板と外部電気回
路基板との間にて接続不良が生じなくなり、長期にわた
り確実にかつ強固な電気的接続が保持され、その結果、
長期間にわたって強固にかつ安定して接続させた高信頼
性の配線基板の実装構造が提供できた。とくに半導体回
路素子の大型化に伴う多端子化の配線基板に対して高い
信頼性の実装構造が提供できた。
As described above, according to the present invention, in the mounting structure in which the connection terminal group of the wiring board is individually brazed to the wiring conductor group of the external electric circuit board, the wiring conductor provided on the external electric circuit board is provided. By providing a part in the recess formed in the insulating plate, the size of the brazing material in the recess becomes longer, and it becomes easier to bend near the brazing material. The thermal stress caused by the difference in thermal expansion at the substrate is reduced, thereby preventing poor connection between the wiring board and the external electric circuit board, and reliably and firmly maintaining the electrical connection for a long time. result,
A highly reliable wiring board mounting structure that is firmly and stably connected for a long time can be provided. In particular, a highly reliable mounting structure can be provided for a multi-terminal wiring board accompanying an increase in the size of a semiconductor circuit element.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の配線基板であるBGA型半導体素子収
納用パッケージを外部電気回路基板に実装した構造の断
面図である。
FIG. 1 is a cross-sectional view of a structure in which a package for storing a BGA type semiconductor element which is a wiring board of the present invention is mounted on an external electric circuit board.

【図2】本発明の外部電気回路基板の配線導体群の配列
を示す平面図である。
FIG. 2 is a plan view showing an arrangement of wiring conductor groups of the external electric circuit board of the present invention.

【図3】本発明の他の外部電気回路基板の配線導体群の
配列を示す平面図である。
FIG. 3 is a plan view showing an arrangement of wiring conductor groups of another external electric circuit board of the present invention.

【図4】本発明の他の外部電気回路基板の配線導体群の
配列を示す平面図である。
FIG. 4 is a plan view showing an arrangement of wiring conductor groups of another external electric circuit board of the present invention.

【図5】本発明の他の外部電気回路基板の配線導体群の
配列を示す平面図である。
FIG. 5 is a plan view showing an arrangement of wiring conductor groups of another external electric circuit board of the present invention.

【図6】本発明の他の外部電気回路基板の配線導体群の
配列を示す平面図である。
FIG. 6 is a plan view showing an arrangement of wiring conductor groups of another external electric circuit board of the present invention.

【図7】本発明の他の外部電気回路基板の配線導体群の
配列を示す平面図である。
FIG. 7 is a plan view showing an arrangement of wiring conductor groups of another external electric circuit board of the present invention.

【図8】本発明の他の外部電気回路基板の配線導体群の
配列を示す平面図である。
FIG. 8 is a plan view showing an arrangement of wiring conductor groups of another external electric circuit board of the present invention.

【図9】本発明の他の外部電気回路基板の配線導体群の
配列を示す平面図である。
FIG. 9 is a plan view showing an arrangement of wiring conductor groups of another external electric circuit board of the present invention.

【符号の説明】[Explanation of symbols]

A BGA型半導体素子収納用パ
ッケージ(パッケージ) B、B1、B2、B3 外部電気回路基板(回路基
板) 1 絶縁基板 5 半導体素子 2 蓋体 6 容器 4 接続端子 a、b ロウ材 7 絶縁体 8、9 配線導体 10 凹部
A BGA type semiconductor element storage package (package) B, B1, B2, B3 External electric circuit board (circuit board) 1 Insulating substrate 5 Semiconductor element 2 Lid 6 Container 4 Connection terminal a, b Brazing material 7 Insulator 8, 9 wiring conductor 10 recess

───────────────────────────────────────────────────── フロントページの続き Fターム(参考) 5E319 AA03 AA07 AA10 AB05 AC02 AC04 AC15 BB04 CC58 CD29 GG03 GG11 GG20 5E336 AA04 AA08 AA09 AA16 BB01 BB16 BB18 BC25 BC34 CC33 CC34 CC36 CC43 CC58 DD01 EE01 GG11  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E319 AA03 AA07 AA10 AB05 AC02 AC04 AC15 BB04 CC58 CD29 GG03 GG11 GG20 5E336 AA04 AA08 AA09 AA16 BB01 BB16 BB18 BC25 BC34 CC33 CC34 CC36 CC43 CC58 DD01 EE01 GG11

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】メタライズ配線層が配設されたセラミック
絶縁基板の一面に接続端子群を形成した配線基板を、ガ
ラスと合成樹脂との複合材からなる絶縁板上に配線導体
群が被着形成された外部電気回路基板上に載置するとと
もに、前記配線基板の接続端子群を前記外部電気回路基
板の配線導体群に個別にロウ付けした実装構造におい
て、前記配線導体の一部を、絶縁板に形成した凹部内に
設けて、接続端子と配線導体との間隔を他の配線導体に
比べ長くしたことを特徴とする配線基板の実装構造。
1. A wiring substrate having a connection terminal group formed on one surface of a ceramic insulating substrate provided with a metallized wiring layer, and a wiring conductor group formed on an insulating plate made of a composite material of glass and synthetic resin. In the mounting structure in which the connection terminal group of the wiring board is individually brazed to the wiring conductor group of the external electric circuit board, the wiring conductor is partially placed on an insulating plate. A wiring board mounting structure characterized in that the distance between the connection terminal and the wiring conductor is longer than that of the other wiring conductors by being provided in the recess formed in the wiring board.
JP11020707A 1999-01-28 1999-01-28 Mounting board for wiring board Pending JP2000223814A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11020707A JP2000223814A (en) 1999-01-28 1999-01-28 Mounting board for wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11020707A JP2000223814A (en) 1999-01-28 1999-01-28 Mounting board for wiring board

Publications (1)

Publication Number Publication Date
JP2000223814A true JP2000223814A (en) 2000-08-11

Family

ID=12034630

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11020707A Pending JP2000223814A (en) 1999-01-28 1999-01-28 Mounting board for wiring board

Country Status (1)

Country Link
JP (1) JP2000223814A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013093404A (en) * 2011-10-25 2013-05-16 Ngk Spark Plug Co Ltd Wiring board and manufacturing method of the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013093404A (en) * 2011-10-25 2013-05-16 Ngk Spark Plug Co Ltd Wiring board and manufacturing method of the same

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