JP2000223659A - Semiconductor integration structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress strain being introduced into a semiconductor element layer by setting the strain reducing layer of an integrated structure with a coefficient of thermal expansion within a specified range of a semiconductor element layer and a specified Young's modulus of a bother board or above and then bonding the upper and lower layers of an adhesion layer mechanically. SOLUTION: A semiconductor circuit board having an insulation film is employed as a mother board 54, a heat dissipation layer and a strain reducing layer 53 are deposited on the mother board 54 under room temperature, an adhesive layer 52 is laminated thereon while hardening through temperature rise and then a semiconductor element layer 51 is bonded thereto. The strain reducing layer 53 in such a structure is set with a coefficient of thermal expansion in the range of 0.6-1.5 times that of the semiconductor element layer 51 and a Young's modulus equal to or higher than 2.5 times that of the mother board 54. The adhesive layer 52 having high temperature hardening properties is provided with a function for bonding the upper and lower strain reducing layer 53 of the adhesive layer 52 and the semiconductor element layer 51 mechanically.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a bonding structure for integrating a semiconductor light receiving element and a semiconductor light emitting element on a mother substrate.

[0002]

2. Description of the Related Art A hybrid structure in which a light receiving element and a light emitting element of a compound semiconductor are integrated on a large-scale silicon integrated circuit is called a smart pixel, and a large-capacity optical interconnection system between chips or boards or an optical computing system. The expectations applied to are increasing. As a method for manufacturing this hybrid structure, a method using polyimide as an adhesive layer has been developed, for example, ELEC
The method is described in detail in TRONICS LETTERS Vol. 33 No. 13 pp. 1148-1149 (1997). In this method,
A compound semiconductor substrate on which a light-receiving element layer or a light-emitting element layer, or both layers are epitaxially grown, and a silicon integrated circuit board are mechanically bonded using polyimide as an adhesive layer. According to the alignment marker, the light-receiving element or the light-emitting element of the compound semiconductor is formed by a manufacturing process using ordinary photolithography.
The positioning between the light receiving elements, the positioning between the light emitting elements, and the positioning between the light receiving element and the light emitting element are all easy and accurate. The electrical connection between the silicon integrated circuit and the light receiving element and the electrical connection between the silicon integrated circuit and the light emitting element are made using metal plating. As described above, by the method using the adhesive layer, the light receiving element and the light emitting element of the compound semiconductor can be collectively integrated over a wide area over the semiconductor integrated circuit substrate.

A semiconductor integrated circuit generally has a layer having poor heat radiation characteristics such as a protective film and an insulating film (in this specification, a thermal conductivity of 4).
0 W / m / K or less) when the total thickness is 2 μm or more, and the method using an adhesive layer is applied to the integration of a heating element such as a semiconductor laser on a semiconductor integrated circuit substrate. In order to improve the heat dissipation of the heating element, it is effective to remove the layer with poor heat dissipation property from the semiconductor integrated circuit board and replace it with a layer with good heat dissipation property only in the area where the heating element is mounted. there were. This is shown in FIG. However, FIG. 1 does not show the heating element and the adhesive layer.

In FIG. 1, reference numeral 1 denotes plasma silicon nitride (P-
SiN) film, 2 is a PSG film, 3 is an aluminum second wiring layer (AL-2), 4 is an interlayer insulating film, 5 is a plasma silicon oxide (P-SiO) film, and 6 is an aluminum first wiring layer (AL-). 1) and 7 are BPSG films, 8 is Poly-Si,
9 is a field oxide film, 10 is a gate oxide film, 11 is a contact electrode, 12 is a laser mounting area, 13 is a heat dissipation layer,
Reference numeral 14 denotes a SiN film, and 15 denotes a silicon CMOS circuit substrate. Then, the adhesive layer and the heating element are adhered on the heat radiation layer 13. At this time, as the material of the heat radiation layer 13, for example, gold, copper, and aluminum having high thermal conductivity were suitable.

[0005]

However, the method using an adhesive layer has the following disadvantages. Gold used for the heat dissipation layer,
As shown in Table 1, copper and aluminum are materials having a very large coefficient of thermal expansion as compared with a semiconductor and at the same time having a Young's modulus similar to that of a semiconductor. On the other hand, the material used for the adhesive layer needs to be a material that can withstand heat treatment at the time of forming a semiconductor element after bonding the substrate, and a thermosetting organic material, for example, a polyimide resin for bonding is used. When such a thermosetting organic material is used, the bonding temperature is 350 ° C. or higher. Because of this, gold, copper,
Alternatively, due to the difference in the thermal expansion coefficient between the heat dissipation layer of aluminum and the semiconductor element layer, strain is introduced into the semiconductor element layer when the temperature is lowered after bonding, for example, when a semiconductor laser is integrated, the initial characteristics and life of the laser are deteriorated. There was a problem.

[0006]

[Table 1]

According to the present invention, when a semiconductor element is integrated on a mother substrate by a method using an adhesive layer, distortion introduced into the semiconductor element layer by adhesion at a high temperature is reduced, and heat dissipation of the semiconductor element is improved. It is an object of the present invention to provide a semiconductor integrated structure that keeps the same.

[0008]

According to a first embodiment of the present invention, there is provided a structure in which a mother substrate, a strain reducing layer, an adhesive layer, and a semiconductor element layer are integrated in this order. Have a thermal expansion coefficient of 0.6 times or more and 1.5 times or less of the semiconductor element layer, a Young's modulus of 2.5 times or more of the mother substrate, and the adhesive layer has a property of curing at a high temperature. And a function of mechanically bonding the upper and lower layers of the adhesive layer. FIG. 2 is a schematic cross-sectional view, where 51 is a semiconductor element layer, 52 is an adhesive layer, 53 is a strain reduction layer, and 54 is a mother substrate.

According to a second embodiment of the present invention, in the first embodiment, a heat radiator made of a material having a thermal conductivity of 200 W / m / K or more is provided between the mother substrate and the strain reducing layer. A heat radiation layer having a thickness of 0.5 times or more of the mother substrate layer.
A semiconductor integrated structure having a Young's modulus of 5 times or less. FIG. 4 is a cross-sectional view showing the outline thereof.
Here, 13 is a heat dissipation layer, 51 is a semiconductor element layer, 52 is an adhesive layer, 53 is a strain reduction layer, and 54 is a mother substrate.

A third embodiment of the present invention provides a mother substrate, an adhesive layer,
A structure in which a strain reduction layer and a semiconductor element layer are integrated in this order, wherein the strain reduction layer has a thermal expansion coefficient of 0.6 to 1.5 times the semiconductor element layer, and the mother substrate A semiconductor integrated circuit having a Young's modulus of 2.5 times or more of that described above, and having a function of mechanically bonding the upper and lower layers of the adhesive layer, wherein the adhesive layer has a high-temperature curing property. It is a structure. FIG. 3 is a cross-sectional view schematically showing the structure, in which 51 is a semiconductor element layer, 52 is an adhesive layer, 53 is a strain reduction layer, and 54 is a mother substrate.

According to a fourth embodiment of the present invention, in the third embodiment, the thermal conductivity is different between the mother substrate and the adhesive layer or between the adhesive layer and the strain reducing layer. A semiconductor integrated structure having a heat dissipation layer made of a material of 200 W / m / K or more, wherein the heat dissipation layer has a Young's modulus of 0.5 to 1.5 times the mother substrate layer. . FIG. 5 is a cross-sectional view showing the outline thereof, 13 is a heat dissipation layer, 51 is a semiconductor element layer, 52 is an adhesive layer, 53 is a strain reduction layer, and 54 is a mother substrate.

According to a fifth embodiment of the present invention, in any one of the first to fourth embodiments, the distortion reduction layer has a thermal expansion coefficient larger than a thermal expansion coefficient of the semiconductor element layer. Semiconductor integrated material having a thermal expansion coefficient of 0.6 times or more and 1.5 times or less of the semiconductor element layer, which is a multilayer structure or an alloy composed of a material having a low thermal expansion coefficient and a material having a low thermal expansion coefficient. It is a structure.

According to a sixth embodiment of the present invention, there is provided a semiconductor integrated structure according to any one of the first to fifth embodiments, wherein a semiconductor integrated circuit substrate is used as the mother substrate. Body.

A seventh embodiment of the present invention is the same as the sixth embodiment, except that the semiconductor integrated circuit board has a thermal conductivity of 40 W /
a semiconductor integrated structure, wherein the strain reducing layer and the heat dissipation layer are selectively deposited or bonded in a concave portion formed by removing a component made of a material having a m / K or less. Body.

An eighth embodiment of the present invention is the vertical cavity surface emitting laser according to any one of the first to seventh embodiments, wherein the semiconductor element layer is made of a compound semiconductor. A semiconductor integrated structure characterized by using:

According to a ninth embodiment of the present invention, in the eighth embodiment, a silicon integrated circuit substrate is used as the mother substrate, and a gallium arsenide / aluminum gallium arsenide semiconductor is used as the material of the surface emitting laser. A semiconductor integrated structure using a material, and using a metal material selected from the group consisting of chromium, molybdenum, and tungsten, a multilayer structure thereof, or an alloy thereof as the strain reduction layer.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation when a semiconductor integrated structure according to a second embodiment of the present invention is used will be described. The layer structure of the semiconductor integrated structure is such that the mother substrate 5
4, a heat dissipation layer 13, a strain reduction layer 53, an adhesive layer 52, and a semiconductor element layer 51. FIG. 4 shows a schematic sectional view.

FIG. 6 is a sectional view of the laser mounting portion of the embodiment when a semiconductor circuit board having an insulating film is used as the mother board 54. 6 used in FIGS. 1 and 4 as they are. This figure is a cross-sectional view before the semiconductor element layer 51 is bonded, and the bonding layer 52 is shown.
And the semiconductor element layer 51 are not shown. As described in the prior art, in order to improve the heat radiation of the heating element, only in the region where the heating element such as a laser is mounted, the insulating film having poor heat radiation characteristics (that is, the interlayer insulating film 4, the surface passivation (P -SiO) film 1, PSG film 2, P-SiO film 5,
The structure is such that the BPSG film 7 and the field oxide film 9) are partially removed from the semiconductor integrated circuit substrate. The heat radiation layer 13 has a thermal conductivity of 200 W / m / K or more. Therefore, it functions as a layer having good heat radiation characteristics in place of a layer having poor heat radiation characteristics.

Since the heat radiation layer 13 and the strain reducing layer 53 are deposited on the mother substrate 54 at room temperature, all the layers have no strain at room temperature before the temperature of the adhesive layer 52 is raised and hardened. When the strain reducing layer 53 is not provided, the temperature of the adhesive layer 5 is increased by increasing the temperature.
After curing the semiconductor element layer 51 and bonding the semiconductor element layer 51, when the temperature is lowered to room temperature, the difference in the coefficient of thermal expansion between the semiconductor element layer 51 and the heat radiation layer 13 and the difference between the semiconductor element layer 51 and the mother substrate 5
4, the semiconductor element layer 5
Strain is introduced into all layers including 1. However, when the strain reducing layer 53 is provided, the strain reducing layer 53 is characterized in that the Young's modulus is larger (harder) than those of the heat radiation layer 13 and the mother substrate 54, and thus the strain reducing layer 53 generated by temperature rise / fall. Of the strain reduction layer 5
(3) Elongation / shrinkage due to the inherent thermal expansion coefficient becomes dominant, and the heat radiation layer having a small Young's modulus (soft) and the mother substrate 54 are less likely to be affected. At the same time, the strain reducing layer 53
Is characterized in that the coefficient of thermal expansion is 0.6 times or more and 1.5 times or less of that of the semiconductor element layer 51. Shrink by the amount of At this time, if the coefficient of thermal expansion of the strain reducing layer 53 is not within the above range, the strain reducing layer 53 has not only the effect of reducing the strain generated in the semiconductor element layer 51 but also the strain reducing layer 53. If the shrinkage is even greater than the shrinkage of the heat radiation layer 13 or the strain reduction layer 53
Is smaller than the contraction of the mother substrate 54, the distortion generated in the semiconductor element layer 51 is increased as compared with the case where the distortion reduction layer 53 is not provided. That is, as a result, the strain introduced after bonding and cooling can be concentrated on the heat dissipation layer 13 and the mother substrate 54, and the strain of the strain reduction layer 53 and the semiconductor element layer 51 can be reduced.
Alternatively, when a semiconductor element that generates heat during operation (hereinafter, referred to as a heating element) is used, the semiconductor integrated structure of the present invention may be used to increase the temperature during operation and to reduce the temperature during operation. Strain with distortion can also be reduced. In this case, the use of the heat radiation layer 13 is particularly effective.

The material used for the strain reducing layer 53 preferably has a large Young's modulus, and more preferably has a Young's modulus 2.5 times or more that of the mother substrate 54 used. When a material having a Young's modulus not more than 2.5 times that of the mother board layer is used as the strain reducing layer, the shrinkage of the strain reducing layer when the temperature is lowered after bonding is affected by the mother board or the heat dissipation layer, and the strain is reduced. Deviates from the shrinkage caused by the thermal expansion coefficient inherent to the layer. As a result, the contraction rate of the strain reducing layer does not match the contraction rate of the semiconductor element layer, and the effect of reducing the distortion generated in the semiconductor element layer is diminished. Further, assuming that the material is introduced into a semiconductor process, metal materials such as chromium, molybdenum, and tungsten shown in Table 1 can be used. In this case, a Young's modulus of 2.5 times or more to about 6 times that of a semiconductor can be obtained, which is a practically possible numerical range. Further, the thermal conductivity of these metal materials is smaller than that of gold, copper, and aluminum, which are metal materials suitable for the heat radiation layer 13, but larger than that of the compound semiconductor material, and the heat radiation characteristics are also good. .

The adhesive layer 52 includes the heat radiation layer 13 and the strain reducing layer 5.
Since the thickness is negligibly small as compared with No. 3, it hardly affects the introduction of distortion into the semiconductor element layer 51, and the extent to which the heat radiation characteristic deteriorates is also small. In fact, it is possible for the thickness of the adhesive layer 52 to be less than 0.1 micrometers. As an example, 1 which is 0.1 micrometers thick
The thermal resistance of the square adhesive layer 52 having a side of 50 micrometers is 222 K / W, which is a typical thermal resistance of the laser element.
000 K / W, so that the adhesive layer 52
Has almost no effect on the heat radiation characteristics. Since the bonding layer 52 has a function of mechanically bonding the upper and lower layers, the mother substrate 54 and the semiconductor element can be bonded.

The layer configuration of the first embodiment of the present invention is a configuration in which the heat radiation layer 13 is removed from the layer configuration of the second embodiment. That is, in order from the bottom, the mother substrate 54, the strain reduction layer 53, the adhesive layer 52, and the semiconductor element layer 51. As is clear from the above description, the effect of reducing the strain in the semiconductor element layer 51 is obtained irrespective of the presence or absence of the heat radiation layer 13 due to the large Young's modulus of the strain reducing layer 53.
As in the case of the layer structure of this embodiment, it has the effect of reducing the distortion of the semiconductor element layer 51, and has good heat dissipation characteristics.

The layer configuration of the third embodiment of the present invention is the same as the layer configuration of the first embodiment except that the vertical relationship between the adhesive layer 52 and the strain reducing layer 53 is reversed. That is,
In order from the bottom, a mother substrate 54, an adhesive layer 52, and a strain reduction layer 5
3. The semiconductor element layer 51. As is apparent from the above description, since the influence of the adhesive layer 52 is small, it has the effect of reducing the distortion of the semiconductor element layer 51 and has good heat dissipation characteristics, similarly to the layer configuration of the first embodiment. It is.

The layer configuration of the fourth embodiment of the present invention is the same as that of the second embodiment, as long as the positional relationship between the heat radiation layer 13 and the strain reducing layer 53 is kept the same, that is, the heat radiation layer. This is a structure in which the order of the three layers of the adhesive layer 52, the heat dissipation layer 13, and the strain reducing layer 53 is changed in a range in which the strain reducing layer 53 is closer to the semiconductor element layer 51 than the layer 13. That is, the mother substrate 54, the heat radiation layer 13, the adhesive layer 52, the strain reduction layer 53, and the semiconductor element layer 51 shown in FIG.
And the mother substrate 54, the adhesive layer 52,
Heat dissipation layer 13, strain reduction layer 53, and semiconductor element layer 51
It is. As is clear from the above description, the strain reduction layer 5
As long as the layer 3 directly contacts the semiconductor element layer 51 or contacts the semiconductor element layer 51 only via the adhesive layer 52, the third embodiment has the effect of reducing the distortion of the semiconductor element layer 51, similarly to the layer configuration of the second embodiment. Also, the heat radiation characteristics are good.

As described above, by using the semiconductor integrated structure according to the present invention, when a semiconductor element is integrated on the mother substrate 54 using the high-temperature-curable adhesive layer 52, the semiconductor element caused by the high-temperature bonding is formed. Reduce the introduction of distortion into
A necessary and sufficient heat radiation function can be obtained. Further, it is also possible to reduce distortion that may be introduced by a heat cycle (at the time of temperature rise and temperature fall) due to the operation of the heating element.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An example in which a surface emitting laser is used as a structure of a bonding portion when integrated on a silicon CMOS circuit board will be described in detail. The semiconductor element in this example is a surface emitting laser (heating element) using a gallium arsenide / aluminum gallium arsenide-based material, and a pin photodiode of the same material is also integrated.

FIGS. 7 to 13 show the process steps. FIG.
2 shows a cross-sectional structure of the laser mounting area 12, the CMOS circuit area 18, the photodiode mounting area 19, and the alignment marker area 20 in the silicon CMOS circuit board 15. An alignment marker 28 was set in the alignment marker area 20. FIG. 6 shown earlier is an enlarged view of the laser mounting area 12 in FIG. Laser mounting area 12
CMOS near the photodiode mounting area 19
Two contact electrodes 11 for electrically connecting the circuit and the semiconductor element were provided two each. The element mounting areas (12 and 19) have a square shape with sides of 50 to 100 micrometers, and have an interlayer insulating film 4, a surface passivation film (P-SiN film) 1, a PSG film 2, a P-SiO film 5, and a BPSG film. 7, and a layer having poor thermal conductivity such as a field oxide film 9 is not deposited.
0, Poly-Si layer 8, aluminum first wiring layer (A
L-1) 6 and the aluminum second wiring layer (AL-2) 3. On the other hand, the region sandwiched between the element mounting region and the contact electrode is the field oxide film 9 and the Poly-S
i layer 8, BPSG film 7, aluminum first wiring layer (AL
-1) It is composed of all layers of 6, P-SiO film 5, interlayer insulating film 4, aluminum second wiring layer (AL-2) 3, PSG film 2, and surface passivation (P-SiO) film 1, The region having the largest layer thickness in the CMOS circuit board was used. As a result, the device mounting area became a concave portion having a depth of about 3.3 μm. However, in bonding the semiconductor element onto the concave portion, only the laser mounting region 12 was formed as follows. The semiconductor integrated structure of the present invention was applied to the present invention. That is, first, in order to prevent aluminum of the second wiring layer 3 and the material of the heat radiation layer 13 (for example, gold) from alloying at the time of high-temperature heat treatment and to provide insulation, a 0.3 μm-thick SiN film is used. Film 14 is plasma C
After being deposited on the entire surface of the substrate by the VD method, the heat dissipation layer 13 (gold of 3.0 μm thickness) and the strain reduction layer 53 (with a thickness of 3.0 μm) are formed in the concave portion of the laser mounting portion by using electron beam evaporation and a lift-off method. 0.5 micrometer thick chromium) was sequentially deposited. By making the sum of the thicknesses of the heat radiation layer 13 and the strain reducing layer 53 3.5 μm, and having a structure 0.2 μm thicker than the depth of the concave portion, the semiconductor element layer 51 described below In the bonding process, the layer thickness of the bonding layer polyimide 52 can be suppressed as small as possible. The heat radiation layer 13 and the strain reduction layer 53 are not formed in the photodiode mounting area.

Next, as shown in FIG. 8, the CMOS circuit board is flattened with a flattening polyimide 22. This flattening step includes an embedding step of the flattening polyimide 22, a thermosetting step, a polishing step, and an etch back step (reactive strain etching layer 5) by reactive ion etching (RIE) of oxygen gas.
3 exposing steps).

After this flattening step, as shown in FIG.
Using the adhesive layer polyimide 52, the CMOS circuit board and the epitaxial substrate to be the semiconductor element layer 51 are temporarily bonded with the CMOS circuit side and the epitaxial layer side facing each other. Both substrates are 2 inches in size. The above epitaxial substrate has a cross-sectional structure shown in FIG. Here, the epitaxial substrate has a gallium arsenide substrate 24 and an epitaxial layer 23, and the epitaxial layer 23 includes a layer for a laser and a layer for a photodiode formed in a later step, and has an n-type.
Al _0.6 Ga _0.4 As layer 102, n-InGaP layer 10
3. n-GaAs laser contact layer 104, n-distributed reflection (DBR) layer 105, GaAs / AlGaAs active layer 106, p-DBR layer 107, p-GaAs laser contact layer 108, p-InGaP layer 109, p −
GaAs photodiode contact layer 110, i-
It comprises a GaAs light absorbing layer 111, an n-Al _0.3 Ga _0.7 As layer 112, and a contact layer 113 for an n-GaAs photodiode.

The temporary bonding was performed under a vacuum of 190 ° C. while applying atmospheric pressure. By this pressing, the two substrates could be bonded to each other without any gap, and the thickness of the adhesive layer polyimide 52 on the strain reducing layer 53 could be reduced to about 0.1 μm or less.

After the temporary bonding, the GaAs substrate 24 is entirely removed leaving only the epitaxial layer. In this step, n-
Al _0.6 Ga _0.4 As layer 102 and n-InGaP layer 10
3 was used as an etching stop layer, and the contact layer 104 for n-GaAs laser was exposed on the surface. Therefore,
Since the epitaxial layer at this stage is composed of the n-GaAs laser contact layer 104 to the n-GaAs photodiode contact layer 113, the epitaxial layer is hereinafter referred to as the epitaxial layer 30 in distinction from the epitaxial layer before etching. Next, the epitaxial layer 30 is
10 mm from the chip size of 5 mm
As shown in (1), the alignment marker 28 previously formed on the CMOS circuit board is made visible with visible light. The process of dividing into chip sizes is CMOS
The position of the photomask is adjusted by applying near-infrared illumination from the backside of the substrate, so the alignment accuracy is several micrometers, which is sufficient accuracy in the process of dividing the chip size into millimeters. . At this stage,
Heat to 350 ° C. to completely cure the adhesive layer polyimide 52. Note that the subsequent photolithography is performed using a stepper using the alignment marker 28, so that the alignment accuracy is 0.3 micrometers or less.

Next, as shown in FIG. 11, a process of forming electrodes of a surface emitting laser and etching a mesa is performed. The mesa had a three-stage structure. The etching for forming the upper mesa 31 and the middle mesa 32 is performed by chlorine-based electron cyclotron resonance (E).
CR) -RIE dry etching, p-GaAs
The s-laser contact layer 108 was exposed. Lower mesa 3
3 is performed by wet etching using the p-InGaP layer 109 as an etching stopper layer.
The contact layer 110 for As photodiode was exposed on the surface. Therefore, the upper mesa 31 includes the n-GaAs laser contact layer 104 and the n-distributed reflection (DBR) layer 1.
05, and the GaAs / AlGaAs active layer 106, the middle mesa 32 is formed of the p-DBR layer 107, and the lower mesa 33 is formed of the p-GaAs laser contact layer 108 and the p-InGaP layer 109. . The remaining layer shown as the epitaxial layer 34 is a layer for forming a photodiode, and is formed of p-GaAs.
Photodiode contact layer 110, i-GaAs
A light absorption layer 111, an n-Al _0.3 Ga _0.7 As layer 112,
And contact layer 1 for n-GaAs photodiode
13.

Next, as shown in FIG. 12, the process of forming the electrodes of the photodiode and the mesa etching are performed. The mesa had a two-stage structure. That is, the upper mesa 35 composed of the p-GaAs photodiode contact layer 110, the i-GaAs light absorbing layer 111, and the n-Al _0.3 Ga _0.7 As layer 112, and the n-GaAs photodiode contact layer 113. Lower mesa 36
It is. The etching for forming the upper mesa 35 is performed by n-Al
Wet etching was performed using the _0.3 Ga _0.7 As layer 112 as an etching stop layer to expose the n-GaAs photodiode contact layer 113 on the surface. Lower mesa 36
The etching for the formation is wet etching of the n-GaAs photodiode contact layer 113. By this etching, the epitaxial layer 23 in all regions except for the mesa of the laser and the mesa of the photodiode is completely removed. did it.

Next, as shown in FIG. 13, the flattening polyimide 22 and the adhesive layer polyimide 52 are removed from the region excluding the laser mesa and the photodiode mesa, and the SiN film 14 at the contact electrode portion is further removed. Then, a step wiring polyimide 26 was buried in the periphery of the mesa to make the slope of the step gentle, and then wiring of the semiconductor element and the CMOS circuit was performed by gold plating 25. Finally, it was mounted on a heat sink (copper) 27.

With the above process, a 2-inch CMO
The GaAs surface emitting laser and the photodiode could be integrated on the S circuit board at a high density. By employing the semiconductor integrated structure according to the present invention, it is possible to reduce the introduction of distortion into the surface emitting laser as compared with the case of employing the conventional structure shown in FIG. The initial characteristics of the laser are: threshold current 1
The lifetime was improved from 0 mA to 4 mA, and the lifetime until the laser did not oscillate at all when driven at room temperature CW of 15 mA was improved from several minutes to 100 hours or more. The heat radiation characteristics were comparable to those of the conventional structure, and a thermal resistance value of about 1500 k / W was obtained.

In this embodiment, gold is used for the heat radiation layer 13 and chromium is used for the strain reduction layer 53. However, in consideration of the bonding temperature, the material of the mother substrate 54, and the material of the semiconductor element layer 51, the materials of the heat radiation layer 13 and the strain reduction layer 53 having an appropriate thermal expansion coefficient, Young's modulus, and thermal conductivity can be selected. For example, as a material of the strain reducing layer 53, molybdenum, tungsten, or a chromium-molybdenum alloy is also effective.

In this embodiment, the case where the strain reducing layer 53 is made of only one kind of material has been described. However, it is possible to make the strain reduction layer 53 have a multilayer structure, and to make the thermal expansion coefficient closer to that of the semiconductor element layer 51. In that case, it is effective to use a multilayer structure made of a material having a larger thermal expansion coefficient than the semiconductor element layer 51 and a material having a smaller thermal expansion coefficient. For example, as shown in FIG. 15, the thermal expansion coefficient is 8.4 × 10 ^−6.
/ K and 4.8 × 10 ⁻⁶ / K molybdenum have a multilayer structure composed of gallium arsenide and a thermal expansion coefficient of gallium arsenide (6.
4 × 10 ⁻⁶ / K). Suitable materials for the multi-layer structure can be any combination of suitable materials, including chromium, molybdenum, and tungsten.

In this embodiment, an aluminum gallium arsenide-based semiconductor material is used as the material of the surface emitting laser. Applicable to Further, the semiconductor element is not limited to a surface emitting laser and a pin photodiode, and other elements known in the art (for example, a DFB laser, a GRIN-SCH laser, an MQW laser, etc.) can be used. is there. Further, the semiconductor integrated structure of the present invention is effective in that a non-heating element such as a photodiode is integrated because the effect of reducing distortion is obtained.

In this embodiment, a silicon CMOS circuit board is used as the mother board 54. However, in this technique such as a silicon bipolar circuit board, a compound semiconductor integrated circuit board, other semiconductor integrated circuit boards, and a ceramic wiring board. It can be applied to known mother substrates in general.

[0040]

As described above, the semiconductor integrated structure according to the present invention can be used at a high temperature when a semiconductor element is integrated on a mother substrate such as a semiconductor integrated circuit substrate by a method using a high-temperature curing type adhesive layer. This has the effect of reducing the distortion introduced into the element by the bonding and maintaining good heat dissipation of the element.

[Brief description of the drawings]

FIG. 1 shows a CMOS for bonding and integrating a surface emitting laser.
It is sectional drawing of the structure (conventional structure) of the laser mounting part on the circuit board side.

FIG. 2 is a schematic cross-sectional view of the semiconductor integrated structure according to the first embodiment.

FIG. 3 is a schematic sectional view of a semiconductor integrated structure according to a third embodiment;

FIG. 4 is a schematic sectional view of a semiconductor integrated structure according to a second embodiment;

FIG. 5 is a schematic sectional view of a semiconductor integrated structure according to a fourth embodiment, in which (a) shows a heat radiation layer 1 between a mother substrate and an adhesive layer.
3 is a schematic cross-sectional view in the case of having a heat dissipation layer 13 between the adhesive layer and the strain reducing layer 53. FIG.

FIG. 6 shows a CMOS for bonding and integrating a surface emitting laser.
The structure of the laser mounting portion on the circuit board side (the structure of the embodiment. FIG.
FIG.

FIG. 7 shows a silicon CM in a process step (embodiment) of bonding and integrating a surface emitting laser and a pin photodiode.
FIG. 3 is a cross-sectional view illustrating an OS circuit board.

FIG. 8 is a sectional view showing a silicon CMOS substrate planarized by using planarized polyimide.

FIG. 9 is a cross-sectional view showing a structure in which an epitaxial substrate for forming an element and a silicon CMOS substrate are bonded.

FIG. 10 is a cross-sectional view showing a silicon CMOS substrate on which an epitaxial layer in which an alignment marker is visible with visible light is stacked.

FIG. 11 is a cross-sectional view showing a silicon CMOS substrate on which electrode formation of a surface emitting laser and mesa etching have been performed.

FIG. 12 is a cross-sectional view showing a silicon CMOS substrate on which electrode formation of a photodiode and mesa etching have been performed.

FIG. 13 is a cross-sectional view showing a CMOS device in which a surface emitting laser and a photodiode are integrated at a high density.

FIG. 14 is a cross-sectional view showing a layer configuration (Example) of a GaAs epitaxial substrate.

FIG. 15 is a cross-sectional view of an example in which the strain reduction layer has a multilayer structure.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 plasma silicon nitride (P-SiN) film 2 PSG film 3 aluminum second wiring layer (AL-2) 4 interlayer insulating film 5 plasma silicon oxide (P-SiO) film 6 aluminum first wiring layer (AL-1) 7 BPSG film 8 Poly-Si 9 Field oxide film 10 Gate oxide film 11 Contact electrode 12 Laser mounting area 13 Heat dissipation layer 14 SiN film 15 Silicon CMOS circuit board 18 CMOS circuit area 19 Photodiode mounting area 20 Alignment marker area 22 Flattening polyimide Reference Signs List 23 epitaxial layer 24 GaAs substrate 25 gold plating 26 polyimide for step wiring 27 heat sink (copper) 28 alignment marker 30 epitaxial layer 31 laser upper mesa 32 laser middle mesa 33 laser lower mesa 34 epitaxial layer 35 photoda Diode upper mesa 36 photodiode lower mesas 51 semiconductor element layer 52 adhesive layer 53 distortion reduction layer 54 mother substrate 102 n-Al _0.6 Ga _0.4 As layer 103 n-InGaP layer 104 n-GaAs laser contact layer 105 n-DBR ( DBR) layer 106 GaAs / AlGaAs active layer 107 p-distributed reflection (DBR) layer 108 p-GaAs laser contact layer 109 p-InGaP layer 110 p-GaAs photodiode contact layer 111 i-GaAs light absorption layer 112 n- Al _0.3 Ga _0.7 As layer 113 Contact layer for n-GaAs photodiode 201 Molybdenum 204 Chromium

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Amano Taxes 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Japan Nippon Telegraph and Telephone Corporation F-term (reference) 4M118 AA08 AA10 AB05 BA02 CA05 CB01 CB02 FC03 FC06 5F041 AA33 AA40 CA12 CA36 CB32 5F088 BA20 DA01 EA09 GA03 GA09

Claims (9)

[Claims] 1. A structure in which a mother substrate, a strain reduction layer, an adhesive layer, and a semiconductor element layer are integrated in this order, wherein the strain reduction layer is at least 0.6 times and 1.5 times the semiconductor element layer.
Having a coefficient of thermal expansion of not more than twice, and a Young's modulus of not less than 2.5 times that of the mother substrate, and the adhesive layer has a high-temperature curing property, and mechanically bonds the layers above and below the adhesive layer. A semiconductor integrated structure characterized by having a function to perform. 2. A heat radiation layer made of a material having a thermal conductivity of 200 W / m / K or more between the mother substrate and the strain reducing layer, wherein the heat radiation layer is 0.5 times or more of the mother substrate layer. 2. The semiconductor integrated structure according to claim 1, having a Young's modulus of 1.5 times or less. 3. A structure in which a mother substrate, an adhesive layer, a strain reduction layer, and a semiconductor element layer are integrated in this order, wherein the strain reduction layer is at least 0.6 times and 1.5 times the semiconductor element layer.
Having a coefficient of thermal expansion of not more than twice, and a Young's modulus of not less than 2.5 times that of the mother substrate, and the adhesive layer has a high-temperature curing property, and mechanically bonds the layers above and below the adhesive layer. A semiconductor integrated structure characterized by having a function to perform. 4. A thermal conductivity between the mother substrate and the adhesive layer or between the adhesive layer and the strain reducing layer is 20.
4. The heat radiation layer according to claim 3, further comprising a heat radiation layer made of a material of 0 W / m / K or more, wherein the heat radiation layer has a Young's modulus of 0.5 times or more and 1.5 times or less of the mother substrate layer. Semiconductor integrated structure. 5. The semiconductor element layer, wherein the strain reduction layer is a multilayer structure or an alloy made of a material having a larger coefficient of thermal expansion than a coefficient of thermal expansion of the semiconductor element layer and a material having a smaller coefficient of thermal expansion. The semiconductor integrated structure according to any one of claims 1 to 4, having a thermal expansion coefficient of 0.6 times or more and 1.5 times or less of the following. 6. The semiconductor integrated structure according to claim 1, wherein a semiconductor integrated circuit substrate is used as said mother substrate. 7. A thermal conductivity of 40 W / m / K from the semiconductor integrated circuit board to a region where a semiconductor element is mounted.
7. The method according to claim 6, wherein the strain reducing layer and the heat dissipation layer are selectively deposited or bonded in a concave portion formed by removing a component made of the following material. Semiconductor integrated structure. 8. The semiconductor integrated structure according to claim 1, wherein a vertical cavity surface emitting laser made of a compound semiconductor is used as the semiconductor element layer. 9. A silicon integrated circuit substrate is used as the mother substrate, and gallium arsenide /
An aluminum gallium arsenide-based semiconductor material is used, and as the strain reducing layer, a metal material selected from the group consisting of chromium, molybdenum, and tungsten, a multilayer structure thereof, or an alloy thereof is used. Item 9. A semiconductor integrated structure according to item 8.