JP2000223227A - Board for inspecting ic - Google Patents
Board for inspecting icInfo
- Publication number
- JP2000223227A JP2000223227A JP11024321A JP2432199A JP2000223227A JP 2000223227 A JP2000223227 A JP 2000223227A JP 11024321 A JP11024321 A JP 11024321A JP 2432199 A JP2432199 A JP 2432199A JP 2000223227 A JP2000223227 A JP 2000223227A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- contact pad
- board
- contact
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Connecting Device With Holders (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、例えば、両端にプ
ランジャを持つポゴコンタクトピンを備えたＢＧＡ（ボ
ールグリッドアレイ）ソケット用のプリント配線基板の
ようなＩＣ検査用基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC inspection board such as a printed circuit board for a BGA (ball grid array) socket having a pogo contact pin having plungers at both ends.
【０００２】[0002]
【従来の技術】ＢＧＡ用ＩＣソケットに、両端にプラン
ジャを持つポゴコンタクトピンを採用し、片方のプラン
ジャをプリント基板上に設けられたコンタクトパッドに
圧接し、もう片方のプランジャをＢＧＡのバンプに圧接
し電気的な接続を行っているものがある。2. Description of the Related Art Pogo contact pins having plungers at both ends are employed in a BGA IC socket, and one plunger is pressed against a contact pad provided on a printed circuit board, and the other plunger is pressed against a BGA bump. Some are making electrical connections.
【０００３】[0003]
【発明が解決しようとする課題】しかし、図３に示す通
り、従来、内層配線ａを有するプリント配線基板ｂ上の
コンタクトパッドｃは、スルーホールｄに隣接する位置
に設けられており、１ピン当たりの占めるスペースが大
きく、最近のＢＧＡのバンプ狭ピッチ化において、プリ
ント配線基板ｂ上に狭ピッチバンプに対応するコンタク
トパッドｃを設けることが困難になっている。なお、図
中符号ｅはポゴコンタクトピンのプランジャを示してい
る。However, as shown in FIG. 3, conventionally, a contact pad c on a printed wiring board b having an inner layer wiring a is provided at a position adjacent to a through hole d, and one pin is provided. The space occupied by the bumps is large, and it has become difficult to provide the contact pads c corresponding to the narrow pitch bumps on the printed wiring board b in recent narrowing of the bump pitch of the BGA. In the drawings, reference symbol e indicates a plunger of a pogo contact pin.
【０００４】本発明は、上記事情に鑑みてなされたもの
で、その目的とするところは、１ピン当たりの占めるス
ペースを小さくすることができ、プリント配線基板上に
狭ピッチバンプに対応するコンタクトパッドを容易に設
けることができるＩＣ検査用基板を提供することにあ
る。The present invention has been made in view of the above circumstances, and an object of the present invention is to reduce a space occupied by one pin and to provide a contact pad corresponding to a narrow pitch bump on a printed wiring board. It is an object of the present invention to provide an IC inspection substrate which can easily provide a substrate.
【０００５】[0005]
【課題を解決するための手段】本発明の請求項１は、コ
ンタクトピンに接触するコンタクトパッドを備えたＩＣ
検査用基板において、基板に設けられたスルーホール内
に、樹脂または導電性ペーストのような充填材を充填
し、上記スルーホール上に上記コンタクトパッドを形成
したことを特徴とする。本発明の請求項２は、基板とし
て内層配線を有するプリント配線基板を用い、このプリ
ント配線基板上に、両端にプランジャを持つポゴコンタ
クトピンを設けたＢＧＡ用ＩＣソケットを搭載したこと
を特徴とする。According to the first aspect of the present invention, there is provided an IC having a contact pad for contacting a contact pin.
In the inspection substrate, a filler such as a resin or a conductive paste is filled in a through hole provided in the substrate, and the contact pad is formed on the through hole. According to a second aspect of the present invention, a printed circuit board having an inner layer wiring is used as a substrate, and a BGA IC socket provided with pogo contact pins having plungers at both ends is mounted on the printed circuit board. .
【０００６】[0006]
【発明の実施の形態】本発明のＩＣ検査用基板の一実施
形態について、ＢＧＡを例にとり、図１、図２を参照し
て説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of an IC inspection board according to the present invention will be described with reference to FIGS. 1 and 2, taking a BGA as an example.
【０００７】図１は、本発明の一実施形態を示す断面図
である。プリント配線基板１に設けられたスルーホール
２には、充填材として樹脂３、または導電性ペーストが
充填され硬化したもので埋められている。そのスルーホ
ール２上にコンタクト用のパッド４を作成し、このコン
タクトパッド４はスルーホール２を通じプリント配線基
板１の内層配線５と電気的に接続されている。スルーホ
ール２への樹脂３の充填は、両端に出没可能なプランジ
ャ６を持つポゴコンタクトピン７の一方のプランジャ６
の圧接によってコンタクトパッド４が陥没するのを防止
するために行っている。FIG. 1 is a sectional view showing one embodiment of the present invention. The through-hole 2 provided in the printed wiring board 1 is filled with a resin 3 or a conductive paste as a filler and cured and filled. A contact pad 4 is formed on the through hole 2, and the contact pad 4 is electrically connected to the inner layer wiring 5 of the printed wiring board 1 through the through hole 2. The filling of the resin 3 into the through hole 2 is performed by using one of the plungers 6 of the pogo contact pins 7 having plungers 6 which can protrude and retract at both ends.
This is performed to prevent the contact pad 4 from being depressed by the pressure contact.
【０００８】次に、本発明の一実施形態の動作を図２に
示す ＢＧＡ ＩＣ用ソケット断面図を使って説明す
る。ＩＣソケット１０を搭載したプリント配線基板１を
ＬＳＩテスタのテストヘッドにセットし、ＢＧＡ１１を
フローティングプレート１２に搭載し、加圧ヘッド１３
で押さえ、両端にプランジャ６を持つポゴコンタクトピ
ン７の一方のプランジャ６をバンプ１４にコンタクトさ
せる。両端にプランジャ６を持つポゴコンタクトピン７
のもう一方のプランジャ６は、プリント配線基板１上の
コンタクトパッド４と圧接し、穴埋めされたスルーホー
ル２を通じてプリント配線基板１の内層配線５に接続さ
れＬＳＩテスタと電気的に接続される。なお、図２中符
号１５は、ＩＣソケット１０をプリント配線基板１に固
定するソケット固定ネジである。このようにして、ＩＣ
ソケット１０に装着されたＢＧＡ１１を円滑にＬＳＩテ
スタにて検査することができる。Next, the operation of the embodiment of the present invention will be described with reference to the sectional view of the BGA IC socket shown in FIG. The printed wiring board 1 on which the IC socket 10 is mounted is set on the test head of the LSI tester, the BGA 11 is mounted on the floating plate 12, and the pressure head 13
, And one of the pogo contact pins 7 having the plungers 6 at both ends is brought into contact with the bumps 14. Pogo contact pins 7 with plungers 6 at both ends
The other plunger 6 is pressed into contact with the contact pad 4 on the printed wiring board 1, is connected to the inner layer wiring 5 of the printed wiring board 1 through the filled through hole 2, and is electrically connected to the LSI tester. Reference numeral 15 in FIG. 2 denotes a socket fixing screw for fixing the IC socket 10 to the printed wiring board 1. Thus, the IC
The BGA 11 mounted on the socket 10 can be smoothly inspected by the LSI tester.
【０００９】[0009]
【発明の効果】以上、説明したように、本発明によれ
ば、プリント配線基板のスルーホールを樹脂等で埋め、
その上にコンタクトパッドを設けることにより、高価な
ビルドアップ基板を使用することなく、コンタクトピン
を狭ピッチに配列することが、安価なプリント配線基板
で可能になった。As described above, according to the present invention, the through holes of the printed wiring board are filled with resin or the like.
By providing the contact pads thereon, it has become possible to arrange the contact pins at a narrow pitch with an inexpensive printed wiring board without using an expensive build-up board.
【図１】 本発明の一実施形態を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図２】 本発明の一実施形態の動作を示す ＢＧＡ
ＩＣ用ソケット断面図である。FIG. 2 is a BGA showing the operation of one embodiment of the present invention.
It is IC socket sectional drawing.
【図３】 従来のコンタクトパッドを示す断面図であ
る。FIG. 3 is a sectional view showing a conventional contact pad.
１ プリント配線基板 ２ スルーホール ３ 樹脂（充填材） ４ コンタクトパッド ５ 内層配線 ６ プランジャ ７ ポゴコンタクトピン １０ ＩＣソケット １１ ＢＧＡ DESCRIPTION OF SYMBOLS 1 Printed wiring board 2 Through hole 3 Resin (filling material) 4 Contact pad 5 Inner layer wiring 6 Plunger 7 Pogo contact pin 10 IC socket 11 BGA
Claims (2)
ッドを備えたＩＣ検査用基板において、 基板に設けられたスルーホール内に、樹脂または導電性
ペーストのような充填材を充填し、上記スルーホール上
に上記コンタクトパッドを形成したことを特徴とするＩ
Ｃ検査用基板。An IC inspection board having a contact pad contacting a contact pin, wherein a through-hole provided in the board is filled with a filler such as resin or conductive paste, and the through-hole is formed on the through-hole. I wherein the contact pad is formed.
C inspection board.
線基板を用い、このプリント配線基板上に、両端にプラ
ンジャを持つポゴコンタクトピンを設けたＢＧＡ用ＩＣ
ソケットを搭載したことを特徴とする請求項１記載のＩ
Ｃ検査用基板。2. A BGA IC in which a printed wiring board having an inner layer wiring is used as a substrate, and pogo contact pins having plungers at both ends are provided on the printed wiring board.
The I according to claim 1, wherein a socket is mounted.
C inspection board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11024321A JP2000223227A (en) | 1999-02-01 | 1999-02-01 | Board for inspecting ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11024321A JP2000223227A (en) | 1999-02-01 | 1999-02-01 | Board for inspecting ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000223227A true JP2000223227A (en) | 2000-08-11 |
Family
ID=12134931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11024321A Pending JP2000223227A (en) | 1999-02-01 | 1999-02-01 | Board for inspecting ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000223227A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005308685A (en) * | 2004-04-26 | 2005-11-04 | Hitachi Ulsi Systems Co Ltd | Manufacturing method for semiconductor device, and test tool used therefor |
-
1999
- 1999-02-01 JP JP11024321A patent/JP2000223227A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005308685A (en) * | 2004-04-26 | 2005-11-04 | Hitachi Ulsi Systems Co Ltd | Manufacturing method for semiconductor device, and test tool used therefor |
| JP4512407B2 (en) * | 2004-04-26 | 2010-07-28 | 株式会社日立超エル・エス・アイ・システムズ | Operation test method of semiconductor device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20000919 |