JP2000208776A - Manufacture of thin-film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To activate impurities implanted in a semiconductor thin-film, without degrading the characteristics of a thin-film transistor. SOLUTION: A laminated structure is provided, wherein a semiconductor thin film 5, a gate insulating film 3 stacked on its one surface, and a gate electrode 1 stacked on the semiconductor thin film 5 via the gate insulating film 3 are included. Here, a film forming process, where the semiconductor thin film 5 is film-formed on an insulating substrate 0, a crystallizing process where the semiconductor thin film 5 is irradiated with laser beam 50 for crystallization, an implantation process where impurity is implanted in a crystallized semiconductor thin film 5, and an activating process where the semiconductor thin film 5 is heated by a heating method (RTA) using a lamp as heat source for activating the implanted impurity are provided. The implantation process comprises a process, wherein a specified impurity is implanted at specified concentration into the semiconductor thin film 5 for controlling the threshold voltage of a thin-film transistor, and the activating process that uses RTA activates at least the impurity implanted for threshold voltage control.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor using a semiconductor thin film such as polycrystalline silicon formed on an insulating substrate as an active layer. For example, the present invention relates to a method for manufacturing a thin film transistor used as a switching element of an active matrix display device. More specifically, a low-temperature process (for example, a process maximum temperature is 60
0 ° C. or lower). More specifically, the present invention relates to a technique for activating an impurity implanted at a low concentration into a semiconductor thin film serving as an active layer of a thin film transistor.

[0002]

2. Description of the Related Art Thin film transistors are widely used as switching elements in active matrix type liquid crystal display devices. In particular, polycrystalline silicon has been conventionally used as a semiconductor thin film serving as an active layer of a thin film transistor.
The polycrystalline silicon thin film transistor can be used not only as a switching element but also as a circuit element, and a peripheral driving circuit can be built on the same substrate together with the switching element. Further, since the polycrystalline silicon thin film transistor can be miniaturized, the area occupied by the switching element in the pixel structure can be reduced, and a high aperture ratio of the pixel can be achieved. By the way, conventionally, a polycrystalline silicon thin film transistor has a process maximum temperature of about 1000 ° C. in a manufacturing process, and quartz glass or the like having excellent heat resistance has been used as an insulating substrate. It has been difficult to use a glass substrate having a relatively low melting point due to the manufacturing process. However, in order to reduce the cost of the liquid crystal display device, it is essential to use a low melting point glass material. Therefore, in recent years, the development of a so-called low-temperature process in which the maximum process temperature is 600 ° C. or lower has been promoted. In particular, the low-temperature process is extremely advantageous in terms of cost when manufacturing a large-sized liquid crystal display device.

[0003] As part of the low-temperature process,
Conventionally, ion shower technology that can implant impurities
Has been issued. In ion showers, mass separation
Ionized ions into a large area semiconductor thin film
Can be injected. However, mass non-separable type ion
In the shower device, the target impurities (dopants)
Other ions (hydrogen ions, etc.) are also implanted at the same time
1 × 10¹⁴/ Cm ^TwoPrecise control of low doses below
It was difficult to do. 1 × 10¹⁴/ Cm^TwoLess than
Injecting impurities with a dose
It is necessary for the threshold voltage control. Large area liquid crystal display
Ray manufacturing, especially active matrix liquid crystal displays
The thin film transistor used for the play is processed at a process temperature of 6.
When manufacturing at a temperature of 00 ° C. or less, the threshold voltage (Vth) is controlled.
Is essential to guarantee the desired electrical characteristics.
You. However, the conventional ion shower system has a low dose.
Dose cannot be controlled accurately. For this reason,
In recent years, semiconductor thin films formed on large-area insulating substrates
To be able to implant mass-separated impurity ions.
Implantation devices have been developed. example
If impurity ions are formed in a 300 to 600 nm line shape,
According to the method of performing mass separation while forming into a beam, 6
Even on a large glass substrate of about 00 × 720 mm square
Equipment that enables ion implantation at low dose has been developed
I have. In the present specification, such an ion implanter
Thin film transistor threshold at low dose using
V for ion implantation for voltage control
This is referred to as th ion implantation. What
This technique is disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 3-6865.
Have been.

[0004]

In a conventional low-temperature process, a so-called laser annealing method is used to obtain a semiconductor thin film made of polycrystalline silicon. First, after amorphous silicon or microcrystalline silicon is formed on an insulating substrate, the silicon is once melted by excimer laser light irradiation and then crystallized in a cooling process. Laser annealing is a technique in which only a semiconductor thin film is selectively heated without substantially thermally damaging a substrate, and amorphous silicon or microcrystalline silicon is converted to polycrystalline silicon. By the way, the conventional low-concentration impurity implantation for controlling the threshold voltage is performed before the crystallization of the semiconductor thin film to be the active layer of the thin film transistor. That is, the semiconductor thin film in the state of amorphous silicon or microcrystalline silicon is doped with impurities. Thereafter, by irradiating the semiconductor thin film with excimer laser light,
At the same time as the crystallization, the impurities were activated. Generally, an impurity doped in a semiconductor thin film functions by activation. When the semiconductor thin film is melted and crystallized by excimer laser light irradiation, the pre-doped impurities are also mixed in the molten crystal and incorporated into the crystal structure when re-solidified, so that relatively efficient activation is performed. I was However, if the crystallization of the semiconductor thin film and the activation of impurities are performed simultaneously, not only the target species but also unnecessary metal elements are mixed, and the unnecessary metal elements are activated by irradiation with strong laser light. Therefore, the characteristics of the thin film transistor may be deteriorated.

[0005]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and has as its object to activate impurities implanted in a semiconductor thin film without deteriorating the characteristics of a thin film transistor. It is. The following measures were taken to achieve this purpose. That is, a semiconductor thin film,
A method of manufacturing a thin film transistor having a stacked structure including a gate insulating film overlaid on one surface thereof and a gate electrode overlaid on a semiconductor thin film via the gate insulating film, wherein the semiconductor thin film is formed on an insulating substrate. A film forming step, a crystallization step of irradiating the semiconductor thin film with an energy beam to crystallize the semiconductor thin film, an implantation step of implanting impurities into the crystallized semiconductor thin film, and a heating method using a lamp as a heat source. And activating the implanted impurities by heating the thin film. Specifically, the implantation step includes a step of implanting a predetermined impurity into the semiconductor thin film at a predetermined concentration in order to control a threshold voltage of the thin film transistor, and the activation step is performed at least for controlling the threshold voltage. Activated impurities. Further, the implanting step includes implanting a predetermined impurity at a predetermined concentration into the semiconductor thin film to form an impurity region having a lower concentration than the drain region between the channel region and the drain region of the thin film transistor, The activation step is characterized in that the impurities implanted between the channel region and the drain region are activated simultaneously with the activation of the impurities implanted for controlling the threshold voltage. In addition, the crystallization step irradiates an energy beam composed of a laser beam to once melt the semiconductor thin film and then performs crystallization in a cooling process. The activation step irradiates ultraviolet light radiated from a lamp to emit the semiconductor thin film. Is heated at a temperature lower than the melting point to activate the impurities.

According to the present invention, a semiconductor thin film made of amorphous silicon or microcrystalline silicon is irradiated with an energy beam such as an excimer laser beam to crystallize the semiconductor thin film, and then an impurity for adjusting a threshold voltage is implanted. ing. Thereafter, the semiconductor thin film is heated by a heating method using a lamp as a heat source to activate the impurities. The so-called rapid heating method (RTA) using an ultraviolet lamp has a lower energy density than the annealing (ELA) using excimer laser light, and can activate impurities without melting the semiconductor thin film. Therefore, there is little possibility that unnecessary metal elements other than the target species are unnecessarily activated, and impurities selected for adjusting the threshold voltage can be effectively activated.

[0007]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a process chart showing a first embodiment of a method for manufacturing a thin film transistor according to the present invention. In this embodiment, a method of manufacturing an n-channel type thin film transistor is described for convenience, but the same applies to a p-channel type thin film transistor only by changing the impurity species (dopant species). Here, a method for manufacturing a thin film transistor having a bottom gate structure is described. First, as shown in (a), Al, Ta, Mo, W, Cr, Cu or an alloy thereof is formed on an insulating substrate 0 made of glass or the like to a thickness of 100 to 200 nm, and is patterned to form a gate electrode 1. Process into

Next, as shown in FIG. 1B, a gate insulating film is formed on the gate electrode 1. In the present embodiment, the gate insulating film is a gate nitride film 2 (SiN _x ) / gate oxide film 3
A (SiO ₂ ) two-layer structure was used. The gate nitride film 2 is made of S
A film was formed by a plasma CVD method (PCVD method) using a mixture of iH ₄ gas and NH ₃ gas as a source gas. still,
Atmospheric pressure CVD or reduced pressure CVD instead of plasma CVD
May be used. In the present embodiment, the gate nitride film 2 is
Deposited at a thickness of 0 nm. Subsequent to the formation of the gate nitride film 2, a gate oxide film 3 is formed with a thickness of about 200 nm. Further, a semiconductor thin film 5 made of amorphous silicon was continuously formed on the gate oxide film 3 to a thickness of about 30 to 80 nm. Double-layered gate insulating film and amorphous semiconductor thin film 5
Formed a continuous film without breaking the vacuum system of the film forming chamber. When the plasma CVD method is used for the above film formation, a so-called heat treatment is performed in a nitrogen atmosphere at a temperature of 400 to 450 ° C. for about 1 hour to release hydrogen contained in the amorphous semiconductor thin film 5. Dehydrogenation annealing is performed. In addition, plasma CV
In the case of the method D, microcrystalline silicon may be deposited instead of amorphous silicon by changing film forming conditions. Alternatively, in this film forming step, low pressure CVD is used instead of the plasma CVD method.
Amorphous silicon or polycrystalline silicon having a relatively small particle size may be formed by a method. Thereafter, a laser beam 50 is irradiated to crystallize the amorphous or microcrystalline semiconductor thin film 5. An excimer laser beam can be used as the laser beam 50. So-called laser annealing is an effective means for crystallizing a semiconductor thin film at a process temperature of 600 ° C. or less. In the present embodiment, crystallization is performed by irradiating the semiconductor thin film 5 with laser light 50 that is excited in a pulse shape and shaped into a rectangular shape or a band shape.

Next, as shown in FIG. 1C, Vth ion implantation is performed for the purpose of controlling the threshold voltage (Vth) of the thin film transistor. In this example, B + is ion-implanted at a dose of about 1 × 10 ^{12 to} 6 × 10 ¹² / cm ² . The acceleration voltage at this time is, for example, about 10 keV. After that, the semiconductor thin film 5 is patterned according to the element region of each thin film transistor.

Subsequently, on the semiconductor thin film 5 crystallized in the previous step (b) and implanted with impurities for adjusting the threshold voltage,
For example, SiO ₂ is formed with a thickness of about 100 nm to 300 nm by a plasma CVD method. This SiO ₂ is patterned into a predetermined shape and processed into an etching stopper film 6. In this case, the etching stopper film 6 is patterned so as to be aligned with the gate electrode 1 using a backside exposure technique. The portion of the polycrystalline semiconductor thin film 5 located immediately below the etching stopper film 6 is protected as a channel region Ch. As described above, the channel region Ch has Vth
B + ions are implanted at a relatively low dose by ion implantation. Subsequently, impurities (for example, P + ions) are implanted into the semiconductor thin film 5 by ion doping using the etching stopper film 6 as a mask, and LD
A D region is formed. The dose at this time is, for example, 6 × 1
0 ^{12 to} 5 × 10 ¹³ / cm ² . Further, after a photoresist is formed by patterning so as to cover the stopper film 6 and the LDD regions on both sides thereof, impurities (for example, P + ions) are implanted at a high concentration using the photoresist as a mask to form a source region S and a drain region D. . For impurity implantation, for example, ion doping (ion shower) can be used. This is to implant impurities by electric field acceleration without applying mass separation, and in this embodiment, 1 × 10 ¹⁵
An impurity was implanted at a dose of about / cm ² to form a source region S and a drain region D. Although not shown,
When forming a p-channel thin film transistor, n
After covering the region of the channel type thin film transistor with the photoresist, the impurities may be switched from P + ions to B + ions and ion-doped with a dose of about 1 × 10 ¹⁵ / cm ² . Here, the impurities may be implanted using a mass separation type ion implantation apparatus.

Thereafter, the impurities implanted into polycrystalline semiconductor thin film 5 are activated by RTA 60. The impurities include B + ions for adjusting the threshold voltage, P + ions implanted into the LDD region, and P + ions implanted into the source region S and the drain region D at a high concentration. All impurities are now activated collectively by RTA 60. However,
The present invention is not limited to this, and may be activated by the RTA 60 at the stage when each impurity is implanted. Conventionally, laser activation annealing using an excimer laser has been performed for the activation process. In the present invention, the impurity is activated by using a rapid heating method (RTA) instead. The RTA 60 activates impurities by irradiating the polycrystalline semiconductor thin film 5 with light having a wavelength in the ultraviolet region for a short time. Since the RTA has excellent heating temperature uniformity, there is an advantage that variation in electric resistance in the LDD region is suppressed and throughput is faster than laser activation annealing using an excimer laser. In laser activation annealing, a glass substrate is irradiated while scanning with an excimer laser pulse, whereas in RTA, ultraviolet light emitted from an arc lamp is used for a very short time (for example, about 1 second).
The glass substrate is instantaneously irradiated to rapidly heat the polycrystalline semiconductor thin film 5. The temperature rise of the semiconductor thin film 5 due to the RTA 60 is at most about 1100 ° C., which is far below the melting point of silicon, 1400 ° C. Therefore, since activation by RTA does not involve melting of the semiconductor thin film 5, unnecessary activation of unnecessary mixed metal elements does not occur.

[0012] As shown in the last (d), the the SiO ₂ about 2
The interlayer insulating film 7 is formed with a thickness of 00 nm. After the formation of the interlayer insulating film 7, SiN _x is applied for about 20
A film having a thickness of 0 to 400 nm is formed as a passivation film (cap film) 8. At this stage, heat treatment at about 350 ° C. is performed for 1 hour in a nitrogen gas, a forming gas, or a vacuum atmosphere to diffuse hydrogen atoms contained in the interlayer insulating film 7 into the semiconductor thin film 5. Before the above-described hydrogenation, a contact hole is opened in the interlayer insulating film 7, Mo, Al, or the like is sputtered to a thickness of 200 to 400 nm, patterned into a predetermined shape, and processed into the wiring electrode 9. Further, after a flattening layer 10 made of an acrylic resin or the like is applied on the passivation film 8 to a thickness of about 1 μm, another contact hole is opened. ITO or IX on the flattening layer 10
After sputtering a transparent conductive film made of O or the like, it is patterned into a predetermined shape and processed into the pixel electrode 11.

FIG. 2 shows an RT used in the rapid heating method described above.
A device is shown. RTA has a wavelength of 240 to 400
This is a technology that enables high-temperature heat treatment without damaging the substrate itself by irradiating ultraviolet light of nm instantaneously (about 1 second) to the insulating substrate 0 made of glass or the like. As shown in the drawing, the insulating substrate 0 is preheated (gradually heated) stepwise in zones 1 to 3 in which infrared heaters 71 to 73 including infrared lamps or the like are arranged. This insulating substrate 0
Is transported at a predetermined speed, and is sent to an RTA unit sandwiched between Xe arc lamps 81 at the top and bottom. Each arc lamp 8
Numeral 1 is covered by a reflection plate 82, and a radiation thermometer 83 for control is arranged in the vicinity thereof. The semiconductor thin film formed on the insulating substrate 0 made of glass or the like absorbs ultraviolet light emitted from the
Heated to about ° C. After passing through the RTA unit, the insulating substrate 0 is also transported to the cooling zone 4 where the infrared heater 74 is arranged, where it is gradually cooled. Process temperature is R
Radiation thermometer 83 arranged immediately before and after the TA unit
Measure with The process temperature of the RTA is determined by the output (power) of the Xe arc lamp 81 in the RTA unit, the power of the infrared heaters 71 to 73 arranged in the residual heat treatment zone,
The transfer speed of the insulating substrate 0 is determined by three parameters. R
The optimum conditions for the TA conditions vary depending on the material of the glass material used, the thickness of the glass, the size of the substrate, and the like. If the optimum conditions are not satisfied, the temperature gradient in the insulating substrate 0 becomes large, and the insulating substrate 0 may be thermally contracted.

FIG. 3 is a process chart showing a second embodiment of the method for manufacturing a thin film transistor according to the present invention. Unlike the first embodiment, this embodiment forms a thin film transistor having a top gate structure. First, as shown in (a), two layers of base films 6a and 6 serving as buffer layers are formed on an insulating substrate 0.
b is continuously formed by a plasma CVD method. The first underlayer 6a is made of SiN _x and has a thickness of 100 to 2 nm.
00 nm. The second underlayer 6b is made of SiO ₂ and has a thickness of 100 to 200 nm. A semiconductor thin film 5 made of amorphous silicon is formed on the base film 6b made of SiO ₂ by plasma CVD or LPCVD to a thickness of about 30 to 80 nm. Here, the size of the insulating substrate 0 made of glass or the like is 600 × 720 mm ² . When the plasma CVD method is used to form the semiconductor thin film 5 made of amorphous silicon, the film is deposited in a nitrogen atmosphere to remove hydrogen from the film.
Anneal at about 00 ° C. to 450 ° C. for about 1 hour. Then, the amorphous silicon is crystallized by irradiation with a laser beam 50 to be converted into polycrystalline silicon.

Subsequently, as shown in FIG. 1B, the semiconductor thin film 5 converted into polycrystalline silicon is patterned in an island shape. On this, Si is formed by plasma CVD, normal pressure CVD, low pressure CVD, ECR-CVD, sputtering, etc.
O ₂ is grown to 50 to 400 nm to form a gate insulating film 3. Here, Vth ion implantation is performed to remove B + ions from, for example, a dose of 0.5 × 10 ^{12 to}
It is implanted into the semiconductor thin film 5 at about 4 × 10 ¹² / cm ² . The acceleration voltage in this case is about 80 KeV. In addition, this V
The th ion implantation may be performed before the gate insulating film 3 is formed. After performing Vth ion implantation in this manner, the semiconductor thin film 5 is heated by a heating method using a lamp as a heat source (RTA 60) to activate the implanted impurities.

Next, as shown in FIG.
, Ti, Mo, W, Ta, doped polycrystalline silicon
Recon or other alloys of 200 to 800
film with a thickness of nm,
The electrode 1 is processed. Next, P + ions are used for mass separation.
Into the semiconductor thin film 5 by the ion implantation method,
Is provided. This ion implantation is performed using the gate electrode 1 as a mask.
To the entire surface of the insulating substrate 0. Dose amount is 6 × 1
0¹²~ 5 × 10¹³/ Cm^Two And generally 1 × 10
¹⁴/ Cm^Two The following low concentration. Note that the gate electrode 1
The underlying channel region Ch is protected and Vt
Pre-implanted at RT and at RT
B + ion activated in A60 is held as it is
I have. After ion implantation into the LDD region, the gate electrode 1
And a resist pattern is formed so as to cover the periphery thereof,
+ Ion non-mass separation type ion shower doping method
And the source region S and the drain region D are implanted at a high concentration.
Form. The dose in this case is, for example, 1 × 10¹⁵/ C
m^Two It is about. 20% of hydrogen dilution in doping gas
PH_Three Gas was used. When forming CMOS circuits
Uses a resist pattern for p-channel thin film transistors.
After formation, doping gas is doped with 5% to 20% B _Two H₆ /
H_Two Switch to gas system, dose 1 × 10¹⁵Or 3 × 1
0¹⁵/ Cm^TwoIon implantation may be performed to the degree. The source
The formation of the region S and the drain region D is performed by mass separation type ions.
An injection device may be used. After that, the semiconductor thin film 5 is injected.
This is the step of activating the dopant. This activation process
Can use the RTA 60 as in the first embodiment.
Wear. In this embodiment, RTA 60 is performed twice.
Activation of the impurity for adjusting the threshold voltage and LDD
Region and the source region S and the drain region D
The activation of the pure substance is performed.

Thereafter, as shown in FIG.
SiO to cover_Two The interlayer insulating film 7 made of
The film is formed with a thickness of nm. Contact this interlayer insulating film 7
Open a hole and sputter Mo, Al, etc. on it.
After forming a film by patterning,
Process into 9 SiN so as to cover this wiring electrode 9 _x 
Is deposited to a thickness of about 100 to 400 nm by a plasma CVD method.
The passivation film (cap film) 8 is used. At this stage
Anneal for about 1 hour at 350 ° C in raw gas
The hydrogen contained in the insulating film 7 is diffused into the semiconductor thin film 5
You. Further, the flattening layer 10 made of an acrylic resin or the like is formed by about 1
After coating with a thickness of μm, open a contact hole in this
You. Transparent conductive from ITO, IXO, etc. on the planarization layer 10
Sputter the electrolytic film and pattern it into a predetermined shape
The pixel electrode 11 is processed.

Finally, an example of an active matrix type display device using the thin film transistor manufactured in the first embodiment or the second embodiment will be described with reference to FIG. As shown in the drawing, this display device has a pair of insulating substrates 101 and 102.
And a electro-optical substance 103 held between them. As the electro-optical material 103, for example, a liquid crystal material is used. On the lower insulating substrate 101, a pixel array section 104 and a drive circuit section are integrally formed.
The drive circuit section includes a vertical drive circuit 105 and a horizontal drive circuit 106
And divided into A terminal 107 for external connection is formed at the upper end of the peripheral portion of the insulating substrate 101. The terminal portion 107 is connected to a vertical drive circuit 105 and a horizontal drive circuit 106 via a wiring 108. Pixel array unit 104
, A row-shaped gate wiring 109 and a column-shaped signal wiring 110 are formed. A pixel electrode 111 and a thin film transistor 112 for driving the pixel electrode 111 are formed at the intersection of the two wires. The gate electrode of the thin film transistor 112 is connected to the corresponding gate wiring 109, the drain region is connected to the corresponding pixel electrode 111, and the source region is connected to the corresponding signal wiring 110. The gate wiring 109 is connected to the vertical driving circuit 105, while the signal wiring 110 is connected to the horizontal driving circuit 106. The thin film transistor 112 for switching and driving the pixel electrode 111 and the thin film transistors included in the vertical drive circuit 105 and the horizontal drive circuit 106 are formed according to the present invention. These thin film transistors have a laminated structure including a semiconductor thin film, a gate insulating film overlaid on one surface thereof, and a gate electrode overlaid on the semiconductor thin film via the gate insulating film. The semiconductor thin film is crystallized by being irradiated with an energy beam such as a laser beam after being formed on the insulating substrate 101, and impurities implanted in the crystallized semiconductor thin film are
It is activated by a rapid heating method using a lamp as a heat source.

[0019]

As described above, according to the present invention, after a semiconductor thin film is crystallized by laser annealing, impurities for adjusting a threshold voltage or the like are implanted, and a rapid heating method (RTA) using a lamp is performed. ) Is trying to activate it. In order to simultaneously perform crystallization and activation with laser light as in the past, it is necessary to melt all regions where impurities exist,
For this reason, the thickness of the semiconductor thin film could not be increased. On the other hand, in the present invention, RTA is used at the time of activation, and it is not necessary to melt the semiconductor thin film. Therefore, it is possible to increase the film thickness. Further, since the RTA does not reach a very high temperature, there is no fear that metal elements other than the target species mixed during doping are unnecessarily activated. In addition, if crystallization and activation are performed simultaneously by laser annealing as in the past,
Not only does the size of the crystal grains change due to the variation in energy, but also the activation rate changes, and the variation in the operating characteristics of the thin film transistor increases. On the other hand, in the present invention, the crystallization by laser annealing and the activation by lamp annealing are separated, so that the variation appearing in the operation characteristics of the thin film transistor is smaller than in the prior art.

[Brief description of the drawings]

FIG. 1 is a process chart showing a first embodiment of a method for manufacturing a thin film transistor according to the present invention.

FIG. 2 is a conceptual diagram showing a rapid heating device used for carrying out the present invention.

FIG. 3 is a process diagram showing a second embodiment of the method for manufacturing a thin film transistor according to the present invention.

FIG. 4 is a perspective view showing an example of an active matrix type display device which is an application example of the present invention.

[Explanation of symbols]

0: insulating substrate, 1: gate electrode, 2: gate nitride film, 3: gate oxide film, 5: semiconductor thin film, 7: interlayer insulating film, 11: pixel Electrodes, 50
..Laser light, 60 ... RTA

Continued on the front page F-term (reference) HJ04 HJ13 HJ23 HL07 HL23 HM15 NN02 NN12 NN23 NN24 NN35 PP03 PP06 PP35 QQ09 QQ12 QQ23

Claims (6)

[Claims] 1. A method of manufacturing a thin film transistor having a stacked structure including a semiconductor thin film, a gate insulating film overlaid on one surface thereof, and a gate electrode overlaid on the semiconductor thin film with the gate insulating film interposed therebetween. A film forming step of forming a thin film on an insulating substrate, a crystallization step of irradiating the semiconductor thin film with an energy beam for crystallization, an implanting step of injecting impurities into the crystallized semiconductor thin film, Activating the semiconductor thin film by a heating method using a lamp to activate the implanted impurities. 2. The method according to claim 1, wherein the implanting step includes implanting a predetermined impurity into the semiconductor thin film at a predetermined concentration to control a threshold voltage of the thin film transistor, and the activating step includes implanting at least a threshold voltage for controlling the threshold voltage. 2. The method according to claim 1, wherein the activated impurities are activated. 3. The step of implanting includes implanting a predetermined impurity at a predetermined concentration into the semiconductor thin film to form an impurity region having a lower concentration than the drain region between the channel region and the drain region of the thin film transistor. 3. The method according to claim 2, wherein the activating step activates the impurities implanted between the channel region and the drain region simultaneously with the activation of the impurities implanted for controlling the threshold voltage. . 4. The crystallization step comprises irradiating an energy beam comprising a laser beam to once melt the semiconductor thin film and then performing crystallization in a cooling step, and the activating step comprises irradiating an ultraviolet ray emitted from a lamp. 2. The method according to claim 1, wherein the impurity is activated by heating the semiconductor thin film at a temperature equal to or lower than the melting point. 5. A thin film transistor having a laminated structure including a semiconductor thin film, a gate insulating film overlaid on one surface thereof, and a gate electrode overlaid on the semiconductor thin film via the gate insulating film, wherein the semiconductor thin film is After being formed on the insulating substrate, the semiconductor thin film is crystallized by irradiation with an energy beam, and the impurities injected into the crystallized semiconductor thin film are heated by a heating method using a lamp as a heat source. A thin film transistor which is activated by heating. 6. A pair of substrates joined to each other via a predetermined gap, and an electro-optical material held in the gap,
A counter electrode is formed on one of the transparent substrates, a pixel electrode and a thin film transistor for driving the pixel electrode are formed on the other insulating substrate, and the thin film transistor is stacked on a semiconductor thin film on one side thereof with a gate insulating film interposed therebetween. A method for manufacturing a display device formed with electrodes, comprising: a film forming step of forming a semiconductor thin film on another substrate; a crystallization step of irradiating the semiconductor thin film with an energy beam to crystallize; An injection step of injecting impurities into the semiconductor thin film, and an activation step of heating the semiconductor thin film by a heating method using a lamp as a heat source to activate the injected impurities, thereby forming a thin film transistor. A method for manufacturing a display device, comprising: