JP2002299629A - Polysilicon thin film semiconductor and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the fluctuation of display pictures due to the dispersion of the characteristic of driving TIFT by controlling the threshold voltage of a thin film transistor in a low temperature process in a picture display device. SOLUTION: In the manufacture of a thin film semiconductor device where a thin film transistor is integrated, a film which is close to an I (intrinsic) layer where impurity is not mixed in a thin film (sheet resistor is not less than 1.0×10<9> ohm/sq.) is used. For crystallizing an active layer, the threshold voltage of the thin film transistor can be adjusted by suppressing impurity contamination to under 1×10<17> /cm<3> .

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film semiconductor device and a thin film semiconductor device.
And a method for producing the same. For details, for example, 1000cm ^Two that's all
Film formed on an insulating substrate such as glass having a large area
Selective implantation of impurity ions into crystalline semiconductor thin films
Low-concentration impurity region, high-concentration impurity region and channel
Forming a thin film transistor having an integrated region,
A thin film that has been subjected to the necessary heat treatment in a low-temperature process of 0 ° C or less
The present invention relates to a film semiconductor device and a method for manufacturing the same. More details
In other words, impurity ions for adjusting the threshold voltage of thin film transistors
The present invention relates to an on-injection method and an activation method.

[0002]

2. Description of the Related Art Large-area thin-film semiconductor devices used for liquid crystal displays and the like have been actively developed. Conventionally, thin film transistors integrated on a thin film semiconductor device for pixel switching generally have a structure using amorphous silicon as an active layer. However, since amorphous silicon thin film transistors have low carrier mobility and do not have sufficient operating characteristics, peripheral drive circuits and the like cannot be integratedly formed on an insulating substrate. In recent years, thin film semiconductor devices using polycrystalline silicon thin film transistors have been developed. Polycrystalline silicon thin film transistors have better operation characteristics than amorphous silicon thin film transistors, and can be used as devices for peripheral driving circuits in addition to pixel switching. As described above, a thin film semiconductor device using a polycrystalline silicon thin film transistor is most suitable for a large-area high-resolution liquid crystal display with a built-in drive circuit, and has been actively researched and developed. In general, the production of polycrystalline silicon thin film transistors is divided into a high-temperature process including a heat treatment at 1000 ° C. or higher and a low-temperature process in which the maximum process temperature is suppressed to 600 ° C. or lower. A low-temperature process is indispensable for using glass, which is comparatively advantageous in cost and the like, as an insulating substrate, and is currently mainstream.

[0003]

However, in the conventional low-temperature process, it is difficult to control the threshold voltage (Vth) of the thin film transistor, and it has not been actually performed. Generally, in order to adjust the threshold voltage of a thin film transistor, it is necessary to controlly implant and activate impurity ions at a relatively low dose into a channel region (active layer) of a semiconductor thin film. Was difficult to process. Further, when impurities are mixed in the active layer in advance, all are activated by the heat treatment.

However, in order to improve the performance of the thin film transistor and to make the operation characteristics of the thin film transistor uniform on a large-area insulating substrate, it is essential to control the threshold voltage. In the conventional low-temperature process, the threshold voltage of the thin film transistor is not controlled. For example, when the threshold voltage (Vth) fluctuates toward the depletion side due to process variations, compensation becomes impossible, and the leak current of the thin film transistor increases. Bright spot defect.
In addition, if impurity contamination is present on the amorphous silicon surface from the beginning, laser annealing is performed as it is, thereby contaminating impurities are activated and variations occur in each transistor.

[0005]

According to the present invention, there is provided a method of manufacturing a thin film semiconductor capable of accurately controlling an impurity implantation process and an activation process for adjusting a threshold voltage of a thin film transistor. And a thin film semiconductor device. In order to achieve this object, a method of manufacturing a thin film semiconductor device according to the present invention comprises first performing a first step of forming a non-single-crystal semiconductor thin film on an insulating substrate, and then, A semiconductor thin film is irradiated with laser light having an intensity exceeding the activation energy to convert a non-single crystal into a polycrystal to form an active layer of a thin film transistor.

Here, a resistance value is monitored using a ring electrode type sheet resistor capable of measuring a high resistance, and a thin film having a resistance value of 10 ⁹ ohm / sq or less is excluded.

Further, in a third step, in order to adjust the threshold voltage of the thin film transistor, an impurity corresponding to a previously measured sheet resistance is implanted into the active layer at a predetermined concentration, and then a heat treatment is performed. Alternatively, the semiconductor thin film is irradiated with a laser beam having an intensity larger than the minimum crystallization energy and equal to or lower than the energy at which the average crystal grain size of the polycrystal is the maximum, and the impurity injected into the active layer is reduced to 1.5 × 10 ¹⁸ / Activates at an effective concentration of less than cm ³ .

Finally, in a fourth step, at least the source region and the drain region of the thin film transistor are formed by selectively injecting impurities into the semiconductor thin film other than the portion where the active layer is left as a channel region as it is. It is.

Preferably, in the fourth step, an impurity having the same conductivity type as the source region and / or the drain region and a lower concentration and a higher concentration than the channel region is provided between the source region and / or the drain region and the channel region. It includes a process of forming a low concentration impurity region by implantation. In a preferred embodiment of the present invention, the thin film transistor is formed on an insulating substrate made of non-alkali glass.
Are performed at a processing temperature of 600 ° C. or less.

According to the present invention, in a method of manufacturing a thin film semiconductor device in which the maximum process temperature is set to, for example, 600 ° C. or less, a predetermined impurity species is ionized at least in an active layer (channel region) for controlling a threshold voltage of a thin film transistor. Introduced by injection. As a characteristic feature, impurity ions introduced into the active layer are activated by heat treatment or laser light irradiation. At this time, a laser beam which is larger than the minimum crystallization energy required for converting the non-single crystal into the polycrystal and is set to be equal to or less than the energy at which the average crystal grain size of the polycrystal becomes the maximum is applied. Further, control is performed so that the concentration of the activated impurity ions is less than 1.5 × 10 ¹⁸ / cm 3. With such an injection process and an activation process, the threshold voltage of the thin film transistor can be accurately controlled.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a process chart showing a first embodiment of a method for manufacturing a thin film semiconductor device according to the present invention. In this embodiment, a non-single-crystal semiconductor thin film formed on an insulating substrate having an area of about 1000 cm ² or more is selectively implanted with impurity ions to form a low-concentration impurity region, a high-concentration impurity region, and a channel region. The thin-film semiconductor device is manufactured by integrally forming a thin film transistor having the above structure and performing necessary heat treatment at a process temperature of 600 ° C. or less. The thin film transistor of the present embodiment has a top gate structure, and includes both an N-channel type and a P-channel type. However, only an N-channel thin film transistor is shown for ease of illustration. In this thin film transistor, the width dimension W of the channel region is 10 μm, and the longitudinal dimension of the channel region is set to 4 μm.

First, as shown in FIG. 1A, a buffer layer 1 as a base film is formed on an insulating substrate 100 made of glass or the like.
To form For example, a SiO2 film or a SiNx film is
The buffer layer 1 is deposited with a thickness of 00 nm to 200 nm.
Note that the buffer layer 1 is not always necessary. Subsequently, the semiconductor thin film 2 made of amorphous silicon is formed to a thickness of about 30 nm by a plasma CVD method or an LPCVD (low pressure CVD) method.
The film is formed to a thickness of about 80 nm. The dimensions of the insulating substrate 100 on which the buffer layer 1 and the semiconductor thin film 2 are formed over the entire surface are 90 cm × 120 cm. Here, when the plasma CVD method is used to form the semiconductor thin film 2 made of amorphous silicon, annealing is performed to desorb hydrogen in the film. In this annealing, the insulating substrate 100 is put in a nitrogen atmosphere and heated at a temperature of 400 to 450 ° C. for about one hour. This dehydrogenation annealing may use lamp annealing such as RTA (Rapid Thermal Annealing). Subsequently, the amorphous silicon is crystallized using a means such as laser annealing or solid phase growth to be converted into polycrystalline silicon.

Next, the sheet resistance of the polycrystalline silicon is measured to monitor the resistance value. The polycrystalline silicon film is expected to have a high resistance, so it is difficult to measure it with a four-terminal four-point probe. For this reason, a ring-shaped electrode made in a donut shape was manufactured and used as an apparatus for measuring high resistance. This is shown in FIG. The resistance value is measured using a ring electrode having an outer inner diameter of 6 mm and an inner electrode outer diameter of 3 mm. If the measurement result is 10 ⁹ ohm / sq or less, it is excluded because a large amount of impurities exists in this thin film.

[0014] A polycrystalline thin film is brought into contact with these two electrodes,
When a voltage of about 0 V is applied, the sheet resistance can be easily measured. The threshold voltage Vth can be predicted in advance from the sheet resistance value.

In this method, a donut-shaped metal pattern may be formed on a-Si. After the film is formed, a voltage is applied to each of the inside and the outside, and a current value flowing at that time is monitored to obtain a resistance value. Convert. When the amorphous silicon film is crystallized by laser annealing, the amount of metal impurities such as boron and aluminum on the surface or inside of the amorphous silicon film is 10 ¹⁷ / cm 3 or less. Further, it is desirable for the control of the threshold value that the contamination amount of the impurity is 10 ¹⁷ / cm 3 or less also in the fabricated polycrystalline silicon film.

After that, the semiconductor thin film 2 converted into polycrystalline silicon is patterned into an island shape by etching to form an element region of a thin film transistor. A gate insulating film is formed so as to cover the etched semiconductor thin film. For example, a plasma CVD method, a normal pressure CVD method, a low pressure CVD method, an ECR-CVD method, a sputtering method, etc.
2 A film is deposited and grown to a thickness of 50 nm to 400 nm to form a gate insulating film 3.

Here, if necessary, a first implantation step (an additional ion beam implantation step) is performed using a large current ion implantation apparatus. That is, the impurity ion generated from the ion source is subjected to mass separation to extract only the target ion species, and the dose is less than 1 × 10 ¹³ / cm 2 while scanning the first ion beam obtained by shaping into a beam shape. The threshold voltage Vth of the thin film transistor is controlled by estimating the threshold voltage Vth of the thin film transistor in advance by adjusting the impurity concentration of a portion to be a channel region in a later step. The high-current ion implantation system used for this process has a magnetic field deflector, and has a large area of 1000 cm ² or more by scanning a high-current ion beam with magnetic field deflection to the extent that scanning by electrostatic deflection is difficult Insulating substrate 10
0 enables efficient processing. Specifically, the target ion species B ⁺ is converted to the Vt of a thin film transistor (TFT).
In order to control h, the dose is set to 1 × 10 ¹² / cm ² to 8 ×
The ion implantation is performed at a setting of about 10 ¹² / cm ² . The acceleration voltage at this time is set to, for example, 10 kV. The ion beam current is 4 μA to 10 μA, the scanning frequency in the horizontal direction is 1 Hz, and the scanning speed in the vertical direction is 30 mm / sec.
And the overlap amount of the beam spot is 66.7.
%, And the vertical scanning cycle is 8 sycles to 10 cy.
cles, and the total time required for ion implantation is 300 sec.
400 seconds. Note that the first implantation step for Vth control may be performed before the gate insulating film 3 is formed. In addition, this implantation may be performed by scanning the ribbon beam on the glass substrate with a mass separation type injector.

Next, as shown in FIG.
A film of Al, Ti, Mo, W, Ta, low-resistance polysilicon or an alloy thereof having a thickness of 200 nm to 800 nm is formed on 0, and is patterned into a predetermined shape to be processed into the gate electrode 4. Next, as in the first implantation step, a second implantation step (ion beam implantation step) is performed using a high-current ion implantation apparatus equipped with a magnetic field deflector. That is, the impurity ions generated from the ion source are subjected to mass separation to extract only the target ion species, and the dose of less than 1 × 10 ¹⁴ / cm 2 is scanned while scanning the second ion beam 5 obtained by shaping into a beam shape. In the semiconductor thin film 2 to form a low-concentration impurity region 8-1 of the TFT. Specifically, P ⁺ which is a target ion species is ion-implanted using the gate electrode 4 as a mask. The dose at this time is 6 × 1
It is set to 0 ¹² / cm 2 to 5 × 10 ¹³ / cm ² .

Further, as shown in FIG. 1C, a resist pattern 6 for an N-channel transistor is formed, and its periphery including the gate electrode 4 is covered. Here, a third implantation step (ion shower step) is performed using an ion doping apparatus.
Perform That is, a dose of 1 × 10 ¹⁴ / cm 2 or more is obtained without scanning the ion shower 7 obtained by accelerating the electric field while containing the target ion species without subjecting the impurity ions generated from another ion source to mass separation. In the semiconductor thin film 2 to form a high-concentration impurity region 8-2 of the TFT. Specifically, the target ion species, P ⁺ , is set to 1 × 10 ¹⁵ / cm 2
Ion implantation is performed at a dose of about the same. Since this ion doping apparatus collectively extracts impurity ions from a bucket type chamber and irradiates the entire surface of the insulating substrate 100, the throughput is high and the processing time per one wafer is about 1 min even when the wafer is transported.

In some cases, the third implantation step may be performed using the above-described ion implantation apparatus instead of the ion doping apparatus. By the above processing, a channel region Ch whose Vth is adjusted in advance is formed immediately below the gate electrode 4, and an LDD (Lightly Doped Drain) region including the low concentration impurity region 8-1 is formed on both sides thereof. A source region S and a drain region D composed of the high concentration impurity region 8-2 are formed on both sides thereof. When a CMOS circuit is integrated on the insulating substrate 100, the resist pattern 6 for the N-channel transistor is used.
To form a resist pattern for the P-channel transistor in place of, switch the gas system of the ion source 5% B2 H6 / H2, the B ⁺ may be ion implanted at a dose of about 1 × 10 ¹⁵ / cm @ 2.

Finally, as shown in FIG. 1D, the thin film transistor TFT is covered with an interlayer insulating film 9 made of PSG or the like. Its thickness is about 600 nm. 30 in this state
Annealing is performed at a temperature of 0 ° C. to 400 ° C. to activate the dopant implanted in the semiconductor thin film 2. Laser activation annealing may be performed instead of such low-temperature activation annealing. Further, after opening a contact hole in the interlayer insulating film 9, a metal film made of Al—Si or the like is formed by sputtering, patterned into a predetermined shape, and processed into the wiring electrode 10. S on the wiring electrodes 10 in order
It is covered with an iO2 film 11 and a SiNx film 12. The total thickness of these films is about 200 to 400 nm. In this state, the insulating substrate 100 is placed in a nitrogen atmosphere, and hydrogenation annealing is performed at a temperature of about 350 ° C. for about 1 hour. Thereby, the hydrogen contained in the SiO2 film 11 is introduced into the semiconductor thin film 2, and the operation characteristics of the thin film transistor TFT can be improved. As described above, the thin film semiconductor device is completed. When the thin film semiconductor device is used for a liquid crystal display, a pixel electrode made of ITO or the like may be further formed on the SiNx film 12. The process temperature of the thin-film semiconductor device described above is up to 40 for dehydrogenation annealing.
0 ° C to 450 ° C.

FIG. 3 is a block diagram showing a specific configuration of a high-current ion implantation apparatus used in the above-described first implantation step and second implantation step. As shown, the apparatus includes an ion source 31, a mass separator 32, a quadrupole lens 33, a deflection magnet 34, an angle correction magnet 35, a work station 36, and the like. The ion beam generated from the ion source 31 passes through the mass separator 32 and is mass-separated. Further, the light enters the deflection magnet 34 via the quadrupole 33. After this, the angle correction magnet 3
5, the angle of the ion beam with respect to the substrate is adjusted, and the dose distribution in the substrate surface is made uniform. Finally, the ion beam is incident on the insulating substrate mounted on the workstation 36. The quadrupole lens 33 is provided to compensate for a change in the imaging position due to the space charge effect accompanying the high current ion beam. A more specific optical system of the large current ion implantation apparatus having such a configuration is, for example, Nuclear Instrument.
ents and Methods in Physi
cs Research A363 (1995) p. 4
68. This large current ion implantation system has a maximum substrate size of 32 cm x 4
0 cm, the maximum beam current is 16 mA, the implantation energy is variable between 10 KeV and 100 KeV, and the dose is controllable in the range of 1 × 10 ¹² / cm 2 to 1 × 10 ¹⁶ / cm ² . The implantable ion species correspond to P ⁺ and B ⁺ . The feature of this ion implantation system is that a large current ion beam is scanned by a magnetic field instead of an electric field. Therefore, it is possible to scan a large current ion beam, which was difficult with the conventional electrostatic deflector. I have. Since it has a magnetic-deflection type scanning system, it is possible to process a substrate in a single wafer using a high-current ion beam of 10 mA or more. In addition, the ion implantation time is completed within a few tens of seconds to a few minutes, and there is no fear of a decrease in throughput. The spot size of the high-current ion beam is a square of 90 mm × 120 mm.

FIG. 4 is a block diagram showing an example of an ion doping apparatus used in the above third implantation step. This ion doping apparatus is large, having an opening corresponding to the size of a substrate, and mainly includes an ion source 51 for generating plasma by capacitively-coupled high-frequency discharge. The ion source 51 is connected to a high frequency power supply 53 via a matching box 52. Four porous electrodes (first electrode 5
4, an ion shower 5 by the extraction / acceleration electrode system formed by the second electrode 55, the suppression electrode 56, and the ground electrode 57).
Pull out 8.

There are a single-stage acceleration system and a two-stage acceleration system as an ion source having a four-electrode configuration. In the present embodiment, the former is adopted. In the case of this one-stage acceleration method, ion energy can be determined with a single acceleration voltage. Further, the state of extraction of ions from the plasma can be adjusted by controlling the extraction current independent of the energy. That is, in this one-stage acceleration system, a drawing power source 59, an acceleration power source 60, and a suppression power source 61 are separately provided. As shown in the figure, the ion doping apparatus differs from the ion implantation apparatus in that it does not have an accelerating tube or a scanning unit. The required energy is determined by the extraction and acceleration electrode system of the ion source. On the other hand, as for the size of the ion shower 58 corresponding to the required substrate size, a porous region of the ion source according to the substrate size is used. Therefore, as the size of the substrate increases, the size of the ion source increases. In the current ion source for a 90 cm × 120 cm substrate, the maximum diameter is 2.5 m.

FIG. 5 is a process chart showing a second embodiment of the semiconductor device manufacturing method according to the present invention. The first shown in FIG.
Corresponding reference numerals are assigned to portions corresponding to the embodiment to facilitate understanding. In this embodiment mode, a thin film transistor having a bottom gate structure is integrated and formed. For ease of illustration, only an N-channel thin film transistor is shown. The channel width is 10 μm and the channel length is 7 μm. First, as shown in FIG. 5A, an SiO2 film or S
An iNx film or the like is formed with a thickness of about 100 nm to 200 nm to form a buffer layer 1. The size of the insulating substrate 100 is 30 cm ×
35 cm. Next, a metal film made of Al, Ta, Mo, W, Cr or an alloy thereof is formed to a thickness of 100 nm to 200 nm, patterned into a predetermined shape, and processed into the gate electrode 4. As a material of the gate electrode 4, Al, Ta,
When Mo / Ta or the like is used, the gate insulating film 3a can be formed by anodizing the surface. Next, plasma C
5 SiNx by VD method, normal pressure CVD method, low pressure CVD method, etc.
A gate insulating film 3b is formed by depositing 0 nm and continuously depositing about 200 nm of SiO2. Further, a semiconductor thin film 2 made of amorphous silicon is continuously formed thereon by about 30 nm to 8 nm.
The film is formed with a thickness of 0 nm. Here, when the plasma CVD method is used, annealing is performed at about 400 ° C. to about 450 ° C. for about 1 hour in a nitrogen atmosphere in order to desorb hydrogen in the film.
This dehydrogenation annealing may use lamp annealing such as RTP. Here, in order to control Vth of the TFT, B ⁺ ions are implanted using a large current ion implantation apparatus. The dose amount is 1 × 10 ¹² / cm ^{2 to} 6 ×
It is set to about 10 ¹² / cm ² .

At this stage, amorphous silicon is converted to polycrystalline silicon by using a laser annealing method or a solid phase growth method. After measuring the sheet resistance, the converted semiconductor thin film 2 made of polycrystalline silicon is patterned into the shape of the element region of the thin film transistor.

Next, as shown in FIG. 5B, SiO2 is formed to a thickness of about 100 nm to 300 nm and patterned by backside exposure using the gate electrode 4 as a mask to form a stopper 6a.
Process into Next, using a large current ion implantation apparatus, P ⁺ ions are implanted into the semiconductor thin film 2 using the stopper 6a as a mask to form a low concentration impurity region 8-1. The dose at this time is 6 × 10 ¹² / cm ^{2 to} 5 × 10
¹³ / cm ² .

Next, as shown in FIG. 5C, a resist pattern 6 of the N-channel transistor 4 is formed. Using this resist pattern 6 as a mask, P + is implanted into the semiconductor thin film 2 by a high-current ion implantation apparatus to form a high-concentration impurity region 8-2. The dose at this time is 1
It is about × 10 ¹⁵ / cm 2. When a CMOS circuit is formed on the insulating substrate 0, a resist pattern for a P-channel transistor is formed separately from the resist pattern 6 for an N-channel transistor, and the ion species is changed from P + to B +.
And ion implantation may be performed.

The dose at this time is about 1 × 10 ¹⁵ / cm 2. As in the first embodiment, a non-mass separation type ion doping apparatus may be used for forming the high concentration impurity region. As described above, a thin film transistor TFT having a bottom gate structure is integrally formed. A channel region Ch is formed immediately below the stopper 6a, an LDD region including a low-concentration impurity region 8-1 is formed on both sides thereof, and a source region S and a high-concentration impurity region 8-2 on both sides thereof. A drain region D is formed. After this, 30
Anneal at about 0 ° C. to 400 ° C. to activate the dopant implanted in the semiconductor thin film 2. This activation annealing may be performed by laser annealing as in the first embodiment.

Finally, as shown in FIG. 5D, SiO 2 is deposited to a thickness of about 20 nm to form an interlayer insulating film 9. After opening a contact hole in the interlayer insulating film 9, Mo, Mo,
A metal film such as Al is sputtered with a thickness of 200 nm to 400 nm, patterned into a predetermined shape, and processed into the wiring electrode 10. On top of this, a SiO2 film 11 and a SiNx film 12
And deposit 200 to 400 nm. Further, the insulating substrate 100 is put in a nitrogen atmosphere, and is held at a temperature of 350 ° C. for one hour to perform hydrogenation annealing, thereby completing a thin film semiconductor device. The maximum process temperature of this embodiment is 400 ° C. to 450 ° C. for dehydrogenation annealing.

FIG. 6 shows the threshold voltage Vth of the thin film transistor.
4 is a graph showing the relationship between the dose and the dose of impurity ions with respect to the channel region. This dose is obtained by injecting a dose corresponding to the dose predicted in advance from the sheet resistance value. This graph is actual measurement data of a thin film transistor created in the second embodiment of the present invention, and shows both an N-channel transistor and a P-channel transistor. This graph sweeps the gate voltage from -10V to + 15V,
Vth is measured under the condition that the drain voltage is set to 10V. In the case of the N-channel transistor shown in (a), when the dose is 3 × 10 ¹² / cm 2 (the point where the dose is the largest), Vth is set to about 0.5 V with respect to the N-channel transistor which has not been subjected to ion implantation at all. It can be shifted in the enhancement direction.

On the other hand, Vth of the P-channel transistor shown in (b) is not remarkably shifted as compared with the N-channel transistor. Nevertheless, when B + is implanted at a dose of 3.times.10@12 / cm @ 2, Vth can be shifted to the depletion side by about 0.1 V as compared with a P-channel transistor without any ion implantation.

FIG. 7 shows the N channel created in the second embodiment.
Gate voltage / drain current characteristics of
This is Suguura. (A) is the dose to the channel region
1 × 10¹³/cm^Two(B)
Means that the dose to the channel region is 1 × 10¹³/ Cm2
It shows the characteristics when exceeding. Threshold voltage control
Dose amount is 1 × 10¹³/ Cm2, as shown in (b)
To thin film transistor gate voltage / drain current characteristics
Abnormality appears. Therefore, the dose of B + for controlling Vth
Quantity is 10¹³/ Cm2 must be adjusted to less than
Or 3 × 10 ¹²/ Cm2 or less. If you do this,
Normal gate voltage of thin film transistor as shown in (a)
/ Drain current characteristics. The above results are
Relating to the thin film transistor obtained in the second embodiment
However, the thin film transistor formed in the first embodiment
The same can be said for data.

FIG. 8 shows a low-concentration impurity region (L) in the N-channel thin-film transistor formed in the second embodiment.
9 is a graph showing a relationship between a dose amount (DD region) and a leak current. As is clear from this graph, the leak current is substantially proportional to the dose in the LDD region.

The dose of P + in the LDD region is 1 × 10 ¹⁴
/ Cm2, the leakage current becomes 10 pA or more, and L
The effect of providing the DD region is almost lost. Therefore, LDD
The dose for the region needs to be less than 1 × 10 ¹⁴ / cm 2 in terms of the effective dose of P + ions.

Preferably, the control is performed at 5 × 10 ¹³ / cm 2 or less. As described above, the sample prepared in the second embodiment has been described as an example, but the same can be said for the thin film transistor manufactured in the first embodiment. or,
The same can be said for not only N-channel transistors but also P-channel transistors.

5 × 10 ¹³ / cm 2 estimated from sheet resistance
If more must be implanted, this substrate should be considered a lot-out.

The thin film transistor formed by the above-described steps can be made uniform in characteristics by accurate threshold value control. Therefore, the active matrix element of a liquid crystal display device or an organic electroluminescence display device, or a driving circuit device. Particularly suitable as an element.

[0039]

As described above, according to the present invention, by measuring the sheet resistance in advance after laser annealing, it is possible to know in advance the Vth of a low-temperature process thin film transistor, which was difficult with the prior art. , Vth and the formation of the LDD region are facilitated. 10 ⁹ [ohm / s
q] or less, it is determined that the film is difficult to control Vth because impurities are activated in the polycrystalline silicon. Vth control is possible with a film of 10 ⁹ [ohm / sq] or more.

It becomes easy to form thin-film transistors made of low-temperature polycrystalline silicon or the like whose electric characteristics are accurately controlled over a large area of an insulating substrate. Therefore, by using the present invention, a high-resolution liquid crystal display in which peripheral driving circuits are integrated on a large-sized substrate can be realized.

[Brief description of the drawings]

FIG. 1 shows a first example of a method of manufacturing a thin film semiconductor device according to the present invention.
Process drawing showing the embodiment

FIG. 2 is a configuration diagram of a ring electrode.

FIG. 3 is a block diagram showing an example of a high-current ion implantation apparatus used for implementing the present invention.

FIG. 4 is a block diagram showing an example of an ion doping apparatus used for implementing the present invention.

FIG. 5 shows a second example of the method of manufacturing a thin film semiconductor device according to the present invention.
Process drawing showing the embodiment

FIG. 6 is a graph showing a relationship between a threshold voltage and a dose of a thin film transistor manufactured according to the present invention.

FIG. 7 is a graph showing gate voltage / drain current characteristics of a thin film transistor similarly manufactured according to the present invention.

FIG. 8 is a graph showing the relationship between the dose and the leakage current of a thin film transistor similarly manufactured according to the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 100 Insulating substrate 1 Buffer layer 2 Semiconductor thin film 3 Gate insulating film 4 Gate electrode 5 Ion beam 6 Resist pattern 6a Stopper 7 Ion shower 8-1 Low concentration impurity region 8-2 High concentration impurity region 9 Interlayer insulating film 31 Ion source 32 Mass Separator 32 Quadrupole lens 34 Deflection magnet 35 Angle correction magnet 36 Workstation 51 Ion source 52 Matching box 53 High frequency power supply 54 First electrode 55 Second electrode 56 Suppression electrode 57 Ground electrode 58 Ion shower 59 Extraction power supply 60 Acceleration power supply 61 Suppression power supply

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/265 602 H01L 21/265 604Z 604 H05B 33/14 A 21/336 H01L 29/78 618F H05B 33 / 14 616A 627G (72) Inventor Tetsuro Kawakita 1006 Kazuma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Hiroshi Tsutsumi 1006 Odaka Kadoma Kadoma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. F-term (reference) 2H092 JA25 JA34 JA37 JA41 JA46 KA04 KA05 KA10 MA08 MA18 MA27 MA30 NA05 NA22 NA24 NA29 3K007 AB18 DB03 EB00 FA01 FA02 5C094 AA05 AA43 BA03 BA29 BA43 CA19 DA14 DA15 EA04 EA07 EB02 FB14 5F052 AA02 DBA03 AA02 DBA03 AA17 AA28 BB02 BB04 CC02 CC08 DD02 DD13 DD14 EE03 EE04 EE06 EE09 FF02 FF03 FF09 F F10 FF24 FF28 FF29 FF30 FF31 FF32 GG02 GG06 GG13 GG28 GG29 GG32 GG34 GG45 GG47 GG52 HJ01 HJ04 HJ13 HJ23 HL03 HL04 HL06 HL23 HM15 NN03 NN04 NN14 NN23 NN24 NNQ PP15

Claims (22)

[Claims] 1. A first step of forming a non-single-crystal semiconductor thin film on an insulating substrate, and irradiating the semiconductor thin film with a laser beam having an intensity exceeding a minimum crystallization energy to reduce the non-single crystal to 1.0 × 10 ⁹
a second step of forming an active layer of a thin film transistor by converting to polycrystalline having a sheet resistance of at least ohm / sq., and a process of injecting impurities at a predetermined concentration into the active layer to adjust a threshold voltage of the thin film transistor. After doing
The impurity implanted into the active layer is subjected to a process of irradiating the semiconductor thin film with laser light having an intensity equal to or less than the energy at which the average crystal grain size of the polycrystal is larger than the minimum crystallization energy and is 1.5 × 10 ¹⁸ / cm3. A third step of activating at an effective concentration of less than and a fourth step of selectively injecting impurities into a semiconductor thin film other than a portion where the active layer is left as it is as a channel region to form at least a source region and a drain region of the thin film transistor. And a method of manufacturing a thin film semiconductor device. 2. The method according to claim 1, further comprising the step of: adding an impurity having the same conductivity type as the source region and / or the drain region and a lower concentration and a higher concentration than the channel region between the source region and / or the drain region. 2. The method for manufacturing a thin film semiconductor device according to claim 1, further comprising a process of forming a low concentration impurity region by implantation. 3. The process according to claim 1, wherein all the steps including the first to fourth steps are performed at a processing temperature of 600 ° C. or less in order to form a thin film transistor on an insulating substrate made of non-alkali glass. Of manufacturing a thin film semiconductor device. 4. In a display element driven by voltage for each pixel, a driving TFT for applying a drive voltage to the display element
And the sheet resistance of the polysilicon constituting the active layer before impurity implantation is 1.0 × 10 ⁹
A thin film transistor characterized by having an ohm / sq. or more. 5. A driving TFT for applying a driving voltage to a display element driven by voltage for each pixel.
And the sheet resistance of the polysilicon constituting the active layer before impurity implantation is 1.0 × 10 ⁹
An array substrate on which a thin film transistor integrated circuit characterized by being at least ohm / sq. 6. A driving TFT for applying a driving voltage to a display element driven by voltage for each pixel.
And the sheet resistance of the polysilicon constituting the active layer before impurity implantation is 1.0 × 10 ⁹ ohm /
sq. An image display element using the thin film transistor integrated circuit described above. 7. An image display apparatus having a thin film display element driven by voltage for each pixel, wherein an active layer of a driving TFT for applying a drive voltage to the thin film display element is formed, and the active layer is formed. An organic electroluminescence (EL) display device using a thin film transistor integrated circuit having a sheet resistance value of 1.0 × 10 ⁹ ohm / sq. Or more before polysilicon impurity implantation. 8. In a display element driven by voltage for each pixel, a driving TFT for applying a driving voltage to the display element.
And the sheet resistance of the polysilicon constituting the active layer before impurity implantation is 1.0 × 10 ⁹
A manufacturing apparatus for manufacturing the active layer, wherein the apparatus can be controlled to be ohm / sq. or more. 9. When a polycrystalline silicon film crystallizes an amorphous silicon film by laser annealing, metal impurities such as boron and aluminum on the surface or inside of the amorphous silicon film. The amorphous silicon film, wherein the amount of contamination is 10 ¹⁷ / cm 3 or less. 10. When a polycrystalline silicon film crystallizes an amorphous silicon film by laser annealing, metal impurities such as boron and aluminum on the surface or inside the amorphous silicon film. An array substrate on which thin film transistor integrated circuits in which the amorphous silicon film is polycrystallized into a polycrystalline silicon film are integrated, wherein the amount of contamination is 10 ¹⁷ / cm 3 or less. 11. When a polycrystalline silicon film crystallizes an amorphous silicon film by laser annealing, a metal impurity such as boron or aluminum on the surface or inside of the amorphous silicon film. An image display element using a thin film transistor integrated circuit in which the amount of contamination is 10 ¹⁷ / cm 3 or less and the amorphous silicon film is polished to a polycrystalline silicon film. 12. When a polycrystalline silicon film crystallizes an amorphous silicon film by laser annealing, a metal impurity such as boron or aluminum on the surface or inside of the amorphous silicon film. An organic electroluminescence (EL) display device using a thin film transistor integrated circuit in which the amount of contamination of the amorphous silicon film is 10 ¹⁷ / cm 3 or less. 13. When a polycrystalline silicon film crystallizes an amorphous silicon film by laser annealing, a metal impurity such as boron or aluminum on the surface or inside of the amorphous silicon film. Wherein the amount of contamination can be 10 ¹⁷ / cm 3 or less. 14. A driving TF for applying a driving voltage to a display element driven by voltage for each pixel.
A polysilicon thin film, wherein an active layer made of a T polysilicon thin film is formed, and an impurity contamination amount in the active layer is 10 ¹⁷ / cm 3 or less. 15. A driving TF for applying a driving voltage to a display element which is driven by voltage for each pixel.
A thin film transistor using a polysilicon thin film, wherein a T polysilicon thin film active layer is formed, and an impurity contamination amount in the active layer is 10 ¹⁷ / cm 3 or less. 16. A driving TF for applying a driving voltage to a display element driven by voltage for each pixel.
Forming a polysilicon thin film active layer of T, and integrating a thin film transistor integrated circuit using a polysilicon thin film characterized in that the impurity contamination amount in the active layer is 10 ¹⁷ / cm 3 or less. Array substrate. 17. In a display element driven by voltage for each pixel, a driving T for applying a driving voltage to the display element is provided.
Forming an FT polysilicon thin film active layer, and using a thin film transistor integrated circuit of a polysilicon thin film, wherein an impurity contamination amount in the active layer is 10 ¹⁷ / cm 3 or less. Display element. 18. The polysilicon thin film according to claim 14, wherein said impurities are metal impurities such as boron and aluminum. 19. The method according to claim 4, wherein said laser annealing uses an excimer laser.
3. The thin film transistor according to claim 1. 20. The polycrystalline silicon film according to claim 4, wherein the polycrystalline silicon film is a polycrystalline silicon film obtained by converting an amorphous silicon film into polycrystalline silicon by irradiating a short-wavelength high-energy pulsed laser beam. 16. The thin film transistor according to 15. 21. The polycrystalline silicon film is a polycrystalline silicon film obtained by etching an amorphous silicon film once with HF (Fusan) or the like and then irradiating a short-wavelength high-energy pulsed laser beam to polycrystalline silicon. The thin film transistor according to claim 4, wherein the thin film transistor is provided. 22. A polycrystalline silicon film which is obtained by once covering the surface of an amorphous silicon film with an oxide film or the like, and then converting the amorphous silicon film into polycrystalline silicon by irradiation with a short-wavelength high-energy pulsed laser beam. Claim 4, characterized in that:
A thin film transistor according to any one of 15, 20 to 21.