JP2000208764A - Power mosfet and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a gate length than an opening dimension formed by photolithography by forming a side wall insulating layer on the opposite surface of a channel diffusion layer of a first insulating film. SOLUTION: A side wall insulating film is formed on the side surface to a high-concentration n+ diffusion layer 3a and first insulating film 5 while that is formed on the side surface to a low-concentration n- diffusion layer 3b and first insulating film 5. In other words, a side wall insulating film 6a is formed on the opposite surface on a p-type channel diffusion layer 9 side of the first insulating film 5 so that a gate length is shorter than the dimension of opening of an opening part 14 provided by photolithography, with the gate length of a gate electrode 10 being 0.5 μm or less. Thus, a gate length which is finer than the patterning process capability of a photo-resist film is formed. With the gate electrode 10 provided with a T-shape in cross section, no gate resistance increases even with a shorter gate length.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power MOSFET (power field effect transistor) used for a semiconductor integrated circuit and a method of manufacturing the same, and more particularly, to a power MOSFET having a gate electrode with a gate length of 0.5 .mu.m or less and a power MOSFET having the same. It relates to a manufacturing method.

[0002]

2. Description of the Related Art The structure of a conventional power MOSFET will be described with reference to FIG. FIG. 8 shows a conventional power MOS.
FIG. 3 is a cross-sectional view showing an FET.

[0003] In a conventional power MOSFET, as shown in FIG. 8, a high-concentration n ⁺ diffusion layer 103 and a low-concentration n ⁻ diffusion layer are formed on a substrate obtained by depositing a p ⁻ epitaxial layer 101 on a p ⁺ substrate 100. The layer 104 is formed to face the p-type channel diffusion layer 102 with the p-type channel diffusion layer 102 interposed therebetween. A gate insulating film 106 is formed on the source high-concentration n ⁺ diffusion layer 103 and the drain low-concentration n ⁻ diffusion layer 104 on the p ⁻ epitaxial layer 101. A gate electrode 107 is formed on gate insulating film 106 at a position corresponding to p-type channel diffusion layer 102. An interlayer insulating film 108 is formed to cover the gate electrode 107 and the gate insulating film 106. Further, a high concentration n ⁺ diffusion layer 105 is formed at both ends of the source high concentration n ⁺ diffusion layer 103 and the drain low concentration n ⁻ diffusion layer 104. Further, a source electrode 109 and a drain electrode 110 are formed on the high-concentration n ⁺ diffusion layer 105, respectively. That is, it has a source high-concentration n ⁺ diffusion layer 103 and a drain low-concentration n ⁻ diffusion layer 104 that are asymmetric with different impurity concentrations.

Next, a method of forming the source high concentration n ⁺ diffusion layer 103 and the drain low concentration n ⁻ diffusion layer 104 will be described with reference to FIG. FIG. 9 is a sectional view showing a method for forming a diffusion layer of a conventional power MOSFET.

Conventionally, first, a gate electrode 107 is formed first. Next, in order to form the source high-concentration n ⁺ diffusion layer 103, a photoresist (hereinafter, referred to as PR) film 111 is patterned just above the gate electrode 107 as shown in FIG. 111 and gate electrode 107
By using both of them as masks, ions are implanted into the source to form a high concentration n ⁺ diffusion layer 103 in the p ⁻ epitaxial layer 101. Lightly-doped drain shown in FIG. 8 n ^- source high concentration forming method of the diffusion layer 104 n ⁺
This is a formation method similar to that of the diffusion layer 103.

[0006]

However, it is known that miniaturization of the gate length is most effective for improving the high-frequency characteristics of the power MOSFET. However, in the conventional manufacturing method, if the gate length is reduced to 0.5 μm or less, the PR
There is a problem that it is difficult to pattern the film 111.

This point will be described with reference to FIG. FIG. 10 is a schematic diagram illustrating patterning of a PR film on a gate electrode in a conventional power MOSFET.

At present, the patterning process capability of the mass-produced PR film 111 is about ± 0.2 μm. To pattern the PR film 111 on the gate electrode 107 with good yield as shown in FIG. Gate electrode 107
Must have a width of at least 0.4 μm. Therefore, when the processing accuracy of the gate length is about 0.5 ± 0.1 μm, there is a problem that it is difficult to reduce the width of the gate electrode 107 to 0.5 μm or less in the conventional manufacturing method.

Therefore, there is a problem that it is difficult to form a power MOSFET in which the impurity concentration of the source diffusion layer and the drain diffusion layer is asymmetric while minimizing the width of the gate electrode to 0.5 μm or less.

Further, in the conventional structure of the gate electrode 107, as the gate electrode 107 becomes finer,
7 is reduced, and the resistance of the gate electrode 107 is increased. An increase in the resistance of the gate electrode 107 causes a signal delay at a high frequency, so that there is a problem that the resistance is not increased even if the gate electrode 107 is miniaturized.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has a power source in which a gate length of a gate electrode is 0.5 μm or less and an impurity concentration of a source diffusion layer and a drain diffusion layer is asymmetric. An object of the present invention is to provide a MOSFET and a method for manufacturing the same.

[0012]

A power MO according to the present invention is provided.
The SFET includes a semiconductor substrate, a source diffusion layer formed on the semiconductor substrate surface, a drain diffusion layer formed on the semiconductor substrate surface and having a lower impurity concentration than the source diffusion layer, the source diffusion layer and the drain A channel diffusion layer formed between the diffusion layer, a first insulating film formed on each of the source diffusion layer and the drain diffusion layer, and a side of the first insulating film closer to the channel diffusion layer. Characterized by having a side wall insulating film formed on the opposing surface, a gate insulating film formed on the channel diffusion layer, and a gate electrode formed on the gate insulating film. The conductivity type of the semiconductor substrate may be n-type or p-type.

In the present invention, a first diffusion layer is formed between the source diffusion layer and the first insulation film, and the first diffusion layer is formed between the drain diffusion layer and the first insulation film. It is preferable that a second diffusion layer having a lower impurity concentration than the first diffusion layer is formed.

In the present invention, it is preferable that an epitaxial layer is formed on the semiconductor substrate.

Further, in the present invention, it is preferable that the gate electrode has a T-shaped cross section.

A method for manufacturing a power MOSFET according to the present invention comprises the steps of: forming an epitaxial layer on a semiconductor substrate; forming a polycrystalline silicon layer on the epitaxial layer; Patterning a first resist film to form a first diffusion layer, and patterning a second resist film on the polycrystalline silicon layer to have an impurity concentration lower than that of the first diffusion layer. Forming a second diffusion layer, and forming an opening reaching the epitaxial layer after forming the first insulating film on the polycrystalline silicon layer, by forming a source diffusion layer formation region and a drain diffusion layer formation region Forming a sidewall insulating film on a surface of the first insulating film facing the channel diffusion layer; and forming the epitaxial film between the sidewall insulating films. Forming a gate insulating film thereon, forming a source diffusion layer and a drain diffusion layer having a lower impurity concentration than the source diffusion layer by heat treatment, and forming a gate electrode on the gate insulating film And the following.

In the present invention, as a post-process of forming a gate electrode on the gate insulating film, a third resist film is patterned to open contact portions of the source diffusion layer and the drain diffusion layer. Forming a high-concentration diffusion layer by implanting ions into the contact portion, forming a conductive metal film, patterning the conductive metal film to form a source electrode and a drain electrode, It is preferable to have

In the present invention, by forming a sidewall insulating film on the surface of the first insulating film facing the channel diffusion layer, the gate length can be made smaller than the opening size whose effective gate length is determined by photolithography. It can be formed by self-alignment.

[0019]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a sectional view showing a power MOSFET according to a first embodiment of the present invention. 2 (a) to 2 (d) to 6 (a) and 6 (b) are cross-sectional views showing a method of manufacturing the power MOSFET according to the first embodiment of the present invention in the order of steps.

In the power MOSFET according to this embodiment, for example, on a p ⁺ substrate 1 made of Si, for example,
A source high-concentration n ⁺ diffusion layer 8a is formed as a source diffusion layer on the substrate on which the p ^- epitaxial layer 2 made of Si is deposited.
And a low-concentration n ⁻ diffusion layer 8b having a lower impurity concentration than the high-concentration n ⁺ diffusion layer 8a are formed opposite to each other with a p-type channel diffusion layer 9 interposed therebetween as a drain diffusion layer. Source high concentration n ⁺ diffusion layer 8a and drain low concentration n ⁻
A high-concentration n ⁺ diffusion layer 12 is formed on each of the diffusion layers 8 b on the side not in contact with the p-type channel diffusion layer 9. On the high-concentration n ⁺ diffusion layer 12, a source electrode 13a and a drain electrode 13b are formed, respectively. The source high concentration n ⁺ impurity concentration of the drain low concentration diffusion layer 8a n ^- of a higher concentration than the diffusion layer 8b is for reducing the source resistance, drain low concentration n ^- impurity diffusion layer 8b The reason why the concentration is lower than that of the source high concentration n ⁺ diffusion layer 8a is to secure the drain-source breakdown voltage.

Further, over the source high concentration n ⁺ diffusion layer 8a, a high concentration n ⁺ diffusion layer 3a is formed as a first diffusion layer, a drain low concentration n across the opening 14 ^- diffusion layer 8b
A low-concentration n ^- diffusion layer 3b is formed as a second diffusion layer. First insulating films 5 are formed on the high-concentration n ⁺ diffusion layer 3a and the low-concentration n ⁻ diffusion layer 3b, respectively, with the opening 14 interposed therebetween.

Further, a side wall insulating film 6a is formed on the side surface of the high concentration n ⁺ diffusion layer 3a and the first insulating film 5 on the p-type channel diffusion layer 9 side. Further, the low concentration n ^- diffusion layer 3b
Sidewall insulating films 6a are formed on the side surfaces of the first insulating film 5 and the first insulating film 5 on the p-type channel diffusion layer 9 side.

Gate insulating film 7 is formed on p-type channel diffusion layer 9. On this gate insulating film 7, a gate electrode 10 having a T-shaped cross section is formed. An interlayer insulating film 11 is formed so as to cover the gate electrode 10 and the first insulating film 5.

In this embodiment, the high-concentration n ⁺ diffusion layer 3
forming side wall insulating films on the side surfaces of the first insulating film 5 and the first insulating film 5;
By forming a side wall insulating film on the side surfaces of the low concentration n ^- diffusion layer 3b and the first insulating film 5, that is, the first insulating film 5
By forming the side wall insulating film 6a on the surface facing the p-type channel diffusion layer 9 side, the gate length can be made shorter than the opening dimension of the opening 14 formed by photolithography. As a result, a gate length finer than the capability of the patterning process of the PR film can be formed.

In this embodiment, the gate electrode 10
Is formed in a T-shaped cross section, the gate resistance does not increase even if the gate length is shortened.

Next, a method of manufacturing a power MOSFET according to this embodiment will be described with reference to FIGS.
A description will be given based on (a) and (b). First, FIG.
As shown in FIG. 1A, a polycrystalline silicon layer 3 serving as a solid-phase diffusion source is formed on a substrate obtained by depositing a p ⁻ epitaxial layer 2 on a p ⁺ substrate 1.

Next, as shown in FIG.
Is formed, the PR film 4 is patterned, and a high-concentration n ⁺ diffusion layer 3a is formed in the polycrystalline silicon layer 3 in a region on the source diffusion layer side by, for example, ion implantation.

Next, as shown in FIG. 2C, patterning of the PR film 4a is performed in the same procedure as that for the source diffusion layer side, and the polycrystalline silicon layer 3 on the drain side is ion-implanted, for example. Then, a low concentration n ^- diffusion layer 3b is formed.

Next, as shown in FIG. 2D, a first insulating film 5 is deposited on the polycrystalline silicon layer 3, for example, an SiO ₂ film as an insulator is deposited.

Next, as shown in FIG.
b, the first insulating film 5 and the polycrystalline silicon layer 3 are dry-etched, for example, to form an opening 14 having a width of, for example, 0.5 μm. It is formed between the region where the diffusion layer is to be formed. By forming the opening 14, the high concentration n ⁺ diffusion layer 3a corresponding to the source diffusion layer and the low concentration n ⁻ diffusion layer 3b corresponding to the drain diffusion layer are separated.

Next, as shown in FIG. 3B, as the second insulating film 6, for example, an SiO ₂ film, which is an insulator, is buried so as to fill the opening 14 of the first insulating film 5. Deposited on

Next, as shown in FIG. 3C, the second insulating film 6 is subjected to, for example, anisotropic dry etching, and the side surfaces of the high-concentration n ⁺ diffusion layer 3a and the first insulating film 5 are formed. And sidewall insulating films 6a are formed on the side surfaces of the low-concentration n ^- diffusion layer 3b and the first insulating film 5, respectively. The side wall insulating film 6a insulates the high concentration n ⁺ diffusion layer 3a and the low concentration n ⁻ diffusion layer 3b, and has a shorter effective gate length than the opening dimension having a width of 0.5 μm. The width of the side wall insulating film 6a is set to 0.
If it is 1 μm, the effective gate length becomes 0.3 μm.

Next, as shown in FIG.
After the gate oxide film 7 is formed by thermal oxidation, it is pressed by heat treatment to form a diffusion layer in the p ⁻ epitaxial layer 2. That is, the high concentration n ⁺ diffusion layer 3a and the low concentration n ⁻ diffusion layer 3
b, the source high concentration n ⁺ diffusion layer 8
a and the drain lightly doped n ⁻ diffusion layer 8b are formed. The pressing is adjusted so that the high-concentration n ⁺ diffusion layer 8a and the low-concentration n ⁻ diffusion layer 8b are diffused in the lateral direction by the width of the sidewall insulating film 6a.

Next, as shown in FIG. 4A, a p-type channel diffusion layer 9 is formed on the entire surface of the first insulating film 5 by, for example, ion implantation.

Next, as shown in FIG.
As the electrode material 15, for example, a high concentration n ⁺Polycrystalline silicon film
Formed so as to fill the first insulating film 5 and the opening 14.
And is deposited on the entire surface.

Next, as shown in FIG. 4C, the PR film 4c
Then, the gate electrode material is dry-etched, for example, to form a gate electrode 10 having a T-shaped cross section.

Next, as shown in FIG. 4D, for example, an SiO ₂ film is deposited as an interlayer insulating film 11 on the entire surface of the gate electrode 10 and the first insulating film 5.

Next, as shown in FIG.
d, the interlayer insulating film 11, the first insulating film 5, the high-concentration n ⁺ diffusion layer 3a and the low-concentration n ^- diffusion layer 3b are etched to form a source high-concentration n ⁺ diffusion layer 8a side and a drain low-concentration layer. A contact portion 12a with the concentration n ⁻ diffusion layer 8b side;
Open 12b. Further, for example, the source high-concentration n ⁺ diffusion layer 8a and the drain low-concentration n ⁻
High-concentration n ⁺ diffusion layers 12 are formed at both ends of the diffusion layer 8b.

Next, for example, as shown in FIG.
Al is deposited on the entire surface as the electrode material 13.

Next, as shown in FIG.
The source electrode 13a and the drain electrode 13b are formed by patterning e and performing dry etching of the electrode material, for example.

As described above, as shown in FIG. 6B, an asymmetric power MOSFET having different impurity concentrations in the source / drain regions can be formed.

In the present embodiment, after depositing an insulating material such as SiO ₂ in the opening 14, the sidewall insulating film 6a is formed in the opening 14 by anisotropic dry etching, thereby forming the film by photolithography. The opening 1 is larger by the width of the formed sidewall insulating film 6a than the size of the formed opening.
4 can be shortened. Therefore, a gate length smaller than the opening size determined by lithography can be easily realized by self-alignment.

[0043] In the present embodiment, p ^- high density different respective impurity concentration formed on the polycrystalline silicon layer 3 deposited on the epitaxial layer 2 p ⁺ diffusion layer 3a and the low-concentration p ^- diffusion layer 3b, asymmetrical sources with different impurity concentrations in the same substrate
A drain region can be formed.

Further, in this embodiment, the gate electrode 1
By forming 0 into a T-shaped cross section, it is possible to prevent the gate cross-sectional area from being reduced even if the effective gate length is reduced.

A second embodiment of the present invention will be described in detail with reference to the accompanying drawings. The same components as those in the first embodiment shown in FIGS. 1 to 6 are denoted by the same reference numerals, and detailed description thereof will be omitted. FIG. 7 is a sectional view showing a power MOSFET according to a second embodiment of the present invention.

The power MOSFET according to the present embodiment is different from the first embodiment in that the interlayer insulating film 11 is not formed and the shapes of the source electrode 13a and the drain electrode 13b are different. Otherwise, the configuration is the same as that of the first embodiment.

In this embodiment, the high concentration n ⁺ diffusion layer 3
a and a first insulating film 5, a side wall insulating film 6 a is formed on a side surface of the first insulating film 5, and a side wall insulating film 6 a is formed on a side surface of the low-concentration n ⁻ diffusion layer 3 b and the first insulating film 5. The gate length can be shorter than the opening size. As a result, a gate length finer than the capability of the patterning process of the PR film can be formed.

Next, the power MOSFET according to the present embodiment
Will be described with reference to FIG. In the manufacturing method of the present embodiment, as compared with the manufacturing method of the first embodiment, the gate electrode 10 and the source electrode shown in FIG. 1
The manufacturing method is the same as that of the first embodiment except that the gate electrode 3a and the gate electrode 13b are simultaneously formed.

In the present embodiment, the gate electrode 10, the source electrode 13a and the gate electrode 13b can be formed simultaneously, and the number of steps can be reduced as compared with the first embodiment.

[0050] In any of the embodiments described above, the substrate, p on p ⁺ substrate 1 as shown in FIG. 2 (a) ^- not just the structure deposited epitaxial layer 2, p ^- substrate by single of It may have a layered structure. As shown in FIGS. 2B and 2C, the method of forming the high concentration n ⁺ diffusion layer 3a and the low concentration n ⁻ diffusion layer 3b in the polycrystalline silicon layer 3 is limited to ion implantation. Instead, it can be formed by gas diffusion or solid phase diffusion.

Further, as shown in FIG.
^{Although the} conductive polycrystalline silicon layer 3 was used as a solid-phase diffusion source for forming the ⁺ diffusion layer 8a and the drain n ^- diffusion layer 8b, the present invention is not particularly limited to this.
The solid-phase diffusion source does not need to be conductive, and an insulator such as SiO ₂ can be used. Further, the material of the gate electrode 10 shown in FIG. 4C is not limited to high-concentration n ⁺ polycrystalline silicon, and other conductive substances such as WSi, Mo, and Al can be used. .

In each of the above embodiments, as shown in FIG. 6A, the gate electrode 10 is not limited to Al, but may be made of another conductive material such as Cu or Au. Can be used. Further, the interlayer insulating film shown in FIG. 6B is not limited to SiO ₂ ,
An insulating film made of another insulating material such as iN can be used.

Further, in any of the above embodiments,
By inverting the conductivity type of each layer, that is, p-type and n-type, a p-channel power MOSFET can of course be formed.

[0054]

As described in detail above, in the present invention,
By forming the sidewall insulating film on the opposing surface of the first insulating film on the channel diffusion layer side, the gate length can be shorter than the opening dimension of the opening formed by photolithography. Accordingly, by self-aligning the gate length, an effective gate length finer than the opening size determined by photolithography can be easily realized.

[Brief description of the drawings]

FIG. 1 is a power MOSFET according to a first embodiment of the present invention.
FIG.

FIGS. 2A to 2D are cross-sectional views illustrating a method of manufacturing the power MOSFET according to the first embodiment of the present invention in the order of steps.

3 (a) to 3 (d) are cross-sectional views showing the next step of FIG. 2 in the order of steps.

FIGS. 4A to 4D are cross-sectional views showing the next step of FIG. 3 in the order of steps.

FIGS. 5A and 5B are cross-sectional views showing the next step of FIG. 4 in the order of steps.

FIGS. 6A and 6B are cross-sectional views showing the next step of FIG. 5 in the order of steps.

FIG. 7 is a power MOSFET according to a second embodiment of the present invention.
FIG.

FIG. 8 is a sectional view showing a conventional power MOSFET.

FIG. 9 is a cross-sectional view showing a method for forming a diffusion layer of a conventional power MOSFET.

FIG. 10 is a schematic diagram illustrating patterning of a PR film on a gate electrode in a conventional power MOSFET.

[Explanation of symbols]

1, 100; p ⁺ substrate ^2, 101; p ⁻ epitaxial layer 3; polycrystalline silicon layer 3a; high concentration n ⁺ diffusion layer 3b; low concentration n ⁻ diffusion layer 4, 4a, 4b, 4c, 4d, 4e, 111 Photoresist film (PR film) 5; first insulating film 6; second insulating film 6a; sidewall insulating films 7, 106; gate insulating films 8a, 103; source high-concentration n ⁺ diffusion layers 8b, 104; Low-concentration n ^- diffusion layers 9, 102; p-type channel diffusion layers 10, 107; gate electrodes 11, 108; interlayer insulating films 12, 105; high-concentration n ⁺ diffusion layers 12a, 12b; contact portions 13; 109; source electrode 13b, 110; drain electrode 14; opening 15; gate electrode material

Claims (6)

[Claims] A semiconductor substrate; a source diffusion layer formed on the surface of the semiconductor substrate; a drain diffusion layer formed on the surface of the semiconductor substrate and having a lower impurity concentration than the source diffusion layer; A channel diffusion layer formed between the drain diffusion layer, a first insulating film formed on the source diffusion layer and the drain diffusion layer, respectively, and the channel diffusion layer in the first insulating film; A side wall insulating film formed on the layer-side facing surface; a gate insulating film formed on the channel diffusion layer; and a gate electrode formed on the gate insulating film. Power MOSFET. 2. A first diffusion layer is formed between the source diffusion layer and the first insulation film, and the first diffusion layer is formed between the drain diffusion layer and the first insulation film. 2. The power MOSFET according to claim 1, wherein a second diffusion layer having a lower impurity concentration than the diffusion layer is formed. 3. The semiconductor device according to claim 1, wherein an epitaxial layer is formed on the semiconductor substrate.
3. The power MOSFET according to 1. 4. The device according to claim 1, wherein said gate electrode is formed in a T-shaped cross section.
The power MOSFET according to the paragraph. 5. A step of forming an epitaxial layer on a semiconductor substrate, a step of forming a polycrystalline silicon layer on the epitaxial layer, and patterning a first resist film on the polycrystalline silicon layer. Forming a first diffusion layer, and patterning a second resist film on the polycrystalline silicon layer to form a second diffusion layer having an impurity concentration lower than that of the first diffusion layer. Forming an opening reaching the epitaxial layer after forming a first insulating film on the polycrystalline silicon layer, between a region where a source diffusion layer is to be formed and a region where a drain diffusion layer is to be formed; Forming a sidewall insulating film on a surface of the first insulating film facing the channel diffusion layer, forming a gate insulating film on the epitaxial layer between the sidewall insulating films, Forming a source diffusion layer and a drain diffusion layer having a lower impurity concentration than the source diffusion layer, and a step of forming a gate electrode on the gate insulating film.
Manufacturing method. 6. A step of patterning a third resist film to open contact portions of a source diffusion layer and a drain diffusion layer as a post-process of forming a gate electrode on the gate insulating film; Forming a high-concentration diffusion layer by injecting ions into the portion, forming a conductive metal film, and forming a source electrode and a drain electrode by patterning the conductive metal film. The power MOSFE according to claim 4, wherein
Manufacturing method of T.