JP2000200845A - Semiconductor amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the effect of ripple on the power supply side, and the like, by setting the electrode of a first transistor at such a potential as the junction of the surrounding region and the inside region is biased reversely. SOLUTION: A circuit of NMOS differential transistor Tr1, Tr2 is provided in a floating region 23 along with constant current sources 25, 26 of Tr3-Tr6. The Tr1, Tr2 operating at the negative power supply side potential where the potential at any electrode of source, drain or gate is equal to or lower than the ground potential GND are floated from a substrate along with the Tr3-Tr6. Consequently, these NMOS transistor Tr1-Tr6 can be operated from an independent power supply separately from the positive power supply for bipolar transistors Q3, Q4, Q7. Since respective circuits operate using the ground GND as a reference potential, power supply ripple is reduced by a factor of two or more as compared with conventional case.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor amplifier circuit, and more particularly to an amplifier circuit driven by positive and negative power supplies such as an OP amplifier or a push-pull drive amplifier having an output at an intermediate potential between a power supply line and ground GND. The present invention relates to a semiconductor amplifier circuit that is not easily affected by noise such as power supply ripple in a circuit.

[0002]

2. Description of the Related Art Amplifying circuits for audio equipment and various amplifying circuits using OP amplifiers are driven by a single power supply, or driven by both a positive power supply and a negative power supply. is there. In a single power supply, a semiconductor substrate side (hereinafter simply referred to as a substrate side or a substrate) is usually connected to a ground line (G).
ND) or connected to a power supply line and set it to a reference potential. Also, with dual power supplies, instead of ground potential,
The amplifier circuit is designed and operated by selecting either the positive side or the lowest potential side power supply line as a potential reference.

As shown in FIG. 4A, a transistor constituting this kind of semiconductor amplifier circuit is formed by a drive transistor 20 provided with, for example, a P-type substrate 21 provided with P ⁺ isolation. This amplifier circuit
An equivalent transistor circuit 2 as shown in FIG.
2, the input signal is applied to the input terminal IN and output from the output terminal OUT. In such a circuit, as shown as a diode Dk, a parasitic diode is simultaneously formed in the opposite direction between the emitter and the base or between the emitter and the collector via the P-type substrate 21, and a parasitic capacitance Ck is also formed. You. Such a parasitic element such as a diode and a parasitic capacitance are represented by I
When a voltage lower than the reference potential set at the input terminal IN is applied, the parasitic diode Dk is turned on, and a current flows from the substrate side to each transistor formation layer. There is a flowing problem. Therefore, normally, a voltage lower than the potential of the substrate (reference potential) is not applied to the input terminal IN. Therefore, the above-described potential reference must be adopted.

FIG. 5 is a circuit diagram of a semiconductor amplifier circuit that operates using both positive and negative power supplies. In FIG. 5, 8 is
An amplifier circuit formed in a semiconductor integrated circuit, comprising: an amplifier circuit 1; and constant current sources 2, 3 connected to a negative power supply line -Vcc.
The amplifier circuit 1 has an input terminal 8a and an output terminal 8b, and has a differential amplifier circuit 4 as an input stage.
However, an output amplifier 5 is provided as an output stage, and is constituted by these. The input signal Vin is applied to the input terminal 8a from the previous stage. The differential amplifier circuit 4 has np
The common emitters of the n-type differential transistors Q1 and Q2 are connected to the constant current source 2, and through this, the negative power supply line -Vcc
It is connected to the. The pnp-type transistors Q3 and Q4 of the current mirror are provided as loads on the respective collector sides, and these are connected to the positive power supply line + Vcc.

The constant current source 2 is composed of npn transistors Q5 and Q6 of a current mirror. The diode-connected transistor Q6 on the input side receives a constant current from the constant current source 7 so that the output transistor Q5 of the current mirror is turned on. A constant current from the common emitter of the differential transistors Q1, Q2 is sinked. The base of the differential transistor Q1 is
The input terminal 8a is connected via the resistor Rs, and the base of the differential transistor Q2 is grounded. Output amplifier 5
Is composed of a pnp transistor Q7 having an emitter connected to the power supply line + Vcc, a collector connected to the output terminal 8b, further connected to the negative power supply line -Vcc via the constant current source 3, and Receive input signal,
Its base is connected to the collector of the differential transistor Q1. The voltage at the output terminal 8b is equal to the return resistance Rf.
Is connected to the base of the differential transistor Q1. The constant current source 3 has the same configuration as that of the constant current source 2 and therefore will not be described.

[0006]

In the circuit shown in FIG. 5, the reference potential normally applied to the substrate is applied to the negative power supply line -Vcc. In such a circuit, the ground GND between the positive and negative power supplies is not used as the reference potential for the above-described reason. Therefore, the output signal Vo obtained at the output terminal 8b is susceptible to fluctuations in the substrate potential. In particular,
Since an integrated circuit operates a large number of circuits, a ripple always accompanies its power supply voltage. Since the substrate side (negative side power supply line -Vcc) and the + Vcc power supply line side are relative to each other, when this ripple is viewed from the + Vcc power supply line side, the substrate side fluctuates with the ripple voltage. Therefore, when the potential of the substrate fluctuates due to the ripple, first, a signal enters each integrated circuit via the parasitic capacitance Ck, and the signal easily appears as a noise signal. In the worst case, the parasitic diode Dk
Is turned on, and the circuit malfunctions.

The problem of such power supply ripple is, in particular,
This is a major problem when an amplifier circuit driven by both positive and negative power supplies is integrated in one semiconductor. This is because the potential difference between the positive and negative power supplies increases, and the circuit that generates the negative power supply internally operates by receiving the power from the positive power supply circuit to obtain negative power. This is because it will double. An object of the present invention is to solve such problems of the prior art,
An object of the present invention is to provide a semiconductor amplifier circuit which is hardly affected by noise such as power supply ripple when using both positive and negative power supplies and a single power supply.

[0008]

In order to achieve this object, a semiconductor amplifying circuit according to the present invention has a well formed on a semiconductor substrate of one of P-type and N-type. A region, a surrounding region of the other of the P-type and N-type formed on the periphery and bottom of the well region so as to surround the region inside the well region, and a first transistor formed in the inside region. And a second transistor formed on the surface of the substrate other than the well region. In the operating state of the first and second transistors, a reference potential is set on the substrate, and the surrounding region has the same potential as the substrate. Alternatively, the first transistor is set to a potential at which the junction between the surrounding region and the substrate is reverse biased and the junction between the surrounding region and the inner region is reverse biased. Both in which one electrode is set.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In such an amplifier circuit,
The surrounding region formed in the well region is of a different type from the substrate, and the same potential as the substrate when the substrate is set to the reference potential, or the potential at which the junction between the surrounding region and the substrate is reverse-biased , And at least one electrode of the first transistor is set to a potential at which a junction between the surrounding region and the inner region is reverse-biased. Accordingly, the region and the element formed in the inner region can be set in a floating state with respect to the substrate, and the first transistor formed in the inner region can be separated from the substrate and operated. As a result, the first transistor and the second transistor can be independently operated by different power supplies, so that the first transistor is operated by setting the substrate to the reference potential corresponding to the second transistor, Can be operated at the second power supply at a potential lower than the first power supply.

In this case, the ripple of the power supply voltage is higher on the larger side of the first power supply voltage and the second power supply voltage when viewed from the reference potential (substrate). If the first power supply voltage is equal to the second power supply voltage, the power supply voltage is substantially halved, and accordingly, the potential fluctuation on the substrate side due to noise such as ripples is reduced, and the amplifier circuit is less affected by the fluctuation. Can be configured. In the case of positive / negative power supply driving, the half of the reference potential becomes the ground GND. As a result, it is an object of the present invention to provide a semiconductor amplifier circuit which is hardly affected by noise such as power supply ripple in dual power supply driving and single power supply driving.

[0011]

FIG. 1 is an explanatory diagram of an amplifying circuit according to an embodiment to which a semiconductor amplifying circuit of the present invention is applied, which uses a ground GND as a reference potential by driving both positive and negative power supplies.
Are N-M arranged on the negative power supply side in the amplifier circuit.
FIG. 3 is a cross-sectional view of the OS transistor formation region, and FIG.
FIG. 4 is an explanatory diagram showing a connection relationship between a bipolar transistor and an N-MOS transistor in a cross-sectional structure. In FIG. 1, reference numeral 9 denotes a semiconductor amplifier circuit, and reference numeral 23 denotes a well region (floating region) in which a transistor in a floating state is formed from the substrate side, in which N-MOS transistors Tr1 to Tr6 are formed. Have been. The bipolar transistors Q3 and Q4 formed in regions other than the floating region 23 have the same circuit as that of FIG. 5 and are transistors formed on the substrate as in the prior art. Note that the same components as those in FIG. 5 are denoted by the same reference numerals, and description thereof will be omitted.

The floating region 23 shown in FIG.
5 is provided with N-MOS differential transistors Tr1 and Tr2 in place of the differential transistors Q1 and Q2 of FIG.
Of the constant current sources 2 and 3 are N-MOS transistors T
A circuit is provided which is replaced by constant current sources 25 and 26 based on r3 to Tr6. The constant current source 25 is formed of a current mirror including N-MOS transistors Tr3 and Tr4. The transistor Tr4 on the input side is diode-connected, and receives the current from the constant current source 27 on the drain side.
The drain of the transistor Tr3 on the output side is connected to a common source of the differential transistors Tr1 and Tr2, and sinks a constant current from this source. Transistors Tr3, T
The source side of r4 is commonly connected and connected to the negative power supply line -Vcc. The constant current source 26 is also a constant current source 25
Has the same structure as that of the N-MOS transistor Tr5,
The input side transistor Tr6 is diode-connected, receives the current from the constant current source 28 on the drain side, and the drain of the output side transistor Tr5 is connected to the collector of the output transistor Q7. A constant current is sinked from this collector.
The sources of the transistors Tr5 and Tr6 are commonly connected and connected to the negative power supply line -Vcc.

As described above, one of the electrodes of the source (S), the drain (D) and the gate (G) is set to the ground potential GND or lower, and the transistors Tr1 and Tr2 and the transistors Tr1 and Tr2 operating at the negative power supply side potential. Side power line -Vcc
The transistors Tr3 to Tr6 connected to the
From the N-MOS transistors Tr1 to Tr6 so that the bipolar transistors Q3,
It can be operated by an independent power supply separate from the positive power supply of Q4 and Q7. Therefore, the amplifying circuit portion including the bipolar transistors Q3, Q4, Q7 is connected to the ground GND.
Can be operated with the positive power supply based on Further, the N-MOS transistors Tr1 to Tr6 can be similarly operated by the negative power supply with reference to the ground.
Thus, each circuit is connected to the ground GND (the substrate 11
The power supply ripple is caused by the positive power supply line + Vcc and the negative power supply line -Vcc.
Is less than or equal to half of the conventional case based on either of the above. These N-MOS transistors Tr1 to Tr6 arranged in the floating region 23 are transistors formed in the N-MOS transistor formation region 10 shown in the sectional structural view of FIG.

FIG. 2 shows the structure of an N-MOS transistor amplifying circuit which can operate independently on the ground GND as a reference potential or at a potential lower than the reference potential or on the negative power supply side. As an N-MOS transistor formation region 10, an N buried layer (B / L) 12 is formed on a P-sub (P-type substrate) substrate 11 by epitaxial growth, and an oxide film is removed to form the N buried layer 12. P ⁺ ions are implanted or applied, and then N buried layer 1
An N ^- epitaxial layer is formed on the P-type layer and the N-type layer in order to form the P-well region 13 on the semiconductor substrate 2. As a result, the region implanted with P ⁺ ions is the P well region 1
3 and an N ^- region is formed outside the region. At this time, P
The range of the well region 13 is slightly smaller than the range of the N buried layer 12 and smaller than the range of the N buried layer 12, and the outside thereof is the N ⁻ region.

Further, the N ⁻ region formed around the outside of the P well region 13 is doped with an N-type impurity and diffused to couple the N diffusion separation region 14 to the outer periphery of the N buried layer 12 as a diffusion separation region. Formed. As a result, the diffusion isolation region 14 becomes a circular or rectangular outer peripheral wall with respect to the P well region 13 when viewed from a plane, and surrounds the substrate P with the reverse type of N with the N buried layer 12 as the bottom surface. A P-type well region 13 is formed. As a result, the P-well region 13 is formed on the P-sub substrate 11 with the N-type layer interposed therebetween, so that the N diffusion isolation region 14 is set by the potential setting of the region surrounded by the N buried layer 12.
The region formed in the P well region 13 floats from the substrate 11. That is, if the potential of the surrounding region of the P well region 13 is set equal to the potential of the substrate 11 or the potential between the substrate 11 and the P well region 13,
In the operating state, at least one of the NP junctions on both sides of the surrounding region is separated by the formation of the space charge layer due to the reverse bias, so that the element formed by the P well region 13 is It is in a floating state as viewed from the substrate 11. In the figure, reference numeral 15 denotes an element isolation oxide film layer (LOCOS). Also, the diffusion isolation region 14
Represents the P well region 1 corresponding to the width of the N buried layer 11.
3 is provided around the side surface of P3.
For the well region 13, a collector wall (colle)
c.wall, C / W).

The inside of the P well region 13 has a surface.
N diffused on the side⁺Source region 13a and drain
Region 13b is on the surface side with the channel forming region 16 interposed therebetween.
Is formed. 17 is a gate layer. This gate
The layer 17, the source region 13a, and the drain region 13b are
Gate G, source S, drain via Al wiring
Extracted as D. Also, collector wall diffusion
The separation area 14 has N as an extraction area. ⁺Extraction area 14a
Is provided on the upper surface by diffusion. this
The extraction area 14a is connected to the power supply line + Vcc through the Al wiring.
It is connected to the. Also, the P well area 13 has
P as area⁺Area 13c is diffused on the upper surface
It is provided and provided. This extraction area 13c is a P-type
Of the well region 13 as a back gate through the Al wiring
This is connected to the source S, and the source S is connected to the negative power line
-Vcc. Note that this N-MOS transistor
The transistor formed in the transistor forming region 10 is shown in FIG.
The transistors Tr3 to Tr5 forming the constant current source shown in FIG.
One of them. As shown, the source S is on the negative side.
Is connected to the power supply line -Vcc, and the drain D is an input terminal.
It is 18. This input terminal 18
Receives current flowing out of the resistor. In addition, the substrate 11
It is connected to ground GND.

The P-well region 13 is formed by N
Is formed as an integral tub-like region formed by the diffusion separation region 14 and the N buried layer 11 at the bottom. Therefore, in the potential setting of the operation state as described above, the surrounding area such as the tub is set to the potential of the power supply line + Vcc, and the substrate 11
Is connected to the ground GND and becomes the ground potential, the NP junction between the surrounding region and the substrate 11 is reverse-biased, and a space charge layer is formed between them. Further, the N-P junction between the surrounding region and the P-well region 13 is also reverse-biased, and a space charge layer is formed between them. As a result, the P-well region 13 is separated from the substrate 11, so that an element (or an element region) formed in this region floats with respect to the substrate. As a result, as shown in FIG. 1, it is possible to operate by independently providing a power supply.

The transistors Tr1 to Tr6 formed in the N-MOS transistor formation region 10 of FIG.
Requires twice the power supply voltage between the drain D and the source S. That is, if the power supply voltage is 5 V, + Vcc = + 5
V, -Vcc = -5V, which is twice the power of a normal transistor and operates with a power supply of a total of 10V, which requires a transistor with a withstand voltage. Therefore, depending on the power supply voltage to be used, the thickness and the concentration (resistivity) of the P-well region 13 pose problems. Since a normal power supply voltage of 3 V to 5 V is used, in this case, the actual thickness of the P well region 13 is about several μm to 10 μm.
At this time, if the concentration is such that the sheet resistance is 2 kΩ to 5 kΩ, it is possible to form a transistor having a required withstand voltage in the well region 13 even if two positive and negative power supplies are used.

When a transistor having a low withstand voltage is formed in the well region 13, the surrounding region formed by the N diffusion isolation region 14 and the N buried layer 12 is ground GND.
Or a potential on the + side slightly larger than this. When the trough-shaped surrounding region of the diffusion isolation region 14 and the buried layer 12 is set to the ground potential, the substrate 11
Therefore, the NP junction with the substrate 11 does not become reverse biased, and becomes a parasitic diode due to the PN junction when viewed from the substrate 11 side. However, when the well region 13 side is viewed from the substrate 11 side, there is a region of N tub between the well region 13 side.
And the well region 13 are separated. At this time, when the substrate 11 is viewed from the N diffusion isolation region 14 and the N buried layer 11 side, a parasitic diode in the opposite direction is inserted, and these surrounding regions and the substrate 11 are set to the same potential. Therefore, no current flows between them.

FIG. 3 shows bipolar transistors Q4 and N
-Cross-sectional structure of connection with MOS transistor Tr2
FIG. Bipolar transistor Q4
And the N-MOS transistor Tr2 are located on the surface of the substrate 11.
Are arranged adjacent to each other. Bipolar Transient
The star Q4 has a well similar to the bipolar transistor Q3.
It is formed on the surface other than the region 13. Bipolar Transient
The structure of the star Q4 is lateral as a PNP transistor.
FIG. 4 shows a general structure of a pnp transistor.
The structure is slightly different from that of. This is the base of N
On the buried layer 31, N^-Well region 32 is formed,
This becomes the base region, and the N side
The kuta wall 35 is formed and the upper surface of the well region 32 is formed.
On the surface, P ⁺Collector region 33 and P⁺Emitter of
A region 34 is formed on the surface of the collector wall 35.
An extraction area is provided, and collector C, base B,
The electrode of this transistor is taken out as a terminal E.
This structure is the same for the transistor Q3.
Reference numeral 36 denotes an element isolation region (ISO).

The N-MOS transistor Tr2 has the same structure as that of FIG. 2, but has a source S, a gate G, and a drain D.
Are different from each other. The source S of the N-MOS transistor Tr2 of FIG. 3 is connected to the drain D of the transistor Tr3 formed with the structure of FIG. The bipolar transistor Q4 has its base B and collector C commonly connected to the drain D of the transistor Tr2 in FIG. 3, and its emitter E connected to a + Vcc power supply line. On the other hand, the bipolar transistor Q3 has its base B connected to the base B of the bipolar transistor Q4 in FIG. 3, its emitter E connected to the + Vcc power supply line, and its collector C connected to the drain D of the N-MOS transistor Tr1. , And has the same structure as the transistor Q4 in FIG. The N-MOS transistor Tr1 has a structure similar to that of FIG. 3 in which a bipolar transistor Q3 is formed adjacent thereto. The connection is such that the collector C of the transistor Q3 is connected to the drain D of the transistor Tr1, and the gate G is connected to the terminal 8a via the resistor Rs.
And the source S is connected to the source S of the transistor Tr1.
Is connected to And the structure is NM of FIG.
This is the same as the OS transistor Tr2.

By the way, as shown in FIG. 1, the potential on the drain D side of the transistors Tr1 and Tr2 connected to the collectors of the bipolar transistors Q3 and Q4 is
The potential of ND (reference potential) or a value higher than ND, but these sources S have a potential lower than the ground GND potential. This is because the potential of the substrate 11 must be set to ground as a reference potential, and the well region 13 and the junction between the diffusion isolation region 14 and the N buried layer 11 must be reverse-biased. As a result, the bipolar transistors Q3, Q4, Q
7 operates at a potential higher than this including the reference potential,
The OS transistors Tr1 to Tr6 have at least one electrode set to a potential lower than the reference potential, and mainly operate at a potential lower than the reference potential.

As described above, in the embodiment of FIG.
Although an example of positive and negative power supply drive is described, in the case of one power supply of either positive or negative, the ground GND is + Vcc / 2.
Alternatively, -Vcc / 2 may be set as the reference potential on the substrate. As a result, the reference voltage can be halved with respect to the power supply, and the same operation and effect can be obtained. In addition, according to the present invention, a transistor may be formed in a region which is in a floating state with respect to a substrate, and the transistor to be formed is not limited to an N-MOS transistor. Further, in the embodiment, a P-type semiconductor substrate is taken as an example, but an N-type semiconductor substrate may be used. In this case, in FIG. 1, the pnp type transistor is changed to an npn type transistor, and the npn type transistor is changed to a pnp type transistor.
The OS transistor is changed to a P-MOS transistor. In the region surrounding the N-well region, a potential equal to or lower than that of the N-substrate is set, and a potential lower than that of the N-well region is set. As a result, at least a region between the surrounding region and the N-well region has a reverse bias. 2 and 3, the N-type region becomes P-type, and the P-type region becomes N-type.

[0024]

As can be understood from the above description, according to the present invention, the surrounding region formed in the well region is of a different type from the substrate, and when the substrate is set at the reference potential, it becomes the same as the substrate. A potential or a potential at which a junction between the surrounding region and the substrate side is reverse-biased, and at least one electrode of the first transistor is reverse-biased at a junction between the surrounding region and the inner region. It is set to the state potential. Accordingly, the region and the element formed in the inner region can be set in a floating state with respect to the substrate, and the first transistor formed in the inner region can be separated from the substrate and operated. Accordingly, the first transistor and the second transistor can be independently operated by different power supplies. Therefore, the first transistor is operated by using the substrate as a reference potential corresponding to the second transistor, and the first transistor is operated.
Can be operated at the second power supply at a potential lower than the first power supply. As a result, it is an object of the present invention to provide a semiconductor amplifier circuit which is hardly affected by noise such as power supply ripple at both power supplies and at one power supply.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of an amplifying circuit according to an embodiment to which a semiconductor amplifying circuit of the present invention is applied, which uses a ground GND as a reference potential by driving both positive and negative power supplies.

FIG. 2 is a cross-sectional view of an N-MOS transistor forming region arranged on a negative power supply side in the amplifier circuit.

FIG. 3 shows a bipolar transistor and an N-MOS.
FIG. 4 is an explanatory diagram illustrating a connection relation of transistors in a cross-sectional structure.

FIGS. 4A and 4B are explanatory diagrams of a driving transistor element in a conventional semiconductor device. FIG. 4A is a cross-sectional view of a formation region thereof, and FIG. 4B is an equivalent circuit diagram thereof.

FIG. 5 is a circuit diagram of a conventional semiconductor amplifier circuit that operates with positive and negative power supplies.

[Explanation of symbols]

1: amplifying circuit, 2, 3, 7, 25 to 28: constant current source, 4
... Differential amplifier circuit, 5 ... Output amplifier, 6 ... Differential amplifier circuit,
8, 9: semiconductor amplifier circuit, 10: N-MOS transistor formation region, 11: P-sub (P-type substrate) substrate, 12: N buried layer (B / L), 13: P-type well region, 13a: N ^{+ type} source region, 13b: drain region, 14: diffusion isolation region, 15: element isolation oxide film layer (LOCOS), 16: channel formation region, 23: floating region, Q1 to Q6: bipolar transistor,
Tr1 to Tr6 ... N-MOS transistors.

Claims (5)

[Claims] 1. A well region formed on a semiconductor substrate of one of a P-type and an N-type, which is formed of the same type as the substrate, and formed around the inner side of the well region at a periphery and a bottom surface of the well region. A surrounding region of the other of the P type and the N type, a first transistor formed in the inner region, and a second transistor formed on the surface of the substrate other than the well region. In the operating state of the first and second transistors, a reference potential is set on the substrate, and the surrounding region has the same potential as the substrate, or a junction between the surrounding region and the substrate side is reverse-biased. Semiconductor in which at least one electrode of the first transistor is set to a potential at which the junction between the surrounding region and the inner region is reverse biased. Width circuit. 2. The reference potential is substantially a half of a power supply voltage, and its electrode is operated such that one of the first and second transistors operates at a potential higher than and including the reference potential. Are set, and the first and second potentials are set.
3. The semiconductor amplifier circuit according to claim 2, wherein a potential lower than the reference potential is set to at least one other electrode of the transistor, and the transistor operates mainly with a potential lower than the reference potential. 3. The enclosing region is formed around the outside of a well region, the power supply voltage is a sum of a positive power supply voltage and a negative power supply voltage, and the reference potential is a ground potential. 3. The semiconductor amplifier circuit according to claim 2, wherein 4. The semiconductor device according to claim 1, wherein said substrate is a P-type substrate, said first transistor is a MOS transistor, said second transistor is a bipolar transistor, and said surrounding region is connected to a ground line. 3. The semiconductor amplifier circuit according to 3. 5. The semiconductor device according to claim 1, wherein the substrate is a P-type substrate, the first transistor is a MOS transistor, the second transistor is a bipolar transistor, and the surrounding region is connected to a positive power supply voltage line. And the voltage of the positive and negative power supplies is in the range of 3 V to 5 V, and the inner region is formed as an epitaxial growth layer having a depth of several μm to 10 μm, and has a sheet resistance value of The semiconductor amplifier circuit according to claim 3, wherein the resistance is 2 kΩ to 5 kΩ.