JP2000188542A - Phase locked loop - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize the oscillation operation of a phase locked loop. SOLUTION: A charge pump 15 and an LPF 16 of the same circuit configuration are provided in parallel to a charge pump 12 and an LPF 13 which are components of the phase locked loop. A bias circuit 18 gives control levels Vcp, Vcn to the charge pump 15 so as to keep a level Vr extracted from an LPF 42 constant when the charge pump 15 is driven by clocks RP, RN with a prescribed period. Fluctuation in an operation center of the charge pump 12 is prevented by giving also the control levels Vcp, Vcn to the charge pump 12 on the same configuration as the charge pump 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop for synchronizing an oscillation clock with a reference clock, and more particularly to stabilization of an oscillation frequency.

2. Description of the Related Art FIG. 5 is a block diagram showing the configuration of a phase locked loop, and FIG. 6 is a timing chart for explaining the operation of a phase comparator. The phase lock loop includes a phase comparator 1, a charge pump 2, a low-pass filter 3, and a voltage controlled oscillator 4. The phase comparator 1 compares the phase of the reference clock RK with the oscillation clock CK output from the voltage controlled oscillator 4, and outputs a comparison output PP that changes according to the phase difference between the reference clock RK and the oscillation clock CK.
Output PN. For example, as shown in FIG. 6, when the oscillation clock CK advances with respect to the reference clock RK, one comparison output PN rises, and conversely, the reference clock R
When the oscillation clock CK lags behind K, the other comparison output PP falls. The charge pump 2 includes a transistor that is turned on / off in response to the comparison outputs PP and PN, and outputs an output PD that changes in response to the comparison outputs PP and PN. For example, when the comparison output PN rises, the output-side potential is lowered to the ground potential, and when the comparison output PP falls, the output-side potential is raised to the power supply potential. When the comparison output PP is at the high level and the comparison output PN is at the low level, all the transistors are turned off, and the output side is:
High impedance. Low-pass filter (LP
F) 3 removes the AC component of the output PD of the charge pump 2 and outputs a control voltage Vc that varies according to the pulse width of the output PD. Therefore, the control voltage Vc is equal to the comparison output PN.
Rises when the output PD reaches the ground potential and rises when the comparison output PP falls and the output PD reaches the power supply potential. Voltage controlled oscillator (VCO)
Reference numeral 4 denotes, for example, a ring oscillator, which is configured to change the frequency of the oscillation clock CK by increasing or decreasing the delay amount of the feedback loop in response to the control voltage Vc. In the above lock loop, when the phase of the oscillation clock CK is shifted with respect to the reference clock RK, the oscillation of the VCO 14 is controlled in a direction opposite to the shift, so that the oscillation clock CK is synchronized with the reference clock RK. Become.

The output P of the phase comparator 1
In the charge pump 2 operating in response to P and PN, it is desirable that the current flowing from the output side in response to the fall of the comparison output PP be equal to the current flowing to the output side in response to the comparison output PN. That is, the charge pump 2
In this case, when the balance between the current flowing from the output side and the current flowing to the output side does not match, the reference clock R
A bias occurs in the phase difference between K and the oscillation clock CK, and stable operation cannot be maintained. As a result, the operation becomes unstable due to the influence of external noise or the like, and the lock may be lost. Therefore, an object of the present invention is to stabilize the operation of the phase locked loop by keeping the current flowing through the charge pump equal during charging and during discharging. \

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the feature thereof is a voltage control for changing the frequency of an oscillation clock in response to a change in a control voltage. An oscillator, a phase comparator for comparing the phase of the oscillation clock with a reference clock having a predetermined period, and a first for selectively outputting a first potential or a second potential according to a comparison output of the phase comparator. A charge pump, a first low-pass filter for smoothing the output of the first charge pump to generate the control voltage, and a first low-pass filter for selectively outputting the first potential or the second potential at a predetermined cycle. 2, a second low-pass filter for smoothing the output of the second charge pump to generate a compensation voltage, and the first and second charge pumps in response to the compensation voltage.
The first and second extracted from the low-pass filter of
And a control unit for controlling the potential of the control signal. According to the present invention, in the second reference charge pump, feedback control is performed so that a current flowing during charging is equal to a current flowing during discharging, and the feedback information forms a phase locked loop. It is also supplied to one charge pump. First
By setting the charge pump and the second charge pump to have the same operation characteristics, the first charge pump is controlled so that the current flowing at the time of charging is equal to the current flowing at the time of discharging.

FIG. 1 is a block diagram showing a first embodiment of a phase locked loop according to the present invention. The phase-locked loop of the present invention includes a phase comparator 11, a first charge pump 12, a first low-pass filter 13, and a voltage-controlled oscillator 14, a second charge pump 15,
, A low-pass filter 16, an A / D converter 17 and a bias circuit 18. The phase comparator 11 compares the phase of the reference clock RK with the oscillation clock CK output from the voltage controlled oscillator 14, and compares the comparison output P that changes according to the phase difference between the reference clock RK and the oscillation clock CK.
P and PN are output. In this phase comparator 11,
When the reference clock RK and the oscillation clock CK have a certain phase difference, they are treated as being synchronized with each other. The first charge pump 12 includes comparison outputs PP, PN
, And transistors that control the current flowing through these transistors in response to control potentials Vcp and Vcn provided from the bias circuit 18 in response to the comparison outputs PP and PN. The output PD that changes is output. First low-pass filter (LP
F) 13 removes the AC component of the output PD of the charge pump 12 and outputs a control voltage Vc that varies according to the pulse width of the output PD. Voltage controlled oscillator (VCO) 14
Is constituted by, for example, a ring oscillator, and is configured to change the frequency of the oscillation clock CK in response to the control voltage Vc. From the above phase comparator 11 to the VCO
The operations up to 14 correspond to the phase locked loop shown in FIG. The second charge pump 15 has the same configuration as the first charge pump 12, and changes in response to a pair of clocks RP and RN having a fixed period, respectively, and in response to the clocks RP and RN. Output the output RD.
Here, the clocks RP and RN are generated such that the P-channel transistor and the N-channel transistor constituting the second charge pump are turned on for an equal time without overlapping each other. For example, the clock RP is set to have a duty ratio of 3/4, and the clock RN is set.
Is set to 1/4 and the clock R
The rising edge of the clock RN is set to 1 for the falling edge of P.
/ 2 periods. The second low-pass filter (LPF) 16 includes a second charge pump 15
Removes the AC component of the output RD, and varies the initially set potential Vr0 according to the pulse width of the output RD.
Is output. The potential Vr extracted from the second LPF 16 is maintained at a constant value while the current flowing during charging and the current flowing during discharging are maintained equal in the second charge pump 15. That is, in the second charge pump 15, since the charging time and the discharging time are set equal by the clocks RP and RN, the second LPF
As long as the charge current and the discharge current for 16 are equal, the output potential Vr is maintained at the initially set potential Vr0. Here, as for the potential Vr0 of the initial setting in the second LPF 16, the control voltage Vc obtained from the first LPF 13 is used.
Is set to match. The A / D converter 17 converts the voltage Vr input from the second LPF 17 into a digital value, and generates control information SC. Then, the bias circuit 18 generates control potentials Vcp and Vcn based on the control information SC input from the A / D converter 17 and supplies the control potentials to the first and second charge pumps 12 and 15. The control potentials Vcp and Vcn are used to control the charge current and the discharge current in each of the charge pumps 12 and 15.
By maintaining the potential Vr obtained from the LPF 16 at a predetermined potential, the charge currents of the charge pumps 12 and 15 are controlled to be equal. First and second
When the balance between the charging current and the discharging current is lost in the charge pumps 12 and 15, the output potential Vr of the second LPF 16 fluctuates. This change in the output potential Vr is transmitted to the bias circuit 18 as a change in the control information SC, and the control potentials Vcp and Vcn fluctuate in a direction in which the charge current and the discharge current of each of the charge pump circuits 12 and 15 match. . As a result, in each of the charge pumps 12 and 15, the balance between the charge current and the discharge current is always kept constant. FIG. 2 shows first and second charge pumps 12, 1
5 is a circuit diagram illustrating an example of a configuration of FIG. The configurations of these charge pumps 12 and 15 are the same. The charge pumps 12 and 15 respectively include a driving transistor 21 and a driving transistor 21.
22 and transistors 23 and 24 for current control. A driving P-channel MOS transistor 21 and an N-channel MOS transistor 22 are connected to a power supply and a ground, respectively. Then, a P-channel MOS transistor 23 and an N-channel MOS transistor 24 for current control are connected in series between the transistors 21 and 22, and a connection point between the transistors 23 and 24 / RD is extracted. The gates of the transistors 21 and 22
The comparison outputs PP and PN from the phase comparator 11 or the clocks RP and RN described above are applied, respectively. The gates of the transistors 23 and 24 are connected to a bias circuit 18.
Are applied, respectively. Therefore, when the transistor 21 is turned on in response to the comparison output PP and the clock RP, the charging current Ip flows from the power supply side to the transistor 21, and the first and second LPFs
Charge the capacity contained in 13 and 16. At the same time, when the transistor 22 is turned on in response to the comparison output PN and the clock RN, the discharge current I
n flows and discharges the capacity included in the first and second LPFs 13 and 16. At this time, since the transistor 23 for current control is connected between the transistor 21 and the output terminal, the charging current is controlled in response to the control potential Vcp. Similarly, between the transistor 22 and the output terminal,
Since the current control transistor 24 is connected, the discharge current is controlled in response to Vcn. FIG. 3 is a circuit diagram showing an example of the configuration of the bias circuit 18. Bias circuit 1
8 is a resistor 31, transistors 32 to 35, decoder 3
6, a switch group 37 and a resistor string 38.
A P-channel transistor 33 and an N-channel transistor 34 are connected in series between power supply grounds. The potential of the switch group 37 is applied to the gate of the transistor 33, and the gate of the transistor 34
It is connected to a connection point between the resistor 31 and the transistor 32. The P-channel transistor 35 for current compensation is
It is connected in parallel with transistor 33, and its gate is connected to the connection point between transistors 33 and 34. Then, a first control potential Vcp is extracted from a connection point between the transistors 33 and 34. Further, the resistor 31 and the N-channel transistor 32 are connected in series between the power supply ground and the connection point therebetween is connected to the gate of the transistor 32. Then, a first control potential Vcp is extracted from a connection point between the transistors 33 and 34. Resistance column 38
Is connected between the power supply ground and extracts a plurality of divided potentials by dividing the voltage between the power supply potential and the ground potential. Switch group 37
Is connected between the respective resistors of the resistor string 38 to selectively extract a plurality of divided potentials. The decoder 36 selects a divided potential by turning on a specific one of the switches 37 in response to the control information SC. The selected divided potential is applied to the gate of the transistor 31.
According to the above bias circuit 18, when the potential of the gate of the transistor 31 changes due to the selecting operation of the decoder 36, the second control potential Vcp changes with the change. At this time, since the first control potential Vcn is fixed, a change in the second control potential Vcp causes the transistor 2
The currents Ip flowing through the transistors 22 and 24 are
Changes in accordance with the current In flowing through. As a result, control is performed so that the charge current and the discharge current flowing through the charge pumps 12 and 15 are equal to each other. FIG. 4 is a block diagram showing a second embodiment of the phase locked loop of the present invention. In this figure, the phase comparator 11 to the VCO 14
The configuration up to this point is the same as that of the first embodiment shown in FIG. 1, and a description thereof will be omitted. 2nd charge pump 41, 2nd
The low-pass filter (LPF) 42 and the bias circuit are the same as the charge pump 15, the second LPF 16, and the bias circuit 18 of the first embodiment shown in FIG. That is, the output RD that changes in response to the clocks RP and RN having a fixed period is generated by the second charge pump 41, and the output width RD of the output RD of the second charge pump 41 is changed by the second LPF 43. A potential Vr that fluctuates accordingly is generated. Then, in response to the control information SC, control potentials Vcp and Vcn for controlling the charge current and the discharge current of the first and second charge pumps 12 and 41 are generated. The comparator 43 compares the potential Vr input from the second LPF 42 with a predetermined reference value. When the potential Vr exceeds the reference value, the comparator 43 starts up the count-up signal UP. Launch. When the reference value is set to an upper limit value and a lower limit value, and the potential Vr is between the upper limit value and the lower limit value, the count-up signal UP and the count-down signal D
Neither of W may be started. The up / down counter 44 counts up in response to a count up signal UP input from the comparator 43,
The countdown is performed in response to the countdown signal DW. As a result, control information SC that increases or decreases with a change in the potential Vr output from the second LPF 42 is generated. The control information SC generated here is the control information SC generated by the A / D converter 17 in the first embodiment.
Is the same as As described above, even when the comparator 43 and the up / down counter 44 are used, the potential Vr output from the first LPF 42 is maintained at a predetermined value, similarly to the case where the A / D converter 17 is used. Thus, the charge pumps 12 and 41 are controlled. Therefore, an operation equivalent to that of the first embodiment can be achieved.

According to the present invention, in the charge pump constituting the phase locked loop, the charge current flowing to the low-pass filter and the discharge current flowing from the low-pass filter are maintained to be always equal. For this reason, the oscillation operation of the voltage controlled oscillator can be stabilized, and a delay in locking of the phase locked loop can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a phase locked loop of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a charge pump.

FIG. 3 is a circuit diagram showing a configuration of a bias circuit.

FIG. 4 is a block diagram showing a second embodiment of the phase locked loop of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional phase locked loop.

FIG. 6 is a timing chart illustrating the operation of a conventional phase locked loop.

[Explanation of symbols]

 1, 11 Phase comparator 2, 12, 15, 41 Charge pump 3, 13, 16, 42 Low pass filter (LPF) 4, 14 Voltage controlled oscillator (VCO) 17 A / D converter 18, 45 Bias circuit 43 Comparator 44 Up / down counter

Claims (4)

[Claims] A voltage-controlled oscillator that varies a frequency of an oscillation clock in response to a change in a control voltage; a phase comparator that compares the phase of the oscillation clock with a reference clock having a predetermined period; 1st according to comparison output
A first charge pump for selectively outputting the potential of the first charge pump or a second potential; a first low-pass filter for smoothing the output of the first charge pump to generate the control voltage; A second charge pump for selectively outputting the first potential or the second potential, a second low-pass filter for smoothing the output of the second charge pump to generate a compensation voltage, and a response to the compensation voltage And a control unit that controls the first and second potentials extracted from the first and second low-pass filters. 2. The control section includes: a compensation information generating circuit that generates compensation information according to the compensation voltage; and a voltage selected according to the compensation information from a plurality of voltages set in stages. The phase-locked loop according to claim 1, wherein the first and second potentials are supplied to first and second charge pumps to control the first and second potentials. 3. The phase locked loop according to claim 2, wherein the compensation information generation circuit includes an A / D converter that converts the compensation voltage into a digital value. 4. A compensation information generating circuit comprising: a comparator for comparing the compensation voltage with a predetermined reference value to determine a magnitude relationship; and an up-counter which counts up or down in response to a comparison output of the comparator. The phase locked loop according to claim 2, further comprising: a down counter.