JP2001102922A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To automatically correct a PLL unbalance current so as to always obtain optimum characteristics irrelevantly of the value of a PLL unbalance current quantity. SOLUTION: The difference between a Pch charge pump drive signal width and an Nch charge pump drive signal width outputted by a phase comparator 4 is detected to perform feedback control, thereby controlling an EFM-PCK phase difference to an optimum position.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a PLL circuit in a disk device such as a CD-ROM.

[0002]

2. Description of the Related Art FIG. 11 shows a conventional PLL circuit used in a disk drive. FIG. 1 is formed on a single integrated circuit chip. This PLL circuit, which controls the transmission frequency of a signal supplied to a disk reproduction system, compares a phase difference between a disk reproduction signal and the oscillation clock with a voltage controlled oscillator 1 that generates an oscillation clock according to an input voltage. A phase comparator 4 for outputting a phase comparison signal, a constant current source 7 driven by the phase comparison signal, and a current output from the constant current source converted into a voltage value to be used as an input voltage of the voltage controlled oscillator. A control loop is constituted by the filter circuit 9 to be supplied.

[0003] The system used by the user is properly PL
The integrated circuit chip includes two correction circuits A and B, which will be described later, so that the L lock is applied. The user can select one of the correction circuits and use the correction circuit. The correction circuit A includes an offset addition circuit 5, a counter 6, a PWM circuit 10 that outputs a PWM signal corresponding to the value of the counter 6, and an adjustment circuit 11 that adjusts the input voltage of the voltage-controlled oscillator 1 based on the PWM signal. ing. The correction circuit B includes a current correction circuit 12 and a switch 13.

First, a case where the correction circuit B is used will be described. Here, a description will be given using a charge pump as the constant current source 7. The EFM signal 2 and the PCK signal 3 are input to the phase comparator 4 and compare the phases of the two signals. The phase comparator 4 outputs a signal for driving the Pch charge pump in the constant current source 7 and a signal for driving the Nch charge pump.
Are output, and if the Pch drive signal is L, Pc
The h charge pump is driven, and if the Nch drive signal is H, the Nch charge pump is driven. When the phase comparison is not being performed, the Pch drive signal becomes H and the Nch drive signal becomes L, and the drive of the charge pump is stopped.

A constant current source 7 driven by a phase comparison signal
Is converted into a voltage using the filter circuit 9 and the voltage is input to the voltage-controlled oscillator 1 so that E
The PCK signal 3 synchronized with the FM signal 2 is generated. The difference between the Pch charge pump current and the Nch charge pump current in the constant current source 7 is called an unbalanced current,
As the amount of unbalance current increases, the pull-in characteristics of the PLL deteriorate.

In order to correct the unbalance current, a correction circuit B is provided to set a correction amount from the outside and turn on the switch 13 according to the set value to perform the correction. A case will be described in which the compensation circuit A is selected so that the unbalance current is automatically compensated without setting the compensation amount externally as in the compensation circuit B.

[0007] The offset adding circuit 5 has an EFM-PCK
To fine-tune the optimal position of the phase difference, set the value to P
It is added to the ch charge pump drive signal and the Nch charge pump drive signal as an offset width, and outputs the charge pump drive signal to which the offset width is added to the counter 6. When the offset width is not added, the phase comparator 4
The same signal as the charge pump driving signal output from the counter is input to the counter 6. The counter 6 detects the difference between the width of the Pch charge pump drive signal and the width of the Nch charge pump drive signal, and counts up the width when both the Pch charge pump drive signal and the Nch charge pump drive signal are at L level. The pump drive signal counts down the width of H at 1/2 clock of the up count. The value of the counter 6 is input to the PWM circuit 10, converted to current by the adjustment circuit 11, converted to voltage using the filter circuit 9, input to the voltage-controlled oscillator 1,
The FM-PCK phase difference is controlled to an optimum position.

[0008]

The amount of unbalanced current of the PLL charge pump varies between low-speed reproduction and high-speed reproduction. In the conventional configuration, the imbalance current amount must be within a certain range. It cannot be corrected. The unbalance correction circuit is a circuit on the assumption that the PLL is normally locked. Therefore, particularly at the time of high-speed playback, the PLL pull-in characteristics are deteriorated, and problems such as a deterioration in an error rate and an access problem occur.

The present invention solves the above problems,
It is an object of the present invention to provide a PLL circuit that can always obtain optimum characteristics irrespective of the reproduction speed.

[0010]

The PLL circuit of the present invention comprises:
It is characterized in that the PLL unbalance current is corrected by changing the correction resolution in accordance with the reproduction speed to improve the correction accuracy. A PLL circuit according to the present invention includes a voltage controlled oscillator that generates an oscillation clock according to an input voltage; a phase comparator that compares a phase difference between a disk reproduction signal and the oscillation clock to output a phase comparison signal; A control loop is formed by a constant current source driven by a phase comparison signal, and a filter circuit that converts a current output from the constant current source into a voltage value and supplies the voltage value as an input voltage of the voltage controlled oscillator, thereby reproducing a disk. A PLL circuit for controlling a transmission frequency of a signal to be supplied to a system, wherein a correction resolution of the control loop is switched according to a disk reproduction speed of the disk reproduction system.

Further, the PLL circuit of the present invention comprises a voltage-controlled oscillator for generating an oscillation clock according to an input voltage, and a phase for outputting a phase comparison signal by comparing a phase difference between a disk reproduction signal and the oscillation clock. A control loop includes a comparator, a constant current source driven by the phase comparison signal, and a filter circuit that converts a current output from the constant current source into a voltage value and supplies the voltage value as an input voltage of the voltage controlled oscillator. A PLL circuit configured to control a transmission frequency of a signal supplied to a disk reproducing system, comprising: a counter for measuring a signal width of the phase comparison signal; and an input of the voltage-controlled oscillator according to a measured value of the counter. A correction circuit for correcting a voltage, wherein a correction resolution of the control loop is switched according to a disk playback speed of the disk playback system. To.

In the above, the correction output from the correction circuit is connected to the input of the voltage controlled oscillator via a resistor, and the correction resolution is switched by switching the resistance value of the resistor according to the disk reproduction speed. I do.
Further, the PLL circuit of the present invention includes a voltage controlled oscillator that generates an oscillation clock according to an input voltage, and a phase comparator that compares a phase difference between a disk reproduction signal and the oscillation clock and outputs a phase comparison signal. Forming a control loop with a constant current source driven by the phase comparison signal, and a filter circuit that converts a current output from the constant current source into a voltage value and supplies the voltage value as an input voltage of the voltage controlled oscillator. PL for controlling the transmission frequency of a signal to be supplied to a disk reproduction system
An L circuit, wherein the constant current source is constituted by a + side and a − side constant current source driven by the phase comparison signal, and the output current value of one of the + side or the − side constant current source is stored in a disk. It is characterized in that the correction resolution of the control loop is switched in accordance with the reproduction speed.

In the above, the correction resolution of the control loop is switched to a higher resolution as the disk reproduction speed increases. In the above, it is characterized in that the switching of the correction resolution is stopped when the disk is abnormally reproduced. In the above, it is characterized in that the measurement by the counter is stopped when the disk reproduction is abnormal.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a PLL circuit according to the present invention will be described with reference to FIG.
Description will be made based on each embodiment shown in FIGS. (Embodiment 1) FIGS. 1 to 7 show a PL of (Embodiment 1).
3 shows an L circuit.

The components having the same functions as those of the prior art shown in FIG. 11 are denoted by the same reference numerals. In this (Embodiment 1), a switch 15 and an adjustment circuit 11 are interposed between a PWM circuit 10 and an input of a voltage controlled oscillator 1 in a compensation circuit A of FIG. Numeral 15 is configured to automatically switch the output by a reproduction speed detection circuit 14 for detecting a reproduction speed in a disk device such as a CD-ROM.

In some cases, the compensation circuit B shown in FIG. 11 is provided in the same semiconductor chip. Switching of the switch 15 is performed as follows. EFM signal 2 and PC
The K signal 3 is input to the phase comparator 4 and compares the phases of the two signals. From the phase comparator 4, the Pch shown in FIG.
A charge pump drive signal and an Nch charge pump drive signal are output. The Pch charge pump drive signal is E
This signal is L during the period from the detection of the edge of the FM signal 2 to the second rising of the PCK signal 3, and the Nch charge pump drive signal is the signal of the PCK signal 3 after detecting the edge of the EFM signal 2. It is a signal that is always in a section H of 1 PCK from the rise to the rise of the next PCK signal 3. Also, regarding the charge pump current amount, Nc
The h charge pump current is set to 1.5 times the Pch charge pump current.

Therefore, when there is no imbalance current as shown in FIG. 2, the charge pump drive signal width is Pc
h: Nch = 1.5PCK: 1PCK, that is, in a state where the phase of the EFM signal 2 and the phase of the PCK signal 3 are in phase, the area A = the area B, and the current amount is balanced.
The PLL locks. Next, the Pch charge pump drive signal and the Nch charge pump drive signal output from the phase comparator 4 are input to the offset addition circuit 5 and the constant current source 7. The offset adding circuit 5 adds the set value to the PFM to finely adjust the optimal position of the EFM-PCK phase difference.
It is added to the ch charge pump drive signal and the Nch charge pump drive signal as an offset width, and outputs the charge pump drive signal to which the offset width is added to the counter 6. When the offset width is not added, the phase comparator 4
The same signal as the charge pump driving signal output from the counter is input to the counter 6.

The counter 6 detects the difference between the Pch charge pump drive signal width and the Nch charge pump drive signal width, and counts up the width when both the Pch charge pump drive signal and the Nch charge pump drive signal are L. , The Nch charge pump drive signal counts down the width of H by ク ロ ッ ク clock when counting up. FIG.
When the Pch charge pump current: Nch charge pump current = 1: 1.5, that is, when there is no imbalance current, when both the Pch charge pump drive signal and the Nch charge pump drive signal are L And the width of the Nch charge pump drive signal is H:
Since it is 2, the value of the counter 6 becomes 0. FIG.
When the Pch charge pump current is larger than the desired value as shown in the following equation, assuming that the unbalance current is b, Pch charge pump current: Nch charge pump current = 1 + b:
1.5, and the area A =
The area becomes B and the PLL is locked. Assuming that the phase shift width at this time is a, the charge pump drive signal width is Pch:
Nch = 1.5PCK-a: 1PCK, and the counter 6 takes a negative value. Conversely, as shown in FIG. 4, when the Pch charge pump current is smaller than the desired value and Pch charge pump current: Nch charge pump current = 1-b: 1.5, the phase of PCK3 is delayed. , The area A = the area B, and the PLL is locked. At this time, the charge pump drive signal width is Pch: Nch = 1.5PCK
+ A: 1PCK, and the counter 6 takes a positive value. Then, the value of the counter 6 is input to the PWM circuit 10, and
Is output. P when next locked
It is connected to a resistor of an adjustment circuit 11 having several kinds of resolutions via a switch which is switched according to the reproduction speed by a reproduction speed detection circuit 14 for detecting the speed by counting the LL extraction clock or monitoring the rotation speed of the motor. Thus, the adjustment circuit 11 having a resolution corresponding to the reproduction speed
, The PWM signal is converted into a current, converted into a voltage using the filter circuit 9, and input to the voltage-controlled oscillator 1. As a result, the resolution is automatically changed to a1 <a2 <a3 as the playback speed increases, as shown in FIG. 10, so that the correction resolution of the control loop is switched to a higher resolution as the disk playback speed increases.

When the value of the counter 6 is 0, a waveform having the same H and L periods is output as shown in FIG. When the value of the counter 6 is negative, a waveform having a short H period is output as shown in FIG. 6 and discharged from the filter circuit 9 toward the PWM circuit 10, so that the input voltage of the voltage controlled oscillator 1 decreases. , PCK3, and delay the phase of EFM as shown in FIG.
-Control the PCK phase difference to the optimal position. When the value of the counter 6 is positive, a waveform having a long H period is output as shown in FIG. 7 and the PWM circuit 10 charges the filter circuit 9, so that the input voltage of the voltage controlled oscillator 1 rises and PCK
3 is advanced, and the EFM-PCK phase difference is controlled to the optimum position as shown in FIG.

As described above, in the first embodiment, optimum characteristics can always be obtained irrespective of the reproduction speed. (Embodiment 2) FIG. 8 shows a PLL circuit according to (Embodiment 2). It is to be noted that components having the same functions as those in FIG.

In this (Embodiment 2), the constant current source 7 in the compensating circuit B shown in FIG. 11 showing a conventional example is constituted by a plurality of positive P-channel charge pumps and a plurality of negative N-channel charge pumps. The charge pump to be used is automatically switched between the gate circuit 18 and a disk device such as a CD-ROM by the output of the reproduction speed detection circuit 14 for detecting the reproduction speed.

Note that the compensation circuit A shown in FIG. 11 may be provided in the same semiconductor chip. The above automatic switching is performed as follows. The constant current source 7 includes a basic charge pump and a charge pump for current correction. The phase comparison and the operation of the basic charge pump are the same as those in the first embodiment, except that the reproduction speed detection circuit 14 controls the current correction charge pump.

The constant current source 7 has a reference 1 on the Pch side.
It is composed of a 00% charge pump and 1% and 2% charge pumps for current correction. A current correction of 1 to 3% is possible by a combination of the charge pumps. %, And 1%, 2%, 4%, 8%, 16%, and 32% charge pumps for current correction.
A current correction of 64% is possible.

In both cases, the reference charge pump is controlled only by the phase comparison signal. If the Pch drive signal is L, the Pch charge pump is driven. If the Nch drive signal is H, the Nch charge pump is driven. I do. When the phase comparison is not being performed, the Pch drive signal becomes H and the Nch drive signal becomes L, and the drive of the charge pump is stopped. Other charge pumps for current correction are charge pumps that are turned on and off by the regeneration speed detection circuit 14.

As described above, the constant current source 7 depends on the reproduction speed.
The PCK signal 3 is generated by converting this current into a voltage by the filter circuit 9 and using the current as an input voltage of the voltage-controlled oscillator 1. As a result, the resolution is changed to a1 <a2 <a as the reproduction speed increases, as shown in FIG. 10, so that the correction resolution of the control loop is switched to a higher resolution as the disk reproduction speed increases.
Automatically change to 3.

Thus, in the second embodiment, optimum characteristics can always be obtained irrespective of the reproduction speed. (Embodiment 3) FIG. 9 shows (Embodiment 3). 16
Is a PLL abnormality detection circuit, and 17 is an unbalance correction output switching circuit.

When a dropout occurs, when the PLL comes off, when the access is made, or when the PLL unbalance correction is not used,
The imbalance correction output is held at the Hi-impedance or the immediately preceding value, and control is performed so as not to hinder the PLL pull-in. By adding the circuit of (Embodiment 3) to (Embodiment 1) or (Embodiment 2), more stable operation can be expected.

When the semiconductor chip of the first embodiment has the compensation circuit B, the compensation circuit B of the second embodiment can be used as the compensation circuit. (Embodiment 3) can also be applied to compensation circuits A and B.

[0029]

As described above, in the PLL circuit of the present invention,
By automatically correcting the PLL charge pump unbalance current, which is not necessarily the same, according to the regeneration speed, it is not necessary to externally set a correction current value.
Since the FM-PCK phase difference can be controlled to an optimum position, problems such as deterioration of an error rate and an access defect can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a PLL circuit according to (first embodiment) of the present invention;

FIG. 2 is a diagram showing a charge pump drive signal when an EFM-PCK phase difference is at an optimum position.

FIG. 3 is a diagram showing a charge pump drive signal when an EFM-PCK phase difference is advanced.

FIG. 4 is a diagram showing a charge pump drive signal when the EFM-PCK phase difference is delayed.

FIG. 5 is a diagram illustrating an output signal of a PWM circuit when a value of a UD counter is 0.

FIG. 6 is a diagram showing an output signal of the PWM circuit when the value of the UD counter is negative.

FIG. 7 is a diagram showing an output signal of the PWM circuit when the value of the UD counter is positive;

FIG. 8 is a diagram showing a PLL circuit according to (second embodiment) of the present invention;

FIG. 9 is a circuit for controlling an unbalance correction output according to the third embodiment of the present invention.

FIG. 10 is a diagram illustrating a relationship between a reproduction speed and a change in resolution of a control loop in each embodiment.

FIG. 11 is a diagram showing a conventional PLL circuit.

[Explanation of symbols]

 A Compensation Circuit B Compensation Circuit 1 Voltage Controlled Oscillator 2 EFM Signal 3 PCK Signal 4 Phase Comparator 5 Offset Addition Circuit 6 Counter 7 Constant Current Source 8 Current Value Control Circuit 9 Filter Circuit 10 PWM Circuit 11 Adjustment Circuit 12 Current Correction Circuit 13 Switch 14 playback speed detection circuit 15 switch

Continued on the front page F term (reference) 5D044 BC03 CC04 GM14 GM18 5J106 AA04 BB03 CC01 CC24 CC38 CC41 DD08 DD17 DD32 EE10 GG07 HH10 KK29 KK32

Claims (7)

[Claims] A voltage-controlled oscillator for generating an oscillation clock corresponding to an input voltage; a phase comparator for comparing a phase difference between a disk reproduction signal and the oscillation clock to output a phase comparison signal; A control loop is formed by a constant current source driven by a signal, and a filter circuit that converts a current output from the constant current source into a voltage value and supplies the voltage value as an input voltage of the voltage-controlled oscillator to form a control loop for a disk reproduction system. A PLL circuit for controlling a transmission frequency of a signal to be supplied, wherein the PLL circuit is configured to switch a correction resolution of the control loop according to a disk playback speed of the disk playback system.
L circuit. 2. A voltage-controlled oscillator for generating an oscillation clock according to an input voltage, a phase comparator for comparing a phase difference between a disk reproduction signal and the oscillation clock and outputting a phase comparison signal, A control loop is formed by a constant current source driven by a signal, and a filter circuit that converts a current output from the constant current source into a voltage value and supplies the voltage value as an input voltage of the voltage-controlled oscillator to form a control loop for a disk reproduction system. A PLL circuit for controlling a transmission frequency of a supplied signal, comprising: a counter for measuring a signal width of the phase comparison signal; and a correction circuit for correcting an input voltage of the voltage controlled oscillator according to a measured value of the counter. A PLL circuit configured to switch the correction resolution of the control loop according to the disk playback speed of the disk playback system. 3. The correction output according to claim 2, wherein a correction output from the correction circuit is connected to an input of the voltage controlled oscillator via a resistor, and the correction resolution is switched by switching a resistance value of the resistor according to a disk reproducing speed. PLL circuit. 4. A voltage-controlled oscillator for generating an oscillation clock according to an input voltage, a phase comparator for comparing a phase difference between a disk reproduction signal and the oscillation clock and outputting a phase comparison signal, A control loop is formed by a constant current source driven by a signal, and a filter circuit that converts a current output from the constant current source into a voltage value and supplies the voltage value as an input voltage of the voltage-controlled oscillator to form a control loop for a disk reproduction system. A PLL circuit for controlling an oscillation frequency of a signal to be supplied, wherein the constant current source is driven by the phase comparison signal.
A PLL configured by a constant current source on the positive side and a negative current source on the negative side, wherein the output current value of one of the constant current sources on the positive side and the negative side is adjusted in accordance with a disk reproducing speed to switch the correction resolution of the control loop. circuit. 5. The PLL circuit according to claim 1, wherein the correction resolution of said control loop is switched to a higher resolution as the disk reproduction speed increases. 6. The PLL circuit according to claim 1, wherein the switching of the correction resolution is stopped when a disk reproduction is abnormal. 7. The PLL circuit according to claim 2, wherein the measurement by said counter is stopped when a disk reproduction is abnormal.