JP2000183703A - Comparator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a comparator where current consumption by a through- current is reduced without increasing the number of components. SOLUTION: In the comparator provided with a comparison capacitor C whose one terminal is connected in series with a plurality of inverters I1, I2 and the other terminal receives an input voltage VIN and a reference voltage VREF via exclusively operated 1st and 2nd switches S1, S2, each of the aforementioned inverters are composed of an even number of inverters, and an output of the comparator is positively fed back to the output of the comparison capacitor C via a 3rd switch S3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chopper type comparator used in an analog / digital converter or the like.

[0002]

2. Description of the Related Art A chopper type comparator 3 will be described as a conventional example 1 of a chopper type comparator, and its configuration will be described below with reference to FIG. Chopper type comparator 3
Is composed of inverters I ₁ and I ₂ , a comparison capacitor C, and MOS switches S ₁₁ , S ₁₂ and S ₂ .
Next, the operation of the chopper type comparator 3 will be described.

An input voltage V _IN and a reference voltage V _REF are input from input terminals, and a rectangular wave as shown in a time chart of FIG. 9 is input to a control terminal of a switch as a clock. The switch closes when the clock is high and opens when it is low. Next, the operation of the comparator 3 in the sections 93 and 94 in FIG. 9 will be described.

[0004] In section 93, MOS switches S ₁₁ reference voltages the left side in the drawing of closed comparative capacitor C V
_{While REF} is applied, MOS switch S ₁₂ is a bias voltage V _I1 caused by shorting both ends of the inverter I ₁ is applied to the right side in the figure in the comparison capacitor C is closed. For this reason, the node b is set (V _I1
−V _REF ).

Next, in the section 94, the MOS switches S ₁₁ ,
By be closed MOS switch S ₂ S ₁₂ is opened,
The potential V _IN is applied to the node a and the node b becomes (V _I1 +
(V _IN −V _REF )). Thus, the inverters I ₁ and I ₂ perform the comparison operation. The chopper comparator 3 repeats the operation in the sections 93 and 94.

In such a chopper type comparator 3, the difference between the input voltage and the reference voltage (V _IN -V _REF )
When the potential difference is small, the gain is insufficient and the amplitude does not become sufficiently large. That is, the gains required to determine the logic by the inverters I ₁ and I ₂ cannot be obtained. Further, at this time, a through current is generated in the inverters I ₁ and I ₂ , and there is a problem that current consumption of the chopper type comparator 3 increases. If the number of inverters connected in series is increased, the necessary gain can be secured even when the potential difference (V _IN −V _REF ) is small, but the number of elements constituting the chopper type comparator increases.

Another conventional example is disclosed in JP-A-63-806.
There is a chopper comparator (prior art 2) described in Japanese Patent No. In the conventional example 2, the output of one or more inverters connected in series is taken out through a latch circuit composed of two inverters, and a switch is provided at the input of the latch circuit. By turning off the circuit during standby, power consumption is reduced.

However, the conventional example 2 has a problem that the number of elements increases because two inverters are used as the latch circuit.

[0009]

As described above, in the conventional comparator, there is a problem that the number of elements increases in order to reduce the current consumption caused by the through current.

In view of such a situation, an object to be solved by the present invention is to provide a comparator in which current consumption due to a through current is reduced without increasing the number of elements.

[0011]

In order to solve such a problem, the present invention provides the following comparator.

According to the present invention, there is provided a comparator comprising a comparison capacitor for connecting an input voltage and a reference voltage to the other end via first and second switches which open and close exclusively, while connecting a plurality of inverters in series to one end. Wherein the plurality of inverters comprises an even number of inverters, and the output of the comparator is positively fed back to the output of the comparison capacitor via a third switch.

In this comparator, the third switch is closed after inputting the input voltage, and is opened simultaneously with inputting the reference voltage.

As an example of the configuration of such a comparator,
The plurality of inverters comprises a first inverter connected to the output of the comparison capacitor and a second inverter connected to the output of the first inverter, wherein the output of the first inverter is connected to a second switch. A comparator is provided that is connected to the input of the first inverter via a fourth switch that opens and closes synchronously.

As another configuration example, a fifth switch for connecting the output of the first inverter to the input of the second inverter, and a fifth switch for connecting the input of the second inverter to a power supply of a predetermined voltage. 6 switches, wherein the fifth and sixth switches provide comparators that are opened and closed exclusively to each other.

As means for exclusively opening and closing the fifth and sixth switches, one of the switches may be an NMOS (N-channel switch).
There is a means of using an etal oxide semiconductor (PET) transistor and the other being a PMOS (P-channel metal oxide semiconductor).

In these configuration examples, it is easy to provide a complementary signal output terminal for outputting the output of the first inverter as a complementary signal of the comparator.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION First Embodiment A chopper type comparator 1 according to a first embodiment of the present invention will be described with reference to FIG.

The chopper type comparator 1 includes inverters I ₁ and I ₂ , a comparison capacitor C, and a MOS switch S
₁₁ , S ₁₂ , S ₂ , and S ₃ . As input,
The input voltage V _IN and the reference voltage V _REF are input to the first and second input terminals, and clocks 21 to 23 as shown in the timing chart of FIG. 2 are input to the MOS switch. The clocks 21 and 22 are clock signals having phases opposite to each other. The clock 23 is a clock signal having substantially the same phase as the clock 22, but having a delay in rising.
On the other hand, the output of the chopper type comparator 1, and outputs the output of the inverter I ₂ from the OUT terminal,
Outputs the output of the inverter I ₁ as a complementary signal to the OUT terminal.

Next, the comparison operation of the chopper type comparator 1 will be described. As can be seen from FIG. 2, a clock high state is indicated by 1 and a low state is indicated by 0 (clock 21, clock 21).
When expressed as clocks 22 and 23), the states of clocks 21 to 23 are (1, 0, 0) in section 24,
(0,1,0) in section 25 and (0,1,1) in section 26
It becomes three kinds of repetitions.

In the section 24, the reference voltage V _REF is applied to the node a, while the bias voltage V _REF which is a voltage obtained by short-circuiting the input and output of the inverter I ₁ is applied to the node b.
_{By I1} is applied, the potential difference between the reference voltage V _REF and the bias voltage V _I1 is charged in the comparative capacitor C.

[0022] In section 25, MOS switch S ₁₁ and S ₁₂
When the MOS switch S ₂ is closed is opened, the node potential of V _IN is applied a node b to _{a (V I1 + (V IN} -
V _REF )). Where inverters I ₁ and I
₂ starts the comparison operation.

The potential of the node a changes to the input voltage V _IN , and the short circuit between the input and output of the inverter I ₁ is released. As a result, the potential of the node a changes by (V _IN -V _REF ), and accordingly, the potential of the node b also changes from VI ₁ to (V
_IN -V _REF) only changes, the output of the inverter I ₁ is trying to be one of the high or low.

Here, when (V _IN -V _REF ) is sufficiently large, the result of the comparison is determined. However, when it is small, the logic is not determined due to insufficient gain. That is, section 25
Can be said to be a section for performing a rough comparison.

[0025] In section 26, the MOS switch S ₃ is closed, the output of the inverter I ₂ is determined a positive feedback has been rapidly logic to the input of the inverter I _1. By the output of the inverter I ₂ positive feedback is applied to the input of the inverter I _1, the theory is confirmed by covering the insufficient gain. Thereby, the through current of the inverters I ₁ and I ₂ can be reduced, and the current consumption can be reduced.

The power consumption during the operation of the chopper type comparators 1 and 3 is compared with reference to FIGS.
The average current consumption of the conventional chopper type comparator 3 is 14
The result of simulating the average current consumption of the chopper type comparator 1 of the present invention is 88.39 μA, compared to 0.35 μA, which indicates that the average power consumption can be reduced to about ／ compared with the conventional case. .

2. Second Embodiment Next, a configuration of a chopper type comparator 2 according to a second embodiment of the present invention will be described with reference to FIG. The difference between the chopper type comparator 2 and the chopper type comparator 1 already described is that the inverters I ₁ and I ₂
And that it includes a MOS switch S ₄₁ between the inverter I
₂ in that a PMOS switch _S42 is provided between the input ₂ and the power supply.

The chopper type comparator 2 operates as follows.

The outline of the operation is the same as that of the chopper type comparator 1 described above. That is, due to the potential difference between the input voltage V _IN and the reference voltage V _REF , the inverters I ₁ and I ₂
There start comparison operation, and finally the output of the inverter I ₂ in the closed MOS switch S ₃ to confirm the positive feedback is rapidly logic to the input of the inverter I _1.

Next, the comparison operation of the chopper type comparator 2 will be described with reference to FIG. Chopper type comparator 1
(Clock 61, clock 6)
2, clock 63, clock 64), the states of these clocks are (1, 0, 0, 0) in section 65, (1, 0, 0, 1) in section 66, and (0, 0) in section 67. , 1,
(0, 1) and four states (0, 1, 1, 1) in the section 68 are repeated.

In the section 65, the reference voltage V _REF is applied to the node a, the voltage V _I1 in which the input and output of the inverter I ₁ is short-circuited is applied to the node b, and the voltage V _I1 is applied to the comparison capacitor C.
The potential difference between _REF and _VI1 is charged. In this section,
Since the clock 64 is low, while the MOS switch S ₄₁ is open, PMOS switch S ₄₂ is closed. Therefore, the inverter I ₂ output is tied low, the through current of the inverter I ₂ in this period is reduced.

In the section 66, the potential difference between the reference voltage V _REF and the bias voltage V _I1 is charged to the comparison capacitor C. Here, the clock 64 goes high and the section 6
Contrary to 5, MOS switch _S41 is closed and PMOS switch _S42 is opened. While in this interval even through current flows in the inverter I _2, which is up to output short voltage V _I1 of the inverter I ₂ settles a relatively short period of time.

In the section 67, the potential of the node a is the input voltage
V_INAnd inverter I₁ I / O short
Is released. As a result, the potential of the node a becomes (V_IN−
V_REF) And the potential at node b is also V_I1Than
(V_IN-V_REF) Only change. And inverter I₁
Tries to be either high or low. this
Hour, (V_IN-V_REF) Is large enough for comparison
The result is determined, but if it is small, the gain is insufficient and the logic is confirmed.
Not determined. That is, this section performs a rough comparison.

[0034] In section 68, the logic is determined covers a gain shortage by positive feedback is applied from the output of the inverter I ₂ to the inverter I _1. Thereby, the inverter I
Through currents of ₁ and I ₂ can be reduced.

That is, while the MOS switches S ₁₁ and S ₁₂ are closed, a through current flows through both the inverters I ₁ and I ₂ , but the MOS switch S ₄₁ opens and the PMOS switch S 12 opens.
By fixing the input of the inverter I _{2 by 42} is closed, thereby reducing the through current of the inverter I _2.

[0036] Thus, according to the chopper type comparator 2, by suppressing the through current of the inverter I _2, it is possible to further reduce the current consumption than chopper comparator 1 described previously.

As shown in FIG. 7, the chopper type comparator 2
Consumes 79.65 μA when the device is operated, which is about 3/5 of that of the conventional chopper type comparator 1 and about 9/10 of that of the chopper type comparator 1 of the present invention. The current can be reduced.

[0038]

According to the present invention, in the chopper type comparator, the through current of the inverter can be reduced without increasing the number of elements.

Although the present invention has been described based on the embodiment, the present invention is not limited to this, and it is understood that changes and improvements can be made within the ordinary knowledge of those skilled in the art. Of course.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a chopper type comparator 1 according to a first embodiment of the present invention.

FIG. 2 is a timing chart of a clock input to the chopper type comparator 1;

FIG. 3 is a diagram illustrating a result of an operation simulation of the chopper type comparator 1;

FIG. 4 is a diagram illustrating a result of an operation simulation of a conventional chopper type comparator 3.

FIG. 5 is a functional block diagram of a chopper type comparator 2 according to a second embodiment of the present invention.

FIG. 6 is a timing chart of a clock input to the chopper type comparator 2;

7 is a diagram illustrating a result of an operation simulation of the chopper type comparator 2. FIG.

FIG. 8 is a functional block diagram of a conventional chopper type comparator 3.

FIG. 9 is a timing chart of a clock input to the chopper type comparator 3.

Claims (6)

[Claims] 1. A comparator comprising: a plurality of inverters connected in series at one end; and a comparison capacitor connected to an input terminal and a reference voltage at the other end via first and second switches that open and close exclusively. The comparator, wherein the plurality of inverters comprises an even number of inverters, and an output of the comparator is positively fed back to an output of the comparison capacitor via a third switch. 2. The comparator according to claim 1, wherein
The comparator, wherein the third switch is closed after the input voltage is input, and is opened simultaneously with the input of the reference voltage. 3. The comparator according to claim 1, wherein the plurality of inverters are connected to a first inverter connected to an output of the comparison capacitor, and to an output of the first inverter. And an output of the first inverter is connected to an input of the first inverter via a fourth switch that opens and closes in synchronization with the second switch. Comparator. 4. The comparator according to claim 3, wherein a fifth switch connecting an output of the first inverter and an input of the second inverter, and a predetermined voltage applied to an input of the second inverter. And a sixth switch connected to the power supply of the first and second switches, wherein the fifth and sixth switches are opened and closed exclusively from each other. 5. The comparator according to claim 4, wherein
One of the fifth and sixth switches is an NMO
An S (N-channel metal oxide semiconductor) transistor, and the other is a PMOS (P-channel metal oxide sem).
a comparator characterized by being an iconductor). 6. The comparator according to claim 3, further comprising a complementary signal output terminal for outputting an output of said first inverter as a complementary signal of said comparator.