KR20010048965A - Operational amplifier having function of cancelling offset voltage - Google Patents

Abstract

PURPOSE: An operational amplifier having an offset voltage removal function is provided which applies a potential having a polarity opposite to the polarity of an offset voltage generated at the output port of an operational amplifier to the offset voltage to compensate the offset. CONSTITUTION: An operational amplifier having an offset voltage removal function includes a differential amplifier(10), an input switch(16), a comparator(!4), and an offset controller(12). the differential amplifier amplifies the difference between the voltage applied through the positive input port and the voltage applied through the negative input port, outputs the amplified results through the positive output port and the negative output port, respectively, and includes an inner current switch to control an output voltage in response to the predetermined first and second control signals represented by n(>1) bits. The input switch connects external positive/negative input ports to the positive/negative input ports of the differential amplifier in response to a predetermined switch control signal in a normal operation mode and connects the positive input port and the negative input port of the differential amplifier with each other in an offset removal operation mode. The comparator compares the voltage output from the positive output port of the differential amplifier with the voltage output from the negative output port of the amplifier to generate a signal corresponding to the compared result. The offset controller generates the first and the second control switch signals in response to the signal output from the comparator, and resets signal and clock signal applied from the outside.

Description

Operational amplifier having function of canceling offset voltage}

The present invention relates to an operational amplifier, and more particularly, to an operational amplifier having an offset voltage cancellation function.

In general, an op amp may exhibit an offset voltage at an output terminal, and the offset voltage may be generated for various reasons. As an example, the offset may be generated by the position of the layout, and may also be generated by the deviation of the power supply voltage applied to the operational amplifier. For example, it is assumed that a transistor designed to have a width WIDTH of 50 μm at an input terminal of an operational amplifier due to a process error is assumed to be 49.999 μm. In this case, a DC offset voltage of several tens of mV may be generated at the output terminal of the amplifier. If the size of the transistor is designed to be 49.995 um, the offset can be increased to several hundred mV.

As described above, the offset voltage generated at the output terminal of the operational amplifier may be a disturbing factor in obtaining a normal output when the magnitude of the offset voltage is large. Therefore, the offset voltage must be removed to obtain a normal amplification output.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an operational amplifier having an offset voltage removing function capable of compensating an offset generated at an output terminal by applying an opposite potential to an offset generated at an output terminal of an operational amplifier. .

1 is a block diagram illustrating an operational amplifier having an offset voltage cancellation function according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a differential amplifier of the circuit shown in FIG. 1.

3 is a circuit diagram illustrating an offset control unit of the circuit illustrated in FIG. 1.

4 (a) to 4 (n) are waveform diagrams for explaining the operation of the offset control unit shown in FIG.

FIG. 5 is a flowchart for describing an offset voltage removing process performed in the circuit shown in FIG. 1.

FIG. 6 is a diagram illustrating a result of removing offset voltage in the circuit of FIG. 1.

In order to achieve the above object, the operational amplifier having an offset voltage cancellation function according to the present invention, differentially amplifies the voltage applied through the positive input terminal and the voltage applied through the negative input terminal, and outputs the amplified result to each of the positive output terminal And a differential amplifier for outputting through a negative output terminal and adjusting an output voltage in response to a predetermined first control signal and a second control signal represented by n (> 1) bits with a current switch inside. In this mode, the external positive / negative input terminal and the positive / negative input terminal of the differential amplifier are connected to each other in response to a predetermined switch control signal, and the positive and negative input terminals of the differential amplifier are connected to each other in the offset elimination mode. Input switch unit for switching, voltage output from the positive output terminal of the differential amplifier, voltage output from the negative output terminal of the differential amplifier Comparing and comparing the output signal from the comparator and the comparator to generate a comparison output signal corresponding to the comparison result, and the switch control signal and the first and second control signals in response to the externally applied reset signal and the clock signal It is preferable that it is comprised by the offset control part which produces | generates.

Hereinafter, an operational amplifier having an offset voltage cancellation function according to the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating an operational amplifier having an offset voltage cancellation function according to an exemplary embodiment of the present invention, and includes a differential amplifier 10, an offset controller 12, a comparator 14, and an input switch unit 16. It includes.

The differential amplifier 10 differentially amplifies the voltage applied through the positive input terminal VIP and the negative input terminal VIN, and outputs the amplified result through the positive output terminal VOP and the negative output terminal VON, respectively. In addition, the differential amplifier 10 includes current switches therein, and in response to the first control signal swp and the second control signal swn output from the offset controller 12, the negative output terminal VOP may be negative or negative. The output voltage is adjusted by adjusting the amount of current at the output terminal VON. Here, the first control signal swp and the second control signal swn may be implemented with n (> 1) bits, respectively.

The input switch unit 16 includes switches SW11 and SW12 respectively connected between the positive input terminal INP and the negative input terminal INN connected to the outside, and the positive input terminal VIP and the negative input terminal VIN of the differential amplifier 10. Include. In addition, the input switch unit 16 includes a switch SW13 connected between the positive input terminal VOP and the negative input terminal VON of the differential amplifier 10. Here, the switches SW11, SW12, and SW13 are switched on / off in response to the switch control signal OST_DONE output from the offset controller 12. For example, when the differential amplifier 10 normally operates, the switch control signal OST_DONE may be set to a high level. At this time, the switches SW11 and SW12 are turned on and the switch SW13 is turned off. In addition, the switch control signal OST_DONE may be set to a low level in the offset voltage removing mode. At this time, the switches SW11 and SW12 are turned off and the switch SW13 is turned on.

The comparator 14 receives the voltage of the positive output terminal VOP and the voltage of the negative output terminal VON output from the differential amplifier 10 as the first and second inputs, respectively, compares the input voltages, and compares the corresponding output signals. Create (C_OUT).

The offset control unit 12 inputs the comparison output signal C_OUT output from the comparator 14, the reset signal resetn, and the clock signal CLK to remove the offset, and the switch control signal OST_DONE and the first, Generate the second control signal (swp, swn). At this time, the first and second control signals swp and swn are used to adjust the voltages of the output terminals VOP and VON by turning on / off the internal current switch of the differential amplifier 10.

Although FIG. 1 illustrates a circuit for removing an offset for one operational amplifier, the same applies to a circuit using a plurality of operational amplifiers using the comparator 14 and the offset controller 12 of FIG. 1. .

FIG. 2 is a detailed circuit diagram illustrating the differential amplifier 10 of the circuit illustrated in FIG. 1, and includes a bias circuit 200, an in-phase mode feedback controller 210, a first amplifier 220, and a second amplifier. 230 and the current switch unit 240.

The bias circuit 200 generates bias voltages B1 and B2 for the amplification operation in response to a bias current Ic applied from the outside. To this end, the bias circuit 200 includes NMOS transistors MN21 and MN22 and a PMOS transistor MP21.

The in-phase mode feedback control unit 210 feeds back the voltages of the positive output terminal VOP and the negative output terminal VON of the differential amplifier 10, and in response to the bias voltages B1 and B2, an intermediate value of the fed back voltage Control to be equal to the common voltage (VCOM). Here, the common voltage is set to a voltage which is halfway between the voltage of the positive output terminal VOP and the voltage of the negative output terminal VON. To this end, the in-phase mode feedback control unit 210 includes PMOS transistors MP22 and MP23, NMOS transistors MN23, MN24 and MN25, resistors R21 and R22, and capacitors C21 and C22.

The first amplifier 220 amplifies the voltage differentially input through the positive input terminal VIP and the negative input terminal VIN in response to the bias voltage B2, and amplifies the first voltage V1 and the second amplified result, respectively. It outputs as voltage V2. To this end, the first amplifier 220 includes PMOS transistors MP24, MP25, MP26, and MP27 and NMOS transistors MN26, MN27, and MN28.

The second amplifier 230 amplifies the first voltage V1 and the second voltage V2 output from the first amplifier 230 and outputs the amplified result through the positive output terminal VOP and the negative output terminal VON. Output To this end, the second amplifier 230 includes PMOS transistors MP28 and MP29 and NMOS transistors MN29 and MN30. Here, the first voltage V1 is connected to the constant output terminal VOP through the external resistor R23 and the capacitor C23, and the second voltage V2 connects the external resistor R24 and the capacitor C24. It is connected to the negative output terminal VON.

The current switch unit 240 includes a first switch unit 250 and a second switch unit 260. The first switch unit 250 is composed of current switches for adjusting the output current to adjust the voltage of the constant output terminal VOP. In addition, the second switch unit 260 is composed of current switches for adjusting the output current to adjust the voltage of the negative output terminal VON. To this end, the first switch unit 250 includes NMOS transistors MN31 to MN42, and the second switch unit 260 includes NMOS transistors MN43 to MN54. Specifically, the transistors MN31 to MN36 of the first switch unit 250 are connected to the first voltage V1 and the respective drains, and the gate of the NMOS transistors MN26 and MN27 of the first amplifier 220 is connected. It is connected to the gate. In addition, drains of the NMOS transistors MN37 to MN42 are respectively connected to the sources of the transistors MN31 to MN36, a source is connected to the ground VSS, and each gate is formed in the offset controller 12. It is connected to one control signals (swp <5> ~ swp <0>). Here, the transistors MN37 to MN42 serve as switching elements only by the input first control signal swp. In addition, the transistors MN31 ˜ MN36 are implemented with transistors of different sizes to play different currents in the switched state. Accordingly, among the first control signals swp <5> to swp <0> input to the gates of the transistors MN37 to MN42, the transistors connected to the control signal enabled to the high level are turned on, so that the first The amount of current to the first voltage node V1 and the ground VSS of the amplifier 220 is adjusted. As a result, the voltage of the output terminal VOP is adjusted by the first control signal swp.

In the second switch unit 260 of the current switch unit 240, the drains of the NMOS transistors MN43 to MN48 are connected to the second voltage V2, and the gate of the first amplifier unit 220 is connected to the second amplifier unit 260. It is connected to the gates of the NMOS transistors MN26 and MN27. In addition, the drains of the NMOS transistors MN49 to MN54 are connected to each source of the MN43 to MN48, the source is connected to the ground VSS, and the respective gates are connected to the second control signals swn <5> to swn <. 0>). Here, the transistors MN49 to MN54 serve as switching elements only by the input second control signal swn. In addition, the transistors MN43 to MN48 are implemented with transistors of different sizes to play different currents in the switched state. Accordingly, among the second control signals swn <5> to swn <0>, which are input to the gates of the NMOS transistors MN49 to MN54, the transistors connected to the high level enabled control signal are turned on, thereby The amount of current to the two voltage nodes V2 and ground VSS is adjusted. For this reason, the voltage of the output terminal VON is adjusted by the second control signal swn.

Table 1 shows transistor sizes of the current switch 240 shown in FIG. In Table 1, sw <i> denotes the current switch of the first switch unit 250 for adjusting the voltage of the positive output terminal VOP, swp, and the second switch unit 260 for adjusting the voltage of the negative output terminal VON. In the current switch of sw), swp or swn. At this time, the size of the current switch sw <i> at the same position is set to have the following channel width and length.

Switch size sw <5> sw <4> sw <3> sw <2> sw <1> sw <0> W 48 24 12 6 6 6 L 0.8 0.8 0.8 0.8 1.6 3.2

That is, in the current switch unit 240 of FIG. 2, the NMOS transistor MN31 of the first switch unit 250 and the NMOS transistor MN43 of the second switch unit 260 correspond to sw5, and W / L is 48. It is implemented with a transistor of /0.8. Similarly, the NMOS transistor MN32 of the first switch unit 250 and the NMOS transistor MN44 of the second switch unit 260 correspond to sw4 of Table 1, and each W / L has a size of 24 / 0.8. It is implemented with a transistor. The other switches of the current switch 240 are determined in a similar manner so that the width / length is reduced in size by a multiple of two for the adjacent current switch.

The operation of the current switch 240 of FIG. 2 is described as follows. First, operation is performed in the offset removing operation mode for a predetermined time after the power supply voltage is applied. That is, in the offset removing operation mode, the voltages of the positive input terminal VIP and the negative input terminal VIN are set equally by the operation of the input switch section 16 (see Fig. 1). At this time, if the output voltage of the comparator 14 is judged to be high level, it is determined that the voltage of the positive output terminal VOP is higher than the voltage of the negative output terminal VON. In addition, when the output voltage of the comparator 14 (refer FIG. 1) is low level, it is discriminated that the voltage of the negative output terminal VON is higher than the voltage of the positive output terminal VOP. If the VOP is larger than VON, the voltage of the positive output terminal VOP is adjusted to be low by adjusting the current switch of the first switch unit 250. That is, the intermediate voltage between the positive output terminal VOP and the negative output terminal VON is fed back by the in-phase mode feedback control unit 210 of FIG. Therefore, when the voltage of the positive output terminal VOP is lowered, the voltage of the negative output terminal VON is increased as the VOP is lowered. For example, when the control signal swp <5> is at a high level, the NMOS transistor MN37 of the first switch unit 250 is turned on, thereby grounding VSS from the first voltage node V1. The predetermined current corresponding to the transistor MN31 flows. Therefore, the first voltage V1 is lowered, and as a result, the voltage of the constant output terminal VOP is adjusted lower.

In addition, when VON is larger than VOP, it operates as follows. At this time, the voltage of the negative output terminal VON is adjusted low by adjusting the current switch of the second switch unit 260. For example, when the control signal swn &lt; 5 &gt; is at a high level, the NMOS transistor MN49 of the second switch unit 260 is turned on, thereby grounding VSS from the second voltage node V2. The predetermined current corresponding to the transistor MN43 flows. Therefore, the second voltage V2 is lowered, and as a result, the voltage of the negative output terminal VON is lowered. Generation of the first and second control signals swp and swn and a switch driving sequence are described in detail with reference to FIGS. 3 to 5.

3 is a detailed circuit diagram illustrating the offset control unit 12 of the circuit illustrated in FIG. 1, and includes a first comparator 300, a first control signal generator 310, and a second control signal generator 320. The switch driving unit 330 includes a first switch control unit 340, a second switch control unit 350, and a switch control signal output unit 360.

The first comparator 300 inputs the comparison output signal C_OUT output from the comparator 14 and the comparison clock signal COMPCLK output from the switch driver 330, and compares the output signal C_OUT. Generates latch input signal TI and first and second comparison signals P_COMP and N_COMP. To this end, the first comparator 300 includes a Schmitt trigger 302 having a hysteresis characteristic, a flip-flop 304, an inverter 306, and a multiplexer 308. The Schmitt trigger 302 generates an output signal at a high or low level depending on the magnitude of the input signal. That is, the Schmitt trigger 302 is used to block external noise components and to obtain an accurate output. The inverter 306 inverts the output signal C_OUTD of the Schmitt trigger 302 and applies the inverted result to the first input of the multiplexer 308. In addition, the output signal of the Schmitt trigger 302 is applied to the second input of the multiplexer 308. The flip-flop 304 is reset in response to the reset signal resetn, and generates the positive output signal Q and the negative output signal QB in response to the comparison clock signal COMPCLK generated by the switch driver 330. . At this time, the constant output signal Q becomes the first comparison signal P_COMP for adjusting the voltage of the constant output terminal VOP of the differential amplifier 10, and the sub output signal QB becomes the differential amplifier 10. Becomes a second comparison signal N_COMP for adjusting the voltage of the negative output terminal. In addition, the positive output signal Q of the flip-flop 304 is applied as the selection signal of the multiplexer 308. The multiplexer 308 applies the output signal of the inverter 306 and the output signal of the Schmitt trigger 302 to the first and second inputs, respectively, and responds to the positive output signal Q of the flip-flop 304. Outputs the first input and the second input selectively. At this time, the output signal of the multiplexer 308 becomes the latch input signal TI described above.

The switch driver 330 delays the power supply voltage VDD for a predetermined time in response to an externally applied clock signal CLK, and generates the comparison clock signal COMPCLK and the switch driving signal SW_ACT based on the delayed result. In addition, the switch driving signal SW_ACT is logically combined with the first and second comparison signals P_COMP N_COMP output from the first comparator 300 to output the positive output switch driving signal P_ACT and the negative output switch driving signal N_ACT. Is generated as). To this end, the switch driver 330 includes flip-flops 332a to 332k connected in series, and end gates 336 and 338. Specifically, the flip-flops 332a to 332k are externally clocked with a predetermined clock signal CLK, and are initialized in response to the reset signal resetn, and output the positive output signal Q of the previous flip-flop. Enter it. Here, the flip-flop 332a data inputs the power supply voltage VDD. In addition, the output signal of the flip-flop 332i becomes the comparison clock signal COMPCLK, and the output of the flip-flop 332k connected to the last stage becomes the switch driving signal SW_ACT. The AND gate 336 ANDs the first comparison signal P_COMP and the switch driving signal SW_ACT, and outputs the AND result as the constant output switch driving signal P_ACT. In addition, the AND gate 338 performs an AND operation on the switch driving signal SW_ACT and the second comparison signal N_COMP, and outputs the AND result as a negative output switch driving signal N_ACT.

The first switch controller 340 generates a set signal sn_p, a reset signal rn_p, and a latch enable signal te_p to generate a control signal for controlling each current switch for adjusting the voltage of the constant output terminal VOP. ) To this end, the first switch controller 340 includes registers 340a to 340f. The register 340a includes flip-flops 341 to 344, a NAND gate 345, and an AND gate 346 connected in series. Specifically, although not shown, the remaining registers 340b to 340f have the same structure. In more detail with respect to the register 340a, the flip-flop 341 is initialized in response to the reset signal resetn by inputting the constant output switch driving signal P_ACT output from the switch driver 330. The constant output signal Q is generated in response to the clock signal CLK. At this time, the output signal of the flip-flop 341 is applied as a reset signal rn5_p for resetting the selection flip-flop 311 of the first control signal generator 310. In addition, the flip-flop 342 is initialized in response to the reset signal resetn, and the output signal of the input flip-flop 341 in response to the clock signal CLK is the positive output signal Q and the sub-output signal QN. Output as The NAND gate 345 inverts and outputs the positive output signal Q of the flip-flop 341, that is, the reset signal rn5_p and the sub-output signal QN of the flip-flop 342, and outputs the result of the inverse AND operation. do. At this time, the output signal of the NAND gate 345 becomes a set signal sn5_p for setting the selection flip-flop 311 of the first control signal generator 310. In addition, the positive output signal Q of the flip-flop 342 is applied to the data input of the flip-flop 343. Flip-flop 343 is initialized in response to a reset signal resetn. In addition, the flip-flop 343 inputs the output signal of the flip-flop 342 and generates a positive output signal in response to the clock signal CLK. At this time, the positive output signal of the flip-flop 343 is applied to the first input of the AND gate 346. The flip-flop 344 data-inputs the output signal of the flip-flop 343 and generates a positive output signal and a sub-output signal in response to the clock signal CLK. At this time, the negative output signal QN of the flip-flop 344 is applied to the second input of the AND gate 346. The AND gate 346 performs an AND operation on the positive output signal Q of the flip-flop 343 and the negative output signal of the flip-flop 344 to be applied to the selection flip-flop 311 of the first control signal generator 310. The latch enable signal te5_p is generated. As described above, the register 340a of the first switch controller 340 sets and resets the selected flip-flop 311 of the first control signal generator 310 and controls the signal signals sn5_p, which latch the input data. rn5_p and te5_p) are generated.

In addition, the register 340b of the first switch controller 340 is similar in configuration to the register 340a. The only difference is that the positive output signal of the flip-flop 344 is applied to the input of the first flip-flop among the terminal and four flip-flops (not shown). Similarly, the output of the fourth flip-flop (not shown) of register 340b is applied to the data input of the first flip-flop of next register 340c. Through this process, the set signals sn5_p to sn0_p and the reset signals rn5_p for controlling the selected flip-flops 311 to 316 of the first control signal generator 310 to adjust the voltage of the constant output terminal VOP. rn0_p and latch enable signals te5_p to te0_p are generated.

The second switch controller 350 generates a set signal sn_n, a reset signal rn_n, and a latch enable signal te_n to generate a control signal for controlling a current switch for adjusting the voltage of the negative output terminal VON. Create To this end, the second switch controller 350 includes registers 350a to 350f. The registers 350a to 350f also have the same structure as the registers 340a to 340f of the first switch controller 340. Referring to the register 350f, the register 350f includes flip-flops 351 to 354, a NAND gate 355, and an end gate 356. Since each operation of the registers 350a to 350f is similar to each of the registers 340a to 340f of the first switch controller 340, a detailed description thereof will be omitted. As a result, the registers 350a to 350f of the second switch control unit 350 control the set signals sn5_n to sn0_n for controlling the respective flip-flops 321 to 326 of the second control signal generator 320. And reset signals rn5_n to rn5_n and latch enable signals te5_n to te0_n.

In addition, the switch control signal output unit 360 is implemented as an OR gate, the output of the last stage flip-flop (not shown) constituting the register 340f of the first switch control unit 340, and the second switch control unit ( The output of the last flip-flop 354 constituting the register 350f of 350 is ORed, and the result of the AND is output as the switch control signal OST_DONE. At this time, when the switch control signal OST_DONE is at a high level, this indicates that the operational amplifier is in a normal operation mode, and when the switch control signal OST_DONE is at a low level, it is in an offset removing operation mode.

The first control signal generator 310 includes a plurality of selection flip-flops 311 ˜ 316 that receive the control signals sn_p, rn_p, and te_p of the first switch controller 340. Here, the selection flip-flop 311 is composed of a multiplexer 311a and a flip-flop 311b. The multiplexer 311a applies the control signal swp <5> to the first input and applies the latch input signal TI to the second input. In addition, the multiplexer 311a selectively outputs one of the first and second input signals in response to the latch enable signal TE generated by the register 340a of the first switch controller 340. For example, if the latch enable signal TE is at a high level, the latch input signal TI is output. If the latch enable signal TE is at a low level, the control signal swp <5> is applied to the first input. Outputs The flip-flop 311b is reset in response to the reset signal rn5_p generated by the register 340a and is set by the set signal sn5_p. The flip-flop 311b also generates an output signal of the multiplexer 311a as a control signal swp <5> in response to the clock signal CLK. The remaining selection flip-flops 312 to 316 have a similar configuration to the selection flip-flop 311, and only the set signal, the reset signal, and the latch enable signals are different. Accordingly, control signals swp <5> to swp <0> for controlling the first switch unit 250 of the current switch are generated through the selected flip-flops 311 to 316.

The second control signal generator 320 includes a plurality of selection flip-flops 321 ˜ 326 that input control signals sn_n, rn_n, and te_n of the second switch controller 350. The configuration of each of the selected flip-flops 321 to 326 is similar to that of the selection flip-flops 311 to 316 of the first control signal generator 310. However, each set signal, reset signal, and latch enable signals are sequentially sn5_n to sn0_n, rn5_n to rn0_n, and te5_n to te0_n generated by the second switch controller 350. That is, the second control signal generator 320 controls the second switch unit 260 of the current switch through the selected flip-flops 321 to 326 (swn <5> to swn <0>). ) Is generated.

4 (a) to 4 (n) are waveform diagrams for explaining the operation of the offset control unit 12 shown in FIG. 3, and FIG. 4 (a) shows a clock signal CLK, and FIG. 4 (b). Denotes a reset signal resetn, and FIG. 4C illustrates a comparison clock signal COMPCLK. 4 (d) shows the constant output switch drive signal P_ACT, FIG. 4 (e) shows the set signal sn5_p, 4 (f) shows the reset signal rn5_p, and 4 (g). Represents a latch enable signal te5_p. 4 (h) to 4 (j) show the set signal sn4_p, the reset signal rn4_p and the latch enable signal te4_p, respectively. 4 (k) to 4 (m) show the set signal sn3_p, the reset signal rn3_p, and the latch enable signal te3_p, respectively. 4 illustrates the operation when the output signal of the comparator 14 (see FIG. 1) is at a high level.

FIG. 5 is a flowchart for explaining an offset elimination operation of the circuit shown in FIG. 1, in which an output signal of the comparator 14 of FIG. When the voltage of the negative output terminal VON is greater than that, the step of adjusting the output voltage by turning on / off the current switch 250 of the positive output terminal VOP (step 510), and the voltage of the negative output terminal VON is the positive output terminal VOP. In the case where the voltage is larger than the voltage, the output voltage is adjusted by turning on / off the current switch 260 of the negative output terminal (operation 550).

3 to 5, the offset voltage removing operation performed in the operational amplifier according to the present invention will be described in detail.

First, it is determined whether the voltage of the positive output terminal VOP is greater than the voltage of the negative output terminal VON by the output signal of the comparator 14 in the initial operation period after the power supply voltage VDD is applied (step 500). Initially all switches of the current switch 240 are in the turned off state, and the output of the comparator 14 determines whether the polarity of the offset is positive or negative. Here, the switch control signal OST_DONE remains initially at a low level, indicating that it operates in the offset voltage removal mode. If it is determined in step 500 that the voltage of the positive output terminal VOP is greater than the voltage of the negative output terminal VON, the constant output voltage is adjusted low by adjusting the current switches of the first switch unit 250 shown in FIG. Step 510). That is, when the power supply voltage VDD is applied, the switch driver 330 enables the comparison clock signal COMPCLK of FIG. 4C to a high level by delaying the power supply voltage VDD for a predetermined time. In addition, the switch driving signal SW_ACT is enabled after the comparison clock signal COMPCLK is enabled. At this time, the output signal Q of the flip-flop 304 becomes high level, and as a result, the constant output switch driving signal P_ACT is generated. When the constant output switch driving signal P_ACT is generated, the register 341a of the first switch controller 340 of FIG. 3 is in response to the clock signal CLK shown in FIG. 4A. The reset signal rn5_p is generated. In addition, the reset signal rn5_p is generated and the set signal sn5_p is enabled. Accordingly, as shown in FIG. 4E, the control signal swp <5> is enabled during the period in which the set signal sn5_p maintains the low level, and the switch swp <5> connected to the control signal swp <5>. ) Is driven. Referring to FIG. 5, it is assumed that I is 5. Therefore, when it is determined in step 500 that the voltage of the positive output terminal is greater than the voltage of the negative output terminal, the i-th switch, that is, swp5 is turned on (step 512). A section P45 of FIG. 4D shows a section in which the switch swp5 is turned on. Here, the current switch swp5 of FIG. 2 represents NMOS transistors MN31 and MN37 of the first switch unit 250. That is, in step 512, the current switch swp5 connected to the control signal swp <5> is turned on, and the voltage of the constant output terminal VOP is adjusted to be lower than the previous state. At this time, when the latch enable signal te5_p of FIG. 4G is applied from the AND gate 346 of the register 340a, the latch input signal TI output from the first comparator 300 of FIG. 3. Is applied to the selection flip-flop 311 of the first control signal generator 310. Accordingly, the changed output signal C_OUT of the comparator 14 is latched to the selection flip-flop 311 of the first control signal generator 310 through the Schmitt trigger 302 and the multiplexer 308. A period P35 of FIG. 4G illustrates a period in which the output signal C_OUTD of the Schmitt trigger 302 changed due to the driving of the switch swp5 is latched. At this point, the output signal of the comparator 14 determines whether the voltage of the positive output terminal VOP is lower than the voltage of the negative output terminal VON (step 514). If it is determined that the voltage of the constant output terminal VOP is still higher, the current switch swp5 remains turned on (step 516), and the next step, i-th current switch, that is, swp4 is driven. (Step 520). However, when the voltage of the negative output terminal is greater in step 514, the current switch swp5 is turned off, and the current switch swp <4> connected to the control signal swp <4> is driven. That is, the output signal of the flip-flop 344 of the first switch controller 340 is applied to the data input of the first flip-flop (not shown) of the register 340b. Therefore, the register 340b enables the set signal sn4_p of FIG. 4 (h) and the reset signal rn4_p of FIG. 4 (i) in response to the clock signal CLK, and drives the switch swp4. (Step 520). Section P44 of FIG. 4H shows a section in which the switch sw4 is turned on. That is, when the switch swp5 is turned on in accordance with the output signal of the comparator 14, since the voltage change range is too large, the large current switch swp5 is turned off (step 518). Therefore, instead of the current switch swp5, the current switch swp4 having a transistor size 1/2 having a smaller width is driven (step 520). In addition, the section P34 of FIG. 4 (j) shows a section in which the output signal C_OUTD of the Schmitt trigger 302 is latched by the latch enable signal te4_p. After operation 520, it is again compared whether the voltage of the positive output terminal VOP is greater than the voltage of the negative output terminal VON (operation 522). If it is determined in step 522 that the voltage of the positive output terminal VOP continues to be greater than the voltage of the negative output terminal VON, the drive of the current switch swp4 is maintained (step 524), and the current composed of the transistor of the smaller size is maintained. The switch swp3 is driven (operation 528). However, if it is determined in step 522 that the voltage of the positive output terminal VOP is smaller than the voltage of the negative output terminal VON, the current switch swp4 is turned off (step 526), and the current switch swp3 is driven (step 528). step). When this process is repeated and driving to the current switch swp0 connected to the control signal swp <0> is completed, it is determined whether the voltage of the positive output terminal VOP is greater than the voltage of the negative output terminal VON (step 532). At this time, if it is determined that the voltage of the positive output terminal is greater than the voltage of the negative output terminal, swp0 continues to be driven (operation 534). If it is determined in step 532 that the voltage of the positive output terminal VOP is smaller than the voltage of the negative output terminal VON, the current switch swpo is turned off (step 536). Through this process, the voltage of the positive output terminal VOP and the voltage of the negative output terminal VON are controlled to be the same.

On the other hand, when it is determined in step 500 that the voltage of the negative output terminal VON is greater than the voltage of the positive output terminal VOP, the voltage of the output terminal VON is adjusted to be low to control the voltage of the output terminal to be the same (550). step). First, in order to adjust the voltage of the negative output terminal VON low, the largest switch among the current switches of the second switch unit 260, that is, swn i is driven (step 552). In FIG. 2, the current switch swni becomes transistors MN49 and MN43 that are turned on and off by the control signal swn <5>. Therefore, after the current switch swn5 is driven in operation 552, the output signal C_OUT of the comparator 14 (see FIG. 1) is again determined to determine whether the voltage of the positive output terminal VOP is greater than the voltage of the negative output terminal VON. Are compared (step 554). That is, steps 554 to 576 of FIG. 5 are performed in a similar process to steps 514 to 534 in step 510. Since the current switches swn5 to swn0 for voltage regulation of the negative output terminal VON are turned on / off, not the constant output terminal VOP, detailed description thereof will be omitted.

Therefore, through this process, the voltage of the negative output terminal VON is adjusted to be equal to the voltage of the positive output terminal VOP. At this time, the output signal of the last flip-flop (not shown) constituting the register 340f of the first switch control unit 340 or the last flip-flop 354 constituting the register 350f of the second switch control unit 350. Is changed to a high level, the switch control signal OST_DONE becomes a high level. At this time, the operational amplifier is switched from the offset voltage cancellation mode to the normal operation mode.

6 is a diagram illustrating a result of offset voltage removal of an operational amplifier according to the present invention, wherein reference numeral 62 denotes a voltage of the positive output terminal VOP and 64 denotes a voltage of the negative output terminal VON.

That is, as shown in Figure 6, the amount of current flowing from the output terminals (VOP, VON) to the ground (VSS) is adjusted, thereby the voltage 62 of the positive output terminal VOP and the voltage 64 of the negative output terminal VON. This is regulated. Thus, the offset voltage that was generated early in the operation of the operational amplifier can be eliminated.

According to the present invention, when an offset is generated at the output terminal of the operational amplifier, it can be removed by itself in the offset voltage cancellation mode at the beginning of operation. Therefore, since the operational amplifier operates normally with the offset removed, there is an effect that an accurate amplification output can be obtained.

Claims (3)

Differentially amplifies the voltage applied through the positive input terminal and the voltage applied through the negative input terminal, and outputs the result of the amplification through the positive output terminal and the negative output terminal, respectively, and includes a current switch unit therein, n (>) 1) a differential amplifier for adjusting an output voltage in response to a predetermined first control signal and a second control signal represented by bits; In response to a predetermined switch control signal in a normal operation mode, a switch is connected to connect an external positive / negative input terminal and a positive / negative input terminal of the differential amplifier. An input switch unit for switching terminals to be connected to each other; A comparator for comparing a voltage output from the positive output terminal of the differential amplifier and a voltage output from the sub output terminal of the differential amplifier and generating a comparison output signal corresponding to the compared result; And And an offset controller configured to generate the switch control signal and the first and second control signals in response to the comparison output signal output from the comparator and a reset signal and a clock signal applied from the outside. . The method of claim 1, wherein the differential amplifier, A first switch unit and a second switch unit inside the current switch unit; The first switch unit includes a plurality of transistors each of which is sequentially reduced in size by a predetermined number, and adjusts the voltage of the positive output terminal of the differential amplifier unit low in response to the first control signal, And the second switch unit includes a plurality of transistors each of which is sequentially reduced in size by a predetermined multiple, and adjusts a voltage of the sub output terminal of the differential amplifier unit to be low in response to the second control signal. The method of claim 2, wherein the offset control unit, A first comparison unit configured to input the comparison output signal output from the comparator, a predetermined comparison clock signal, and generate a latch input signal and first and second comparison signals for latching the comparison output signal; The power supply voltage is delayed in response to the clock signal for a predetermined time, the comparison clock signal and the switch driving signal are generated based on the delayed result, and the first and second comparison signals are combined with the switch driving signal to output a constant output. A switch driver generating a switch driving signal and a negative output switch driving signal; Generating a first set signal, a first reset signal, and a first latch enable signal in response to the constant output switch driving signal to control the first switch unit for adjusting a voltage of the positive output terminal of the differential amplifier; 1 switch control unit; Generating a second set signal, a second reset signal, and a second latch enable signal in response to the sub output switch driving signal to control the second switch unit for adjusting a voltage of the sub output terminal of the differential amplifier; 2 switch control unit; A switch control signal output unit implemented as a logic gate and configured to logically combine an output signal of the first switch controller and an output signal of the second switch controller to output the switch control signal; A first control signal generator configured to generate the first control signal, including a plurality of selection flip-flops that use the output signals of the first switch controller as a control input; And And a second control signal generator configured to generate the second control signal, including a plurality of selected flip-flops that use the output signals of the second switch controller as control inputs.